Dima Zavin | 03cf431 | 2009-01-23 16:38:30 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2008, Google Inc. |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * * Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer. |
| 10 | * * Redistributions in binary form must reproduce the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer in |
| 12 | * the documentation and/or other materials provided with the |
| 13 | * distribution. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 16 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 17 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 18 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 19 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 20 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 21 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 22 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 23 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 24 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 25 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 26 | * SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #ifndef __PLATFORM_MSM_SHARED_NAND_H |
| 30 | #define __PLATFORM_MSM_SHARED_NAND_H |
| 31 | |
Ajay Dudani | 232ce81 | 2009-12-02 00:14:11 -0800 | [diff] [blame] | 32 | #ifdef PLATFORM_MSM7X30 |
| 33 | #define MSM_NAND_BASE 0xA0200000 |
Kinson Chik | 18e3633 | 2011-08-15 10:07:28 -0700 | [diff] [blame] | 34 | #elif PLATFORM_MDM9X15 |
| 35 | #define MSM_NAND_BASE 0x1B400000 |
Ajay Dudani | 232ce81 | 2009-12-02 00:14:11 -0800 | [diff] [blame] | 36 | #else |
Dima Zavin | 03cf431 | 2009-01-23 16:38:30 -0800 | [diff] [blame] | 37 | #define MSM_NAND_BASE 0xA0A00000 |
Ajay Dudani | 232ce81 | 2009-12-02 00:14:11 -0800 | [diff] [blame] | 38 | #endif |
Murali Nalajala | a8c94c6 | 2010-03-05 20:24:30 +0530 | [diff] [blame] | 39 | |
| 40 | #define MSM_NAND_NC01_BASE 0xA0240000 |
| 41 | #define MSM_NAND_NC10_BASE 0xA0280000 |
| 42 | #define MSM_NAND_NC11_BASE 0xA02C0000 |
| 43 | #define EBI2_REG_BASE 0xA0000000 |
| 44 | |
| 45 | #define NC01(off) (MSM_NAND_NC01_BASE + (off)) |
| 46 | #define NC10(off) (MSM_NAND_NC10_BASE + (off)) |
| 47 | #define NC11(off) (MSM_NAND_NC11_BASE + (off)) |
| 48 | #define EBI2_REG(off) (EBI2_REG_BASE + (off)) |
Dima Zavin | 03cf431 | 2009-01-23 16:38:30 -0800 | [diff] [blame] | 49 | |
| 50 | #define NAND_REG(off) (MSM_NAND_BASE + (off)) |
| 51 | |
| 52 | #define NAND_FLASH_CMD NAND_REG(0x0000) |
| 53 | #define NAND_ADDR0 NAND_REG(0x0004) |
| 54 | #define NAND_ADDR1 NAND_REG(0x0008) |
| 55 | #define NAND_FLASH_CHIP_SELECT NAND_REG(0x000C) |
| 56 | #define NAND_EXEC_CMD NAND_REG(0x0010) |
| 57 | #define NAND_FLASH_STATUS NAND_REG(0x0014) |
| 58 | #define NAND_BUFFER_STATUS NAND_REG(0x0018) |
| 59 | #define NAND_DEV0_CFG0 NAND_REG(0x0020) |
| 60 | #define NAND_DEV0_CFG1 NAND_REG(0x0024) |
| 61 | #define NAND_DEV1_CFG0 NAND_REG(0x0030) |
| 62 | #define NAND_DEV1_CFG1 NAND_REG(0x0034) |
Shashank Mittal | c20b5a1 | 2009-11-18 19:35:30 -0800 | [diff] [blame] | 63 | #define NAND_SFLASHC_CMD NAND_REG(0x0038) |
| 64 | #define NAND_SFLASHC_EXEC_CMD NAND_REG(0x003C) |
Dima Zavin | 03cf431 | 2009-01-23 16:38:30 -0800 | [diff] [blame] | 65 | #define NAND_READ_ID NAND_REG(0x0040) |
| 66 | #define NAND_READ_STATUS NAND_REG(0x0044) |
| 67 | #define NAND_CONFIG_DATA NAND_REG(0x0050) |
| 68 | #define NAND_CONFIG NAND_REG(0x0054) |
| 69 | #define NAND_CONFIG_MODE NAND_REG(0x0058) |
| 70 | #define NAND_CONFIG_STATUS NAND_REG(0x0060) |
| 71 | #define NAND_MACRO1_REG NAND_REG(0x0064) |
| 72 | #define NAND_XFR_STEP1 NAND_REG(0x0070) |
| 73 | #define NAND_XFR_STEP2 NAND_REG(0x0074) |
| 74 | #define NAND_XFR_STEP3 NAND_REG(0x0078) |
| 75 | #define NAND_XFR_STEP4 NAND_REG(0x007C) |
| 76 | #define NAND_XFR_STEP5 NAND_REG(0x0080) |
| 77 | #define NAND_XFR_STEP6 NAND_REG(0x0084) |
| 78 | #define NAND_XFR_STEP7 NAND_REG(0x0088) |
Shashank Mittal | c20b5a1 | 2009-11-18 19:35:30 -0800 | [diff] [blame] | 79 | #define NAND_GENP_REG0 NAND_REG(0x0090) |
| 80 | #define NAND_GENP_REG1 NAND_REG(0x0094) |
| 81 | #define NAND_GENP_REG2 NAND_REG(0x0098) |
| 82 | #define NAND_GENP_REG3 NAND_REG(0x009C) |
| 83 | #define NAND_SFLASHC_STATUS NAND_REG(0x001C) |
Dima Zavin | 03cf431 | 2009-01-23 16:38:30 -0800 | [diff] [blame] | 84 | #define NAND_DEV_CMD0 NAND_REG(0x00A0) |
| 85 | #define NAND_DEV_CMD1 NAND_REG(0x00A4) |
| 86 | #define NAND_DEV_CMD2 NAND_REG(0x00A8) |
| 87 | #define NAND_DEV_CMD_VLD NAND_REG(0x00AC) |
| 88 | #define NAND_EBI2_MISR_SIG_REG NAND_REG(0x00B0) |
Shashank Mittal | c20b5a1 | 2009-11-18 19:35:30 -0800 | [diff] [blame] | 89 | #define NAND_ADDR2 NAND_REG(0x00C0) |
| 90 | #define NAND_ADDR3 NAND_REG(0x00C4) |
| 91 | #define NAND_ADDR4 NAND_REG(0x00C8) |
| 92 | #define NAND_ADDR5 NAND_REG(0x00CC) |
| 93 | #define NAND_DEV_CMD3 NAND_REG(0x00D0) |
| 94 | #define NAND_DEV_CMD4 NAND_REG(0x00D4) |
| 95 | #define NAND_DEV_CMD5 NAND_REG(0x00D8) |
| 96 | #define NAND_DEV_CMD6 NAND_REG(0x00DC) |
| 97 | #define NAND_SFLASHC_BURST_CFG NAND_REG(0x00E0) |
| 98 | #define NAND_ADDR6 NAND_REG(0x00E4) |
Dima Zavin | 03cf431 | 2009-01-23 16:38:30 -0800 | [diff] [blame] | 99 | #define NAND_EBI2_ECC_BUF_CFG NAND_REG(0x00F0) |
| 100 | #define NAND_FLASH_BUFFER NAND_REG(0x0100) |
Channagoud Kadabi | 404a706 | 2011-03-21 19:27:50 +0530 | [diff] [blame] | 101 | #define NAND_HW_INFO NAND_REG(0x00FC) |
Dima Zavin | 03cf431 | 2009-01-23 16:38:30 -0800 | [diff] [blame] | 102 | |
| 103 | /* device commands */ |
| 104 | |
| 105 | #define NAND_CMD_SOFT_RESET 0x01 |
| 106 | #define NAND_CMD_PAGE_READ 0x32 |
| 107 | #define NAND_CMD_PAGE_READ_ECC 0x33 |
| 108 | #define NAND_CMD_PAGE_READ_ALL 0x34 |
| 109 | #define NAND_CMD_SEQ_PAGE_READ 0x15 |
| 110 | #define NAND_CMD_PRG_PAGE 0x36 |
| 111 | #define NAND_CMD_PRG_PAGE_ECC 0x37 |
| 112 | #define NAND_CMD_PRG_PAGE_ALL 0x39 |
| 113 | #define NAND_CMD_BLOCK_ERASE 0x3A |
| 114 | #define NAND_CMD_FETCH_ID 0x0B |
| 115 | #define NAND_CMD_STATUS 0x0C |
| 116 | #define NAND_CMD_RESET 0x0D |
| 117 | |
Shashank Mittal | c20b5a1 | 2009-11-18 19:35:30 -0800 | [diff] [blame] | 118 | /* Sflash Commands */ |
| 119 | |
| 120 | #define NAND_SFCMD_DATXS 0x0 |
| 121 | #define NAND_SFCMD_CMDXS 0x1 |
| 122 | #define NAND_SFCMD_BURST 0x0 |
| 123 | #define NAND_SFCMD_ASYNC 0x1 |
| 124 | #define NAND_SFCMD_ABORT 0x1 |
| 125 | #define NAND_SFCMD_REGRD 0x2 |
| 126 | #define NAND_SFCMD_REGWR 0x3 |
| 127 | #define NAND_SFCMD_INTLO 0x4 |
| 128 | #define NAND_SFCMD_INTHI 0x5 |
| 129 | #define NAND_SFCMD_DATRD 0x6 |
| 130 | #define NAND_SFCMD_DATWR 0x7 |
| 131 | |
Shashank Mittal | c20b5a1 | 2009-11-18 19:35:30 -0800 | [diff] [blame] | 132 | #define SFLASH_PREPCMD(numxfr, offval, delval, trnstp, mode, opcode) \ |
| 133 | ((numxfr<<20)|(offval<<12)|(delval<<6)|(trnstp<<5)|(mode<<4)|opcode) |
| 134 | |
| 135 | #define SFLASH_BCFG 0x20100327 |
| 136 | |
| 137 | #define CLEAN_DATA_32 0xFFFFFFFF |
| 138 | #define CLEAN_DATA_16 0xFFFF |
| 139 | |
| 140 | /* Onenand addresses */ |
| 141 | |
| 142 | #define ONENAND_MANUFACTURER_ID 0xF000 |
| 143 | #define ONENAND_DEVICE_ID 0xF001 |
| 144 | #define ONENAND_VERSION_ID 0xF002 |
| 145 | #define ONENAND_DATA_BUFFER_SIZE 0xF003 |
| 146 | #define ONENAND_BOOT_BUFFER_SIZE 0xF004 |
| 147 | #define ONENAND_AMOUNT_OF_BUFFERS 0xF005 |
| 148 | #define ONENAND_TECHNOLOGY 0xF006 |
| 149 | #define ONENAND_START_ADDRESS_1 0xF100 |
| 150 | #define ONENAND_START_ADDRESS_2 0xF101 |
| 151 | #define ONENAND_START_ADDRESS_3 0xF102 |
| 152 | #define ONENAND_START_ADDRESS_4 0xF103 |
| 153 | #define ONENAND_START_ADDRESS_5 0xF104 |
| 154 | #define ONENAND_START_ADDRESS_6 0xF105 |
| 155 | #define ONENAND_START_ADDRESS_7 0xF106 |
| 156 | #define ONENAND_START_ADDRESS_8 0xF107 |
| 157 | #define ONENAND_START_BUFFER 0xF200 |
| 158 | #define ONENAND_COMMAND 0xF220 |
| 159 | #define ONENAND_SYSTEM_CONFIG_1 0xF221 |
| 160 | #define ONENAND_SYSTEM_CONFIG_2 0xF222 |
| 161 | #define ONENAND_CONTROLLER_STATUS 0xF240 |
| 162 | #define ONENAND_INTERRUPT_STATUS 0xF241 |
| 163 | #define ONENAND_START_BLOCK_ADDRESS 0xF24C |
| 164 | #define ONENAND_WRITE_PROT_STATUS 0xF24E |
| 165 | #define ONENAND_ECC_STATUS 0xFF00 |
| 166 | #define ONENAND_ECC_ERRPOS_MAIN0 0xFF01 |
| 167 | #define ONENAND_ECC_ERRPOS_SPARE0 0xFF02 |
| 168 | #define ONENAND_ECC_ERRPOS_MAIN1 0xFF03 |
| 169 | #define ONENAND_ECC_ERRPOS_SPARE1 0xFF04 |
| 170 | #define ONENAND_ECC_ERRPOS_MAIN2 0xFF05 |
| 171 | #define ONENAND_ECC_ERRPOS_SPARE2 0xFF06 |
| 172 | #define ONENAND_ECC_ERRPOS_MAIN3 0xFF07 |
| 173 | #define ONENAND_ECC_ERRPOS_SPARE3 0xFF08 |
| 174 | |
Shashank Mittal | c20b5a1 | 2009-11-18 19:35:30 -0800 | [diff] [blame] | 175 | /* Onenand commands */ |
| 176 | |
| 177 | #define ONENAND_CMDLOAD 0x0000 |
| 178 | #define ONENAND_CMDLOADSPARE 0x0013 |
| 179 | #define ONENAND_CMDPROG 0x0080 |
| 180 | #define ONENAND_CMDPROGSPARE 0x001A |
| 181 | #define ONENAND_CMDERAS 0x0094 |
| 182 | |
| 183 | #define ONENAND_SYSCFG1_ECCENA 0x40E0 |
| 184 | #define ONENAND_SYSCFG1_ECCDIS 0x41E0 |
| 185 | #define ONENAND_CLRINTR 0x0000 |
| 186 | #define ONENAND_STARTADDR1_RES 0x07FF |
| 187 | #define ONENAND_STARTADDR3_RES 0x07FF |
| 188 | |
| 189 | #define DEVICE_FLASHCORE_0 0 |
| 190 | #define DEVICE_BUFFERRAM_0 0 |
| 191 | #define DATARAM0_0 0x8 |
| 192 | |
Shashank Mittal | 83d16d0 | 2009-11-18 16:54:42 -0800 | [diff] [blame] | 193 | /* Flash type */ |
| 194 | #define FLASH_UNKNOWN_DEVICE 0x00 |
| 195 | #define FLASH_NAND_DEVICE 0x01 |
| 196 | #define FLASH_8BIT_NAND_DEVICE 0x01 |
| 197 | #define FLASH_16BIT_NAND_DEVICE 0x02 |
| 198 | #define FLASH_ONENAND_DEVICE 0x03 |
| 199 | |
Murali Nalajala | a8c94c6 | 2010-03-05 20:24:30 +0530 | [diff] [blame] | 200 | #define EBI2_CFG_REG EBI2_REG(0x0004) |
| 201 | #define EBI2_NAND_ADM_MUX EBI2_REG(0x005C) |
| 202 | #define EBI2_CHIP_SELECT_CFG0 EBI2_REG(0x0000) |
| 203 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 204 | #endif /* __PLATFORM_MSM_SHARED_NAND_H */ |