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Joonwoo Park451dca32014-04-02 11:47:03 -07001/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
anisha agarwaldd04af62014-11-17 10:57:49 -080029#ifndef _PLATFORM_MDM9640_IOMAP_H_
30#define _PLATFORM_MDM9640_IOMAP_H_
Joonwoo Park451dca32014-04-02 11:47:03 -070031
32/* NAND */
33#define MSM_NAND_BASE 0x079B0000
34/* NAND BAM */
35#define MSM_NAND_BAM_BASE 0x07984000
36
37#define APPS_SS_BASE 0x0B000000
38
Channagoud Kadabi1b69e482014-09-23 15:20:22 -070039#define MSM_IOMAP_BASE 0x00000000
40#define MSM_IOMAP_END 0x80000000
Joonwoo Park451dca32014-04-02 11:47:03 -070041
42#define SYSTEM_IMEM_BASE 0x08600000
43#define MSM_SHARED_IMEM_BASE 0x08600000
44
45#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
46#define BS_INFO_OFFSET (0x6B0)
47#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
48#define SDRAM_START_ADDR 0x80000000
49
Joonwoo Parkb574b8a2014-08-25 15:41:14 -070050#define MSM_SHARED_BASE 0x87E80000
Joonwoo Park451dca32014-04-02 11:47:03 -070051
52#define MSM_GIC_DIST_BASE APPS_SS_BASE
53#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
54#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
55#define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000)
56#define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE
57
58#define PERIPH_SS_BASE 0x07800000
59
60#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
61#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
62
63/* SDHCI */
64#define SDCC_MCI_HC_MODE (0x00000078)
65#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
66#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
67#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
68#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
69#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000)
70#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000)
Channagoud Kadabi1b69e482014-09-23 15:20:22 -070071#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x000B1000)
Joonwoo Park451dca32014-04-02 11:47:03 -070072#define MSM_USB30_BASE 0x08A00000
73#define MSM_USB30_QSCRATCH_BASE 0x08AF8800
74
75#define CLK_CTL_BASE 0x1800000
76
77#define SPMI_BASE 0x02000000
78#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
79#define SPMI_PIC_BASE (SPMI_BASE + 0x01800000)
80#define PMIC_ARB_CORE 0x200F000
81
82#define TLMM_BASE_ADDR 0x1000000
83#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
84#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x00000004 + (x)*0x1000)
85
86#define MPM2_MPM_CTRL_BASE 0x004A0000
87#define MPM2_MPM_PS_HOLD 0x004AB000
88#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000
89
90/* CRYPTO ENGINE */
91#define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000)
92#define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004)
93#define GCC_0RYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008)
94#define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C)
95#define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020)
96#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
97/* GPLL */
98#define GPLL0_STATUS (CLK_CTL_BASE + 0x21000)
99#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
100#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
101
102/* SDCC */
103#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000)
104#define SDCC1_BCR (CLK_CTL_BASE + 0x42000)
105#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x42018)
106#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4201C)
107#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x42004)
108#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x42008)
109#define SDCC1_M (CLK_CTL_BASE + 0x4200C)
110#define SDCC1_N (CLK_CTL_BASE + 0x42010)
111#define SDCC1_D (CLK_CTL_BASE + 0x42014)
112
113/* UART */
114#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
115#define BLSP1_UART1_APPS_CBCR (CLK_CTL_BASE + 0x203C)
116#define BLSP1_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2044)
117#define BLSP1_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0x2048)
118#define BLSP1_UART1_APPS_M (CLK_CTL_BASE + 0x204C)
119#define BLSP1_UART1_APPS_N (CLK_CTL_BASE + 0x2050)
120#define BLSP1_UART1_APPS_D (CLK_CTL_BASE + 0x2054)
121
122#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C)
123#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034)
124#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038)
125#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x303C)
126#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x3040)
127#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x3044)
128
129#define BLSP1_UART3_APPS_CBCR (CLK_CTL_BASE + 0x403C)
130#define BLSP1_UART3_APPS_CMD_RCGR (CLK_CTL_BASE + 0x4044)
Channagoud Kadabi1b69e482014-09-23 15:20:22 -0700131#define BLSP1_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0x4048)
132#define BLSP1_UART3_APPS_M (CLK_CTL_BASE + 0x404C)
Joonwoo Park451dca32014-04-02 11:47:03 -0700133#define BLSP1_UART3_APPS_N (CLK_CTL_BASE + 0x4050)
134#define BLSP1_UART3_APPS_D (CLK_CTL_BASE + 0x4054)
135
136
137/* USB */
138#define USB_HS_BCR (CLK_CTL_BASE + 0x41000)
139#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x41004)
140#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008)
141#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
142#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
Joonwoo Park76641c72014-05-22 16:37:10 -0700143#define QUSB2A_PHY_BCR (CLK_CTL_BASE + 0x41028)
Joonwoo Park451dca32014-04-02 11:47:03 -0700144
145/* USB 3.0 clock */
146#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0x5E084)
147#define GCC_USB30_MASTER_CBCR (CLK_CTL_BASE + 0x5E000)
148#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0x5E078)
149#define GCC_USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0x5E00C)
150#define GCC_USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0x5E010)
151#define GCC_USB30_MASTER_M (CLK_CTL_BASE + 0x5E014)
152#define GCC_USB30_MASTER_N (CLK_CTL_BASE + 0x5E018)
153#define GCC_USB30_MASTER_D (CLK_CTL_BASE + 0x5E01C)
154
155/* USB 3.0 base */
156#define USB3_PIPE_CMD_RCGR (CLK_CTL_BASE + 0x5E048)
157#define USB3_PIPE_CFG_RCGR (CLK_CTL_BASE + 0x5E04C)
158#define USB_PHY_CFG_AHB_CBCR (CLK_CTL_BASE + 0x5E080)
159#define USB3_PIPE_CBCR (CLK_CTL_BASE + 0x5E040)
Channagoud Kadabi1b69e482014-09-23 15:20:22 -0700160#define USB3_PIPE_BCR (CLK_CTL_BASE + 0x5E03C)
Joonwoo Park451dca32014-04-02 11:47:03 -0700161
162#define USB3_AUX_CMD_RCGR (CLK_CTL_BASE + 0x5E05C)
163#define USB3_AUX_CFG_RCGR (CLK_CTL_BASE + 0x5E060)
164#define USB3_AUX_M (CLK_CTL_BASE + 0x5E064)
165#define USB3_AUX_N (CLK_CTL_BASE + 0x5E068)
166#define USB3_AUX_D (CLK_CTL_BASE + 0x5E06C)
167#define USB3_AUX_CBCR (CLK_CTL_BASE + 0x5E044)
168
169/* USB 3.0 phy */
170#define USB3_PHY_BCR (CLK_CTL_BASE + 0x0005E034)
171
Joonwoo Park39aed062014-06-09 17:00:07 -0700172/* QUSB2 PHY */
173#define QUSB2_PHY_BASE 0x00079000
174#define QUSB2PHY_PORT_POWERDOWN (QUSB2_PHY_BASE + 0x000000B4)
175#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x00041028)
anisha agarwal4ddb64b2014-08-13 14:03:08 -0700176#define QUSB2PHY_PORT_UTMI_CTRL2 (QUSB2_PHY_BASE + 0x000000C4)
177#define QUSB2PHY_PORT_TUNE1 (QUSB2_PHY_BASE + 0x00000080)
178#define QUSB2PHY_PORT_TUNE2 (QUSB2_PHY_BASE + 0x00000084)
179#define QUSB2PHY_PORT_TUNE3 (QUSB2_PHY_BASE + 0x00000088)
180#define QUSB2PHY_PORT_TUNE4 (QUSB2_PHY_BASE + 0x0000008C)
Joonwoo Park39aed062014-06-09 17:00:07 -0700181
Joonwoo Park451dca32014-04-02 11:47:03 -0700182/* SS QMP (Qulacomm Multi Protocol) */
183#define QMP_PHY_BASE 0x78000
184
185/* QMP register offset */
186#define PLATFORM_QMP_OFFSET 0x8
187
188/* Boot config */
189#define SEC_CTRL_CORE_BASE 0x00058000
190#define BOOT_CONFIG_OFFSET 0x0000602C
191#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET)
192
anisha agarwalffb78ab2014-11-18 15:20:31 -0800193/* QPIC DISPLAY */
194#define QPIC_BASE 0x7980000
195#define APCS_ALIAS0_IPC_INTERRUPT 0xB011008
Joonwoo Park451dca32014-04-02 11:47:03 -0700196#endif