Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2013, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <platform/iomap.h> |
| 30 | #include <platform/irqs.h> |
| 31 | #include <platform/interrupts.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <kernel/event.h> |
| 34 | #include <target.h> |
| 35 | #include <string.h> |
| 36 | #include <stdlib.h> |
| 37 | #include <bits.h> |
| 38 | #include <debug.h> |
| 39 | #include <sdhci.h> |
| 40 | |
| 41 | |
| 42 | /* |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 43 | * Function: sdhci error status enable |
| 44 | * Arg : Host structure |
| 45 | * Return : None |
| 46 | * Flow: : Enable command error status |
| 47 | */ |
| 48 | static void sdhci_error_status_enable(struct sdhci_host *host) |
| 49 | { |
| 50 | /* Enable all interrupt status */ |
| 51 | REG_WRITE16(host, SDHCI_NRML_INT_STS_EN, SDHCI_NRML_INT_STS_EN_REG); |
| 52 | REG_WRITE16(host, SDHCI_ERR_INT_STS_EN, SDHCI_ERR_INT_STS_EN_REG); |
| 53 | /* Enable all interrupt signal */ |
| 54 | REG_WRITE16(host, SDHCI_NRML_INT_SIG_EN, SDHCI_NRML_INT_SIG_EN_REG); |
| 55 | REG_WRITE16(host, SDHCI_ERR_INT_SIG_EN, SDHCI_ERR_INT_SIG_EN_REG); |
| 56 | } |
| 57 | |
| 58 | /* |
| 59 | * Function: sdhci clock supply |
| 60 | * Arg : Host structure |
| 61 | * Return : 0 on Success, 1 on Failure |
| 62 | * Flow: : 1. Calculate the clock divider |
| 63 | * 2. Set the clock divider |
| 64 | * 3. Check if clock stable |
| 65 | * 4. Enable Clock |
| 66 | */ |
| 67 | uint32_t sdhci_clk_supply(struct sdhci_host *host, uint32_t clk) |
| 68 | { |
| 69 | uint32_t div = 0; |
| 70 | uint32_t freq = 0; |
| 71 | uint16_t clk_val = 0; |
| 72 | |
| 73 | if (clk > host->caps.base_clk_rate) { |
| 74 | dprintf(CRITICAL, "Error: Requested clk freq is more than supported\n"); |
| 75 | return 1; |
| 76 | } |
| 77 | |
| 78 | if (clk == host->caps.base_clk_rate) |
| 79 | goto clk_ctrl; |
| 80 | |
| 81 | /* As per the sd spec div should be a multiplier of 2 */ |
| 82 | for (div = 2; div < SDHCI_CLK_MAX_DIV; div += 2) { |
| 83 | freq = host->caps.base_clk_rate / div; |
| 84 | if (freq <= clk) |
| 85 | break; |
| 86 | } |
| 87 | |
| 88 | div >>= 1; |
| 89 | |
| 90 | clk_ctrl: |
| 91 | /* As per the sdhci spec 3.0, bits 6-7 of the clock |
| 92 | * control registers will be mapped to bit 8-9, to |
| 93 | * support a 10 bit divider value. |
| 94 | * This is needed when the divider value overflows |
| 95 | * the 8 bit range. |
| 96 | */ |
| 97 | clk_val = ((div & SDHCI_SDCLK_FREQ_MASK) << SDHCI_SDCLK_FREQ_SEL); |
| 98 | clk_val |= ((div & SDHC_SDCLK_UP_BIT_MASK) >> SDHCI_SDCLK_FREQ_SEL) |
| 99 | << SDHCI_SDCLK_UP_BIT_SEL; |
| 100 | |
| 101 | clk_val |= SDHCI_INT_CLK_EN; |
| 102 | REG_WRITE16(host, clk_val, SDHCI_CLK_CTRL_REG); |
| 103 | |
| 104 | /* Check for clock stable */ |
| 105 | while (!(REG_READ16(host, SDHCI_CLK_CTRL_REG) & SDHCI_CLK_STABLE)); |
| 106 | |
| 107 | /* Now clock is stable, enable it */ |
| 108 | clk_val = REG_READ16(host, SDHCI_CLK_CTRL_REG); |
| 109 | clk_val |= SDHCI_CLK_EN; |
| 110 | REG_WRITE16(host, clk_val, SDHCI_CLK_CTRL_REG); |
| 111 | |
| 112 | host->cur_clk_rate = freq; |
| 113 | |
| 114 | return 0; |
| 115 | } |
| 116 | |
| 117 | /* |
| 118 | * Function: sdhci stop sdcc clock |
| 119 | * Arg : Host structure |
| 120 | * Return : 0 on Success, 1 on Failure |
| 121 | * Flow: : 1. Stop the clock |
| 122 | */ |
| 123 | static uint32_t sdhci_stop_sdcc_clk(struct sdhci_host *host) |
| 124 | { |
| 125 | uint32_t reg; |
| 126 | |
| 127 | reg = REG_READ32(host, SDHCI_PRESENT_STATE_REG); |
| 128 | |
| 129 | if (reg & (SDHCI_CMD_ACT | SDHCI_DAT_ACT)) { |
| 130 | dprintf(CRITICAL, "Error: SDCC command & data line are active\n"); |
| 131 | return 1; |
| 132 | } |
| 133 | |
| 134 | REG_WRITE16(host, SDHCI_CLK_DIS, SDHCI_CLK_CTRL_REG); |
| 135 | |
| 136 | return 0; |
| 137 | } |
| 138 | |
| 139 | /* |
| 140 | * Function: sdhci change frequency |
| 141 | * Arg : Host structure & clock value |
| 142 | * Return : 0 on Success, 1 on Failure |
| 143 | * Flow: : 1. Stop the clock |
| 144 | * 2. Star the clock with new frequency |
| 145 | */ |
| 146 | static uint32_t sdhci_change_freq_clk(struct sdhci_host *host, uint32_t clk) |
| 147 | { |
| 148 | if (sdhci_stop_sdcc_clk(host)) { |
| 149 | dprintf(CRITICAL, "Error: Card is busy, cannot change frequency\n"); |
| 150 | return 1; |
| 151 | } |
| 152 | |
| 153 | if (sdhci_clk_supply(host, clk)) { |
| 154 | dprintf(CRITICAL, "Error: cannot change frequency\n"); |
| 155 | return 1; |
| 156 | } |
| 157 | |
| 158 | return 0; |
| 159 | } |
| 160 | |
| 161 | /* |
| 162 | * Function: sdhci set bus power |
| 163 | * Arg : Host structure |
| 164 | * Return : None |
| 165 | * Flow: : 1. Set the voltage |
| 166 | * 2. Set the sd power control register |
| 167 | */ |
| 168 | static void sdhci_set_bus_power_on(struct sdhci_host *host) |
| 169 | { |
| 170 | uint8_t voltage; |
| 171 | |
| 172 | voltage = host->caps.voltage; |
| 173 | |
| 174 | voltage <<= SDHCI_BUS_VOL_SEL; |
Channagoud Kadabi | 8990251 | 2013-05-14 13:22:06 -0700 | [diff] [blame] | 175 | REG_WRITE8(host, voltage, SDHCI_PWR_CTRL_REG); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 176 | |
| 177 | voltage |= SDHCI_BUS_PWR_EN; |
| 178 | |
| 179 | REG_WRITE8(host, voltage, SDHCI_PWR_CTRL_REG); |
| 180 | |
| 181 | } |
| 182 | |
| 183 | /* |
| 184 | * Function: sdhci set SDR mode |
| 185 | * Arg : Host structure |
| 186 | * Return : None |
| 187 | * Flow: : 1. Disable the clock |
| 188 | * 2. Enable sdr mode |
| 189 | * 3. Enable the clock |
| 190 | * Details : SDR50/SDR104 mode is nothing but HS200 |
| 191 | * mode SDCC spec refers to it as SDR mode |
| 192 | * & emmc spec refers as HS200 mode. |
| 193 | */ |
| 194 | void sdhci_set_sdr_mode(struct sdhci_host *host) |
| 195 | { |
| 196 | uint16_t clk; |
| 197 | uint16_t ctrl = 0; |
| 198 | |
| 199 | /* Disable the clock */ |
| 200 | clk = REG_READ16(host, SDHCI_CLK_CTRL_REG); |
| 201 | clk &= ~SDHCI_CLK_EN; |
| 202 | REG_WRITE16(host, clk, SDHCI_CLK_CTRL_REG); |
| 203 | |
| 204 | /* Enable SDR50 mode: |
| 205 | * Right now we support only SDR50 mode which runs at |
| 206 | * 100 MHZ sdcc clock, we dont need tuning with SDR50 |
| 207 | * mode |
| 208 | */ |
| 209 | ctrl = REG_READ16(host, SDHCI_HOST_CTRL2_REG); |
| 210 | |
| 211 | /* Enable SDR50/SDR104 mode based on the controller |
| 212 | * capabilities. |
| 213 | */ |
| 214 | if (host->caps.sdr50_support) |
| 215 | ctrl |= SDHCI_SDR50_MODE_EN; |
| 216 | |
| 217 | REG_WRITE16(host, ctrl, SDHCI_HOST_CTRL2_REG); |
| 218 | |
| 219 | /* Run the clock back */ |
| 220 | sdhci_clk_supply(host, SDHCI_CLK_100MHZ); |
| 221 | } |
| 222 | |
| 223 | /* |
| 224 | * Function: sdhci set ddr mode |
| 225 | * Arg : Host structure |
| 226 | * Return : None |
| 227 | * Flow: : 1. Disable the clock |
| 228 | * 2. Enable DDR mode |
| 229 | * 3. Enable the clock |
| 230 | */ |
| 231 | void sdhci_set_ddr_mode(struct sdhci_host *host) |
| 232 | { |
| 233 | uint16_t clk; |
| 234 | uint16_t ctrl = 0; |
| 235 | |
| 236 | /* Disable the clock */ |
| 237 | clk = REG_READ16(host, SDHCI_CLK_CTRL_REG); |
| 238 | clk &= ~SDHCI_CLK_EN; |
| 239 | REG_WRITE16(host, clk, SDHCI_CLK_CTRL_REG); |
| 240 | |
| 241 | ctrl = REG_READ16(host, SDHCI_HOST_CTRL2_REG); |
| 242 | ctrl |= SDHCI_DDR_MODE_EN; |
| 243 | |
| 244 | /* Enalbe DDR mode */ |
| 245 | REG_WRITE16(host, ctrl, SDHCI_HOST_CTRL2_REG); |
| 246 | |
| 247 | /* Run the clock back */ |
| 248 | sdhci_clk_supply(host, host->cur_clk_rate); |
| 249 | } |
| 250 | |
| 251 | /* |
| 252 | * Function: sdhci set adma mode |
| 253 | * Arg : Host structure |
| 254 | * Return : None |
| 255 | * Flow: : Set adma mode |
| 256 | */ |
| 257 | static void sdhci_set_adma_mode(struct sdhci_host *host) |
| 258 | { |
| 259 | /* Select 32 Bit ADMA2 type */ |
| 260 | REG_WRITE8(host, SDHCI_ADMA_32BIT, SDHCI_HOST_CTRL1_REG); |
| 261 | } |
| 262 | |
| 263 | /* |
| 264 | * Function: sdhci set bus width |
| 265 | * Arg : Host & width |
| 266 | * Return : 0 on Sucess, 1 on Failure |
| 267 | * Flow: : Set the bus width for controller |
| 268 | */ |
| 269 | uint8_t sdhci_set_bus_width(struct sdhci_host *host, uint16_t width) |
| 270 | { |
| 271 | uint16_t reg = 0; |
| 272 | |
| 273 | reg = REG_READ8(host, SDHCI_HOST_CTRL1_REG); |
| 274 | |
| 275 | switch(width) { |
| 276 | case DATA_BUS_WIDTH_8BIT: |
| 277 | width = SDHCI_BUS_WITDH_8BIT; |
| 278 | break; |
| 279 | case DATA_BUS_WIDTH_4BIT: |
| 280 | width = SDHCI_BUS_WITDH_4BIT; |
| 281 | break; |
| 282 | case DATA_BUS_WIDTH_1BIT: |
| 283 | width = SDHCI_BUS_WITDH_1BIT; |
| 284 | break; |
| 285 | default: |
| 286 | dprintf(CRITICAL, "Bus width is invalid: %u\n", width); |
| 287 | return 1; |
| 288 | } |
| 289 | |
| 290 | REG_WRITE8(host, (reg | width), SDHCI_HOST_CTRL1_REG); |
| 291 | |
| 292 | return 0; |
| 293 | } |
| 294 | |
| 295 | /* |
| 296 | * Function: sdhci command err status |
| 297 | * Arg : Host structure |
| 298 | * Return : 0 on Sucess, 1 on Failure |
| 299 | * Flow: : Look for error status |
| 300 | */ |
| 301 | static uint8_t sdhci_cmd_err_status(struct sdhci_host *host) |
| 302 | { |
| 303 | uint32_t err; |
| 304 | |
| 305 | err = REG_READ16(host, SDHCI_ERR_INT_STS_REG); |
| 306 | |
| 307 | if (err & SDHCI_CMD_TIMEOUT_MASK) { |
| 308 | dprintf(CRITICAL, "Error: Command timeout error\n"); |
| 309 | return 1; |
| 310 | } else if (err & SDHCI_CMD_CRC_MASK) { |
| 311 | dprintf(CRITICAL, "Error: Command CRC error\n"); |
| 312 | return 1; |
| 313 | } else if (err & SDHCI_CMD_END_BIT_MASK) { |
| 314 | dprintf(CRITICAL, "Error: CMD end bit error\n"); |
| 315 | return 1; |
| 316 | } else if (err & SDHCI_CMD_IDX_MASK) { |
| 317 | dprintf(CRITICAL, "Error: Command Index error\n"); |
| 318 | return 1; |
| 319 | } else if (err & SDHCI_DAT_TIMEOUT_MASK) { |
| 320 | dprintf(CRITICAL, "Error: DATA time out error\n"); |
| 321 | return 1; |
| 322 | } else if (err & SDHCI_DAT_CRC_MASK) { |
| 323 | dprintf(CRITICAL, "Error: DATA CRC error\n"); |
| 324 | return 1; |
| 325 | } else if (err & SDHCI_DAT_END_BIT_MASK) { |
| 326 | dprintf(CRITICAL, "Error: DATA end bit error\n"); |
| 327 | return 1; |
| 328 | } else if (err & SDHCI_CUR_LIM_MASK) { |
| 329 | dprintf(CRITICAL, "Error: Current limit error\n"); |
| 330 | return 1; |
| 331 | } else if (err & SDHCI_AUTO_CMD12_MASK) { |
| 332 | dprintf(CRITICAL, "Error: Auto CMD12 error\n"); |
| 333 | return 1; |
| 334 | } else if (err & SDHCI_ADMA_MASK) { |
| 335 | dprintf(CRITICAL, "Error: ADMA error\n"); |
| 336 | return 1; |
| 337 | } |
| 338 | |
| 339 | return 0; |
| 340 | } |
| 341 | |
| 342 | /* |
| 343 | * Function: sdhci command complete |
| 344 | * Arg : Host & command structure |
| 345 | * Return : 0 on Sucess, 1 on Failure |
| 346 | * Flow: : 1. Check for command complete |
| 347 | * 2. Check for transfer complete |
| 348 | * 3. Get the command response |
| 349 | * 4. Check for errors |
| 350 | */ |
| 351 | static uint8_t sdhci_cmd_complete(struct sdhci_host *host, struct mmc_command *cmd) |
| 352 | { |
| 353 | uint8_t i; |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 354 | uint32_t retry = 0; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 355 | uint32_t int_status; |
| 356 | |
| 357 | do { |
| 358 | int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG); |
| 359 | int_status &= SDHCI_INT_STS_CMD_COMPLETE; |
| 360 | |
| 361 | if (int_status == SDHCI_INT_STS_CMD_COMPLETE) |
| 362 | break; |
| 363 | |
| 364 | retry++; |
| 365 | udelay(500); |
| 366 | if (retry == SDHCI_MAX_CMD_RETRY) { |
| 367 | dprintf(CRITICAL, "Error: Command never completed\n"); |
| 368 | goto err; |
| 369 | } |
| 370 | } while(1); |
| 371 | |
| 372 | /* Command is complete, clear the interrupt bit */ |
| 373 | REG_WRITE16(host, SDHCI_INT_STS_CMD_COMPLETE, SDHCI_NRML_INT_STS_REG); |
| 374 | |
| 375 | /* Copy the command response, |
| 376 | * The valid bits for R2 response are 0-119, & but the actual response |
| 377 | * is stored in bits 8-128. We need to move 8 bits of MSB of each |
| 378 | * response to register 8 bits of LSB of next response register. |
| 379 | * As: |
| 380 | * MSB 8 bits of RESP0 --> LSB 8 bits of RESP1 |
| 381 | * MSB 8 bits of RESP1 --> LSB 8 bits of RESP2 |
| 382 | * MSB 8 bits of RESP2 --> LSB 8 bits of RESP3 |
| 383 | */ |
| 384 | if (cmd->resp_type == SDHCI_CMD_RESP_R2) { |
| 385 | for (i = 0; i < 4; i++) { |
| 386 | cmd->resp[i] = REG_READ32(host, SDHCI_RESP_REG + (i * 4)); |
| 387 | cmd->resp[i] <<= SDHCI_RESP_LSHIFT; |
| 388 | |
| 389 | if (i != 0) |
| 390 | cmd->resp[i] |= (REG_READ32(host, SDHCI_RESP_REG + ((i-1) * 4)) >> SDHCI_RESP_RSHIFT); |
| 391 | } |
| 392 | } else |
| 393 | cmd->resp[0] = REG_READ32(host, SDHCI_RESP_REG); |
| 394 | |
| 395 | retry = 0; |
| 396 | |
| 397 | /* |
| 398 | * Clear the transfer complete interrupt |
| 399 | */ |
Channagoud Kadabi | 709ce1c | 2013-05-29 15:19:15 -0700 | [diff] [blame] | 400 | if (cmd->data_present || cmd->resp_type == SDHCI_CMD_RESP_R1B) { |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 401 | do { |
| 402 | int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG); |
| 403 | int_status &= SDHCI_INT_STS_TRANS_COMPLETE; |
| 404 | |
| 405 | if (int_status & SDHCI_INT_STS_TRANS_COMPLETE) |
| 406 | break; |
| 407 | |
| 408 | retry++; |
| 409 | udelay(1000); |
| 410 | if (retry == SDHCI_MAX_TRANS_RETRY) { |
| 411 | dprintf(CRITICAL, "Error: Transfer never completed\n"); |
| 412 | goto err; |
| 413 | } |
| 414 | } while(1); |
| 415 | |
| 416 | /* Transfer is complete, clear the interrupt bit */ |
| 417 | REG_WRITE16(host, SDHCI_INT_STS_TRANS_COMPLETE, SDHCI_NRML_INT_STS_REG); |
| 418 | } |
| 419 | |
| 420 | err: |
| 421 | /* Look for errors */ |
| 422 | int_status = REG_READ16(host, SDHCI_NRML_INT_STS_REG); |
| 423 | if (int_status & SDHCI_ERR_INT_STAT_MASK) { |
| 424 | if (sdhci_cmd_err_status(host)) { |
| 425 | dprintf(CRITICAL, "Error: Command completed with errors\n"); |
Channagoud Kadabi | 8990251 | 2013-05-14 13:22:06 -0700 | [diff] [blame] | 426 | /* Reset the command & Data line */ |
| 427 | REG_WRITE8(host, (SOFT_RESET_CMD | SOFT_RESET_DATA), SDHCI_RESET_REG); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 428 | return 1; |
| 429 | } |
| 430 | } |
| 431 | |
| 432 | /* Reset data & command line */ |
| 433 | if (cmd->data_present) |
| 434 | REG_WRITE8(host, (SOFT_RESET_CMD | SOFT_RESET_DATA), SDHCI_RESET_REG); |
| 435 | |
| 436 | return 0; |
| 437 | } |
| 438 | |
| 439 | /* |
| 440 | * Function: sdhci prep desc table |
| 441 | * Arg : Pointer data & length |
| 442 | * Return : Pointer to desc table |
| 443 | * Flow: : Prepare the adma table as per the sd spec v 3.0 |
| 444 | */ |
| 445 | static struct desc_entry *sdhci_prep_desc_table(void *data, uint32_t len) |
| 446 | { |
| 447 | struct desc_entry *sg_list; |
| 448 | uint32_t sg_len = 0; |
| 449 | uint32_t remain = 0; |
| 450 | uint32_t i; |
| 451 | uint32_t table_len = 0; |
| 452 | |
| 453 | if (len <= SDHCI_ADMA_DESC_LINE_SZ) { |
| 454 | /* Allocate only one descriptor */ |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 455 | sg_list = (struct desc_entry *) memalign(lcm(4, CACHE_LINE), ROUNDUP(sizeof(struct desc_entry), CACHE_LINE)); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 456 | |
| 457 | if (!sg_list) { |
| 458 | dprintf(CRITICAL, "Error allocating memory\n"); |
| 459 | ASSERT(0); |
| 460 | } |
| 461 | |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 462 | sg_list[0].addr = (uint32_t)data; |
Channagoud Kadabi | 942a8df | 2013-06-20 14:30:49 -0700 | [diff] [blame] | 463 | sg_list[0].len = (len < SDHCI_ADMA_DESC_LINE_SZ) ? len : (SDHCI_ADMA_DESC_LINE_SZ & 0xffff); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 464 | sg_list[0].tran_att = SDHCI_ADMA_TRANS_VALID | SDHCI_ADMA_TRANS_DATA |
| 465 | | SDHCI_ADMA_TRANS_END; |
| 466 | |
| 467 | arch_clean_invalidate_cache_range((addr_t)sg_list, sizeof(struct desc_entry)); |
| 468 | } else { |
| 469 | /* Calculate the number of entries in desc table */ |
| 470 | sg_len = len / SDHCI_ADMA_DESC_LINE_SZ; |
| 471 | remain = len - (sg_len * SDHCI_ADMA_DESC_LINE_SZ); |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 472 | |
| 473 | /* Allocate sg_len + 1 entries if there are remaining bytes at the end */ |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 474 | if (remain) |
| 475 | sg_len++; |
| 476 | |
| 477 | table_len = (sg_len * sizeof(struct desc_entry)); |
| 478 | |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 479 | sg_list = (struct desc_entry *) memalign(lcm(4, CACHE_LINE), ROUNDUP(table_len, CACHE_LINE)); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 480 | |
| 481 | if (!sg_list) { |
| 482 | dprintf(CRITICAL, "Error allocating memory\n"); |
| 483 | ASSERT(0); |
| 484 | } |
| 485 | |
| 486 | memset((void *) sg_list, 0, table_len); |
| 487 | |
| 488 | /* |
| 489 | * Prepare sglist in the format: |
| 490 | * ___________________________________________________ |
| 491 | * |Transfer Len | Transfer ATTR | Data Address | |
| 492 | * | (16 bit) | (16 bit) | (32 bit) | |
| 493 | * |_____________|_______________|_____________________| |
| 494 | */ |
| 495 | for (i = 0; i < (sg_len - 1); i++) { |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 496 | sg_list[i].addr = (uint32_t)data; |
Channagoud Kadabi | 942a8df | 2013-06-20 14:30:49 -0700 | [diff] [blame] | 497 | /* |
| 498 | * Length attribute is 16 bit value & max transfer size for one |
| 499 | * descriptor line is 65536 bytes, As per SD Spec3.0 'len = 0' |
| 500 | * implies 65536 bytes. Truncate the length to limit to 16 bit |
| 501 | * range. |
| 502 | */ |
| 503 | sg_list[i].len = (SDHCI_ADMA_DESC_LINE_SZ & 0xffff); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 504 | sg_list[i].tran_att = SDHCI_ADMA_TRANS_VALID | SDHCI_ADMA_TRANS_DATA; |
| 505 | data += SDHCI_ADMA_DESC_LINE_SZ; |
| 506 | len -= SDHCI_ADMA_DESC_LINE_SZ; |
| 507 | } |
| 508 | |
| 509 | /* Fill the last entry of the table with Valid & End |
| 510 | * attributes |
| 511 | */ |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 512 | sg_list[sg_len - 1].addr = (uint32_t)data; |
Channagoud Kadabi | 942a8df | 2013-06-20 14:30:49 -0700 | [diff] [blame] | 513 | sg_list[sg_len - 1].len = (len < SDHCI_ADMA_DESC_LINE_SZ) ? len : (SDHCI_ADMA_DESC_LINE_SZ & 0xffff); |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 514 | sg_list[sg_len - 1].tran_att = SDHCI_ADMA_TRANS_VALID | SDHCI_ADMA_TRANS_DATA | |
| 515 | SDHCI_ADMA_TRANS_END; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 516 | } |
| 517 | |
| 518 | arch_clean_invalidate_cache_range((addr_t)sg_list, table_len); |
| 519 | |
| 520 | return sg_list; |
| 521 | } |
| 522 | |
| 523 | /* |
| 524 | * Function: sdhci adma transfer |
| 525 | * Arg : Host structure & command stucture |
| 526 | * Return : Pointer to desc table |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 527 | * Flow : 1. Prepare descriptor table |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 528 | * 2. Write adma register |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 529 | * 3. Write block size & block count register |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 530 | */ |
| 531 | static struct desc_entry *sdhci_adma_transfer(struct sdhci_host *host, |
| 532 | struct mmc_command *cmd) |
| 533 | { |
| 534 | uint32_t num_blks = 0; |
| 535 | uint32_t sz; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 536 | void *data; |
| 537 | struct desc_entry *adma_addr; |
| 538 | |
| 539 | |
| 540 | num_blks = cmd->data.num_blocks; |
| 541 | data = cmd->data.data_ptr; |
| 542 | |
Channagoud Kadabi | 709ce1c | 2013-05-29 15:19:15 -0700 | [diff] [blame] | 543 | /* |
| 544 | * Some commands send data on DAT lines which is less |
| 545 | * than SDHCI_MMC_BLK_SZ, in that case trying to read |
| 546 | * more than the data sent by the card results in data |
| 547 | * CRC errors. To avoid such errors allow data to pass |
| 548 | * the required block size, if the block size is not |
| 549 | * passed use the default value |
| 550 | */ |
| 551 | if (cmd->data.blk_sz) |
| 552 | sz = num_blks * cmd->data.blk_sz; |
| 553 | else |
| 554 | sz = num_blks * SDHCI_MMC_BLK_SZ; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 555 | |
| 556 | /* Prepare adma descriptor table */ |
| 557 | adma_addr = sdhci_prep_desc_table(data, sz); |
| 558 | |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 559 | /* Write adma address to adma register */ |
| 560 | REG_WRITE32(host, (uint32_t) adma_addr, SDHCI_ADM_ADDR_REG); |
| 561 | |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 562 | /* Write the block size */ |
Channagoud Kadabi | 709ce1c | 2013-05-29 15:19:15 -0700 | [diff] [blame] | 563 | if (cmd->data.blk_sz) |
| 564 | REG_WRITE16(host, cmd->data.blk_sz, SDHCI_BLKSZ_REG); |
| 565 | else |
| 566 | REG_WRITE16(host, SDHCI_MMC_BLK_SZ, SDHCI_BLKSZ_REG); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 567 | |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 568 | /* |
| 569 | * Set block count in block count register |
| 570 | */ |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 571 | REG_WRITE16(host, num_blks, SDHCI_BLK_CNT_REG); |
| 572 | |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 573 | return adma_addr; |
| 574 | } |
| 575 | |
| 576 | /* |
| 577 | * Function: sdhci send command |
| 578 | * Arg : Host structure & command stucture |
| 579 | * Return : 0 on Success, 1 on Failure |
| 580 | * Flow: : 1. Prepare the command register |
| 581 | * 2. If data is present, prepare adma table |
| 582 | * 3. Run the command |
| 583 | * 4. Check for command results & take action |
| 584 | */ |
| 585 | uint32_t sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) |
| 586 | { |
| 587 | uint8_t retry = 0; |
| 588 | uint32_t resp_type = 0; |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 589 | uint16_t trans_mode = 0; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 590 | uint16_t present_state; |
| 591 | uint32_t flags; |
| 592 | struct desc_entry *sg_list = NULL; |
| 593 | |
| 594 | if (cmd->data_present) |
| 595 | ASSERT(cmd->data.data_ptr); |
| 596 | |
| 597 | /* |
| 598 | * Assert if the data buffer is not aligned to cache |
| 599 | * line size for read operations. |
| 600 | * For write operations this function assumes that |
| 601 | * the cache is already flushed by the caller. As |
| 602 | * the data buffer we receive for write operation |
| 603 | * may not be aligned to cache boundary due to |
| 604 | * certain image formats like sparse image. |
| 605 | */ |
| 606 | if (cmd->trans_mode == SDHCI_READ_MODE) |
| 607 | ASSERT(IS_CACHE_LINE_ALIGNED(cmd->data.data_ptr)); |
| 608 | |
| 609 | do { |
| 610 | present_state = REG_READ32(host, SDHCI_PRESENT_STATE_REG); |
| 611 | /* check if CMD & DAT lines are free */ |
| 612 | present_state &= SDHCI_STATE_CMD_DAT_MASK; |
| 613 | |
| 614 | if (!present_state) |
| 615 | break; |
| 616 | udelay(1000); |
| 617 | retry++; |
| 618 | if (retry == 10) { |
| 619 | dprintf(CRITICAL, "Error: CMD or DAT lines were never freed\n"); |
| 620 | return 1; |
| 621 | } |
| 622 | } while(1); |
| 623 | |
| 624 | switch(cmd->resp_type) { |
| 625 | case SDHCI_CMD_RESP_R1: |
| 626 | case SDHCI_CMD_RESP_R3: |
| 627 | case SDHCI_CMD_RESP_R6: |
| 628 | case SDHCI_CMD_RESP_R7: |
| 629 | /* Response of length 48 have 32 bits |
| 630 | * of response data stored in RESP0[0:31] |
| 631 | */ |
| 632 | resp_type = SDHCI_CMD_RESP_48; |
| 633 | break; |
| 634 | |
| 635 | case SDHCI_CMD_RESP_R2: |
| 636 | /* Response of length 136 have 120 bits |
| 637 | * of response data stored in RESP0[0:119] |
| 638 | */ |
| 639 | resp_type = SDHCI_CMD_RESP_136; |
| 640 | break; |
| 641 | |
| 642 | case SDHCI_CMD_RESP_R1B: |
| 643 | /* Response of length 48 have 32 bits |
| 644 | * of response data stored in RESP0[0:31] |
| 645 | * & set CARD_BUSY status if card is busy |
| 646 | */ |
| 647 | resp_type = SDHCI_CMD_RESP_48_BUSY; |
| 648 | break; |
| 649 | |
| 650 | case SDHCI_CMD_RESP_NONE: |
| 651 | resp_type = SDHCI_CMD_RESP_NONE; |
| 652 | break; |
| 653 | |
| 654 | default: |
| 655 | dprintf(CRITICAL, "Invalid response type for the command\n"); |
| 656 | return 1; |
| 657 | }; |
| 658 | |
| 659 | flags = (resp_type << SDHCI_CMD_RESP_TYPE_SEL_BIT); |
| 660 | flags |= (cmd->data_present << SDHCI_CMD_DATA_PRESENT_BIT); |
| 661 | flags |= (cmd->cmd_type << SDHCI_CMD_CMD_TYPE_BIT); |
| 662 | |
| 663 | /* Set the timeout value */ |
| 664 | REG_WRITE8(host, SDHCI_CMD_TIMEOUT, SDHCI_TIMEOUT_REG); |
| 665 | |
| 666 | /* Check if data needs to be processed */ |
| 667 | if (cmd->data_present) |
| 668 | sg_list = sdhci_adma_transfer(host, cmd); |
| 669 | |
| 670 | /* Write the argument 1 */ |
| 671 | REG_WRITE32(host, cmd->argument, SDHCI_ARGUMENT_REG); |
| 672 | |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 673 | /* Set the Transfer mode */ |
| 674 | if (cmd->data_present) |
| 675 | { |
| 676 | /* Enable DMA */ |
| 677 | trans_mode |= SDHCI_DMA_EN; |
| 678 | |
| 679 | if (cmd->trans_mode == SDHCI_MMC_READ) |
| 680 | trans_mode |= SDHCI_READ_MODE; |
| 681 | |
Channagoud Kadabi | 8990251 | 2013-05-14 13:22:06 -0700 | [diff] [blame] | 682 | /* Enable auto cmd23 or cmd12 for multi block transfer |
| 683 | * based on what command card supports |
| 684 | */ |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 685 | if (cmd->data.num_blocks > 1) { |
Channagoud Kadabi | 8990251 | 2013-05-14 13:22:06 -0700 | [diff] [blame] | 686 | if (cmd->cmd23_support) { |
| 687 | trans_mode |= SDHCI_TRANS_MULTI | SDHCI_AUTO_CMD23_EN | SDHCI_BLK_CNT_EN; |
| 688 | REG_WRITE32(host, cmd->data.num_blocks, SDHCI_ARG2_REG); |
| 689 | } |
| 690 | else |
| 691 | trans_mode |= SDHCI_TRANS_MULTI | SDHCI_AUTO_CMD12_EN | SDHCI_BLK_CNT_EN; |
Channagoud Kadabi | 2e233e7 | 2013-06-06 14:09:57 -0700 | [diff] [blame] | 692 | } |
| 693 | } |
| 694 | |
| 695 | /* Write to transfer mode register */ |
| 696 | REG_WRITE16(host, trans_mode, SDHCI_TRANS_MODE_REG); |
| 697 | |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 698 | /* Write the command register */ |
| 699 | REG_WRITE16(host, SDHCI_PREP_CMD(cmd->cmd_index, flags), SDHCI_CMD_REG); |
| 700 | |
| 701 | /* Command complete sequence */ |
| 702 | if (sdhci_cmd_complete(host, cmd)) |
| 703 | return 1; |
| 704 | |
| 705 | /* Invalidate the cache only for read operations */ |
| 706 | if (cmd->trans_mode == SDHCI_MMC_READ) |
| 707 | arch_invalidate_cache_range((addr_t)cmd->data.data_ptr, (cmd->data.num_blocks * SDHCI_MMC_BLK_SZ)); |
| 708 | |
| 709 | /* Free the scatter/gather list */ |
| 710 | if (sg_list) |
| 711 | free(sg_list); |
| 712 | |
| 713 | return 0; |
| 714 | } |
| 715 | |
| 716 | /* |
| 717 | * Function: sdhci reset |
| 718 | * Arg : Host structure |
| 719 | * Return : None |
| 720 | * Flow: : Reset the host controller |
| 721 | */ |
| 722 | static void sdhci_reset(struct sdhci_host *host) |
| 723 | { |
| 724 | uint32_t reg; |
| 725 | |
| 726 | REG_WRITE8(host, SDHCI_SOFT_RESET, SDHCI_RESET_REG); |
| 727 | |
| 728 | /* Wait for the reset to complete */ |
| 729 | do { |
| 730 | reg = REG_READ8(host, SDHCI_RESET_REG); |
| 731 | reg &= SDHCI_SOFT_RESET_MASK; |
| 732 | |
| 733 | if (!reg) |
| 734 | break; |
| 735 | } while(1); |
| 736 | } |
| 737 | |
| 738 | /* |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 739 | * Function: sdhci init |
| 740 | * Arg : Host structure |
| 741 | * Return : None |
| 742 | * Flow: : 1. Reset the controller |
| 743 | * 2. Read the capabilities register & populate the host |
| 744 | * controller capabilities for use by other functions |
| 745 | * 3. Enable the power control |
| 746 | * 4. Set initial bus width |
| 747 | * 5. Set Adma mode |
| 748 | * 6. Enable the error status |
| 749 | */ |
| 750 | void sdhci_init(struct sdhci_host *host) |
| 751 | { |
| 752 | uint32_t caps[2]; |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 753 | |
| 754 | /* |
| 755 | * Reset the controller |
| 756 | */ |
| 757 | sdhci_reset(host); |
| 758 | |
| 759 | /* Read the capabilities register & store the info */ |
| 760 | caps[0] = REG_READ32(host, SDHCI_CAPS_REG1); |
| 761 | caps[1] = REG_READ32(host, SDHCI_CAPS_REG2); |
| 762 | |
| 763 | host->caps.base_clk_rate = (caps[0] & SDHCI_CLK_RATE_MASK) >> SDHCI_CLK_RATE_BIT; |
| 764 | host->caps.base_clk_rate *= 1000000; |
| 765 | |
| 766 | /* Get the max block length for mmc */ |
| 767 | host->caps.max_blk_len = (caps[0] & SDHCI_BLK_LEN_MASK) >> SDHCI_BLK_LEN_BIT; |
| 768 | |
| 769 | /* 8 bit Bus width */ |
| 770 | if (caps[0] & SDHCI_8BIT_WIDTH_MASK) |
| 771 | host->caps.bus_width_8bit = 1; |
| 772 | |
| 773 | /* Adma support */ |
| 774 | if (caps[0] & SDHCI_BLK_ADMA_MASK) |
| 775 | host->caps.adma_support = 1; |
| 776 | |
| 777 | /* Supported voltage */ |
| 778 | if (caps[0] & SDHCI_3_3_VOL_MASK) |
| 779 | host->caps.voltage = SDHCI_VOL_3_3; |
| 780 | else if (caps[0] & SDHCI_3_0_VOL_MASK) |
| 781 | host->caps.voltage = SDHCI_VOL_3_0; |
| 782 | else if (caps[0] & SDHCI_1_8_VOL_MASK) |
| 783 | host->caps.voltage = SDHCI_VOL_1_8; |
| 784 | |
| 785 | /* DDR mode support */ |
| 786 | host->caps.ddr_support = (caps[1] & SDHCI_DDR_MODE_MASK) ? 1 : 0; |
| 787 | |
| 788 | /* SDR50 mode support */ |
| 789 | host->caps.sdr50_support = (caps[1] & SDHCI_SDR50_MODE_MASK) ? 1 : 0; |
| 790 | |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 791 | /* Set bus power on */ |
| 792 | sdhci_set_bus_power_on(host); |
| 793 | |
| 794 | /* Wait for power interrupt to be handled */ |
Channagoud Kadabi | 8990251 | 2013-05-14 13:22:06 -0700 | [diff] [blame] | 795 | event_wait(host->sdhc_event); |
Channagoud Kadabi | 74ed835 | 2013-03-11 13:12:05 -0700 | [diff] [blame] | 796 | |
| 797 | /* Set bus width */ |
| 798 | sdhci_set_bus_width(host, SDHCI_BUS_WITDH_1BIT); |
| 799 | |
| 800 | /* Set Adma mode */ |
| 801 | sdhci_set_adma_mode(host); |
| 802 | |
| 803 | /* |
| 804 | * Enable error status |
| 805 | */ |
| 806 | sdhci_error_status_enable(host); |
| 807 | } |