Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame^] | 1 | /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include <hdmi.h> |
| 31 | #include <platform/timer.h> |
| 32 | #include <platform/gpio.h> |
| 33 | #include <platform/clock.h> |
| 34 | #include <platform/iomap.h> |
| 35 | #include <platform/scm-io.h> |
| 36 | |
| 37 | extern void hdmi_app_clk_init(int); |
| 38 | extern void hdmi_msm_turn_on(); |
| 39 | |
| 40 | void hdmi_msm_init_phy() |
| 41 | { |
| 42 | dprintf(SPEW,"PHY INIT\n"); |
| 43 | uint32_t offset = 0; |
| 44 | uint32_t len = 0; |
| 45 | |
| 46 | writel(0x0C,HDMI_PHY_REG_0); |
| 47 | writel(0x54,HDMI_PHY_REG_1); |
| 48 | writel(0x7F,HDMI_PHY_REG_2); |
| 49 | writel(0x3F,HDMI_PHY_REG_2); |
| 50 | writel(0x1F,HDMI_PHY_REG_2); |
| 51 | |
| 52 | writel(0x01,HDMI_PHY_REG_3); |
| 53 | writel(0x00,HDMI_PHY_REG_9); |
| 54 | writel(0x03,HDMI_PHY_REG_12); |
| 55 | writel(0x01,HDMI_PHY_REG_2); |
| 56 | writel(0x81,HDMI_PHY_REG_2); |
| 57 | |
| 58 | offset = (HDMI_PHY_REG_4 - MSM_HDMI_BASE); |
| 59 | len = (HDMI_PHY_REG_11 - MSM_HDMI_BASE); |
| 60 | while (offset <= len) { |
| 61 | writel(0x0, MSM_HDMI_BASE + offset); |
| 62 | offset += 4; |
| 63 | } |
| 64 | writel(0x13,HDMI_PHY_REG_12); |
| 65 | } |
| 66 | |
| 67 | void hdmi_frame_ctrl_reg() |
| 68 | { |
| 69 | uint32_t hdmi_frame_ctrl; |
| 70 | |
| 71 | hdmi_frame_ctrl = ((0 << 31) & 0x80000000); |
| 72 | hdmi_frame_ctrl |= ((0 << 29) & 0x20000000); |
| 73 | hdmi_frame_ctrl |= ((0 << 28) & 0x10000000); |
| 74 | hdmi_frame_ctrl |= (1 << 12); |
| 75 | writel(hdmi_frame_ctrl,HDMI_FRAME_CTRL); |
| 76 | } |
| 77 | |
| 78 | static void hdmi_gpio_config() |
| 79 | { |
| 80 | uint32_t func; |
| 81 | uint32_t pull; |
| 82 | uint32_t drv; |
| 83 | uint32_t enable = 0; |
| 84 | uint32_t dir; |
| 85 | |
| 86 | func = 1; |
| 87 | pull = GPIO_NO_PULL; |
| 88 | drv = GPIO_16MA; |
| 89 | dir = 1; |
| 90 | gpio_tlmm_config(170, func, dir, pull, drv, enable); |
| 91 | |
| 92 | gpio_tlmm_config(171, func, dir, pull, drv, enable); |
| 93 | |
| 94 | func = 1; |
| 95 | pull = GPIO_PULL_DOWN; |
| 96 | drv = GPIO_16MA; |
| 97 | gpio_tlmm_config(172, func, dir, pull, drv, enable); |
| 98 | } |
| 99 | |
| 100 | /* |
| 101 | * This is the start function which initializes clocks , gpios for hdmi |
| 102 | * & powers on the HDMI core |
| 103 | */ |
| 104 | void hdmi_display_init() |
| 105 | { |
| 106 | // Enable HDMI clocks |
| 107 | hdmi_app_clk_init(1); |
| 108 | // Enable pm8058 |
| 109 | pm8058_ldo_set_voltage(); |
| 110 | pm8058_vreg_enable(); |
| 111 | // configure HDMI Gpio |
| 112 | hdmi_gpio_config(); |
| 113 | // Enable pm8091 |
| 114 | pm8901_mpp_enable(); |
| 115 | pm8901_vs_enable(); |
| 116 | // Power on HDMI |
| 117 | hdmi_msm_turn_on(); |
| 118 | } |
| 119 | |
| 120 | void dtv_on() |
| 121 | { |
| 122 | uint32_t val, pll_mode, ns_val, pll_config; |
| 123 | |
| 124 | // Configure PLL2 for tv src clk |
| 125 | pll_mode |= BIT(1); |
| 126 | secure_writel(pll_mode, MM_PLL2_MODE_REG); |
| 127 | udelay(10); |
| 128 | |
| 129 | pll_mode = secure_readl(MM_PLL2_MODE_REG); |
| 130 | pll_mode &= ~BIT(0); |
| 131 | secure_writel(pll_mode, MM_PLL2_MODE_REG); |
| 132 | pll_mode &= ~BIT(2); |
| 133 | secure_writel(pll_mode, MM_PLL2_MODE_REG); |
| 134 | |
| 135 | secure_writel(0x2C, MM_PLL2_L_VAL_REG); |
| 136 | secure_writel(0x0, MM_PLL2_M_VAL_REG); |
| 137 | secure_writel(0x0, MM_PLL2_N_VAL_REG); |
| 138 | udelay(10); |
| 139 | |
| 140 | val = 0xA6248F; |
| 141 | secure_writel(val, MM_PLL2_CONFIG_REG); |
| 142 | |
| 143 | // set M N D |
| 144 | ns_val = secure_readl(TV_NS_REG); |
| 145 | ns_val |= BIT(7); |
| 146 | secure_writel(ns_val, TV_NS_REG); |
| 147 | |
| 148 | secure_writel(0xff, TV_MD_REG); |
| 149 | |
| 150 | val = secure_readl(TV_CC_REG); |
| 151 | val &= ~(BM(7,6)); |
| 152 | val |= CC(6, 0); |
| 153 | secure_writel(val, TV_CC_REG); |
| 154 | |
| 155 | ns_val &= ~BIT(7); |
| 156 | secure_writel(ns_val, TV_NS_REG); |
| 157 | |
| 158 | // confiure hdmi_ref clk to run @ 148.5 MHz |
| 159 | val = secure_readl(MISC_CC2_REG); |
| 160 | val &= ~(BIT(28)|BM(21, 18)); |
| 161 | ns_val = NS_MM(23, 16, 0, 0, 15, 14, 2, 2, 0, 3); |
| 162 | val |= (BIT(28)| BVAL(21, 18, (ns_val >> 14) & 0x3)); |
| 163 | secure_writel(val, MISC_CC2_REG); |
| 164 | |
| 165 | pll_mode |= BIT(2); |
| 166 | secure_writel(pll_mode, MM_PLL2_MODE_REG); |
| 167 | |
| 168 | pll_mode |= BIT(0); |
| 169 | secure_writel(pll_mode, MM_PLL2_MODE_REG); |
| 170 | udelay(50); |
| 171 | |
| 172 | // Enable TV src clk |
| 173 | val = secure_readl(TV_NS_REG); |
| 174 | val &= ~(BM(23, 16) | BM(15, 14) | BM(2, 0)); |
| 175 | ns_val = NS_MM(23, 16, 0, 0, 15, 14, 2, 2, 0, 3); |
| 176 | val |= (ns_val & (BM(23, 16) | BM(15, 14) | BM(2, 0))); |
| 177 | secure_writel(val, TV_NS_REG); |
| 178 | |
| 179 | // Enable hdmi clk |
| 180 | val = secure_readl(TV_CC_REG); |
| 181 | val |= BIT(12); |
| 182 | secure_writel(val, TV_CC_REG); |
| 183 | |
| 184 | // Root en of tv src clk |
| 185 | val = secure_readl(TV_CC_REG); |
| 186 | val |= BIT(2); |
| 187 | secure_writel(val, TV_CC_REG); |
| 188 | |
| 189 | // De-Assert hdmi clk |
| 190 | val = secure_readl(SW_RESET_CORE_REG); |
| 191 | val |= BIT(1); |
| 192 | secure_writel(val, SW_RESET_CORE_REG); |
| 193 | udelay(10); |
| 194 | val = secure_readl(SW_RESET_CORE_REG); |
| 195 | val &= ~(BIT(1)); |
| 196 | secure_writel(val, SW_RESET_CORE_REG); |
| 197 | udelay(10); |
| 198 | |
| 199 | // enable mdp dtv clk |
| 200 | val = secure_readl(TV_CC_REG); |
| 201 | val |= BIT(0); |
| 202 | secure_writel(val, TV_CC_REG); |
| 203 | udelay(10); |
| 204 | } |