Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame^] | 1 | /* Copyright (c) 2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <stdint.h> |
| 30 | #include <debug.h> |
| 31 | #include <reg.h> |
| 32 | #include <mmc.h> |
| 33 | #include <clock.h> |
| 34 | #include <platform/timer.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | #include <pm8x41.h> |
| 38 | |
| 39 | void clock_init_mmc(uint32_t interface) |
| 40 | { |
| 41 | char clk_name[64]; |
| 42 | int ret; |
| 43 | |
| 44 | snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface); |
| 45 | |
| 46 | /* enable interface clock */ |
| 47 | ret = clk_get_set_enable(clk_name, 0, true); |
| 48 | if(ret) |
| 49 | { |
| 50 | dprintf(CRITICAL, "failed to set sdc%u_iface_clk ret = %d\n", interface, ret); |
| 51 | ASSERT(0); |
| 52 | } |
| 53 | } |
| 54 | |
| 55 | /* Configure MMC clock */ |
| 56 | void clock_config_mmc(uint32_t interface, uint32_t freq) |
| 57 | { |
| 58 | int ret = 0; |
| 59 | char clk_name[64]; |
| 60 | |
| 61 | snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface); |
| 62 | |
| 63 | if(freq == MMC_CLK_400KHZ) |
| 64 | { |
| 65 | ret = clk_get_set_enable(clk_name, 400000, true); |
| 66 | } |
| 67 | else if(freq == MMC_CLK_50MHZ) |
| 68 | { |
| 69 | ret = clk_get_set_enable(clk_name, 50000000, true); |
| 70 | } |
| 71 | else if(freq == MMC_CLK_96MHZ) |
| 72 | { |
| 73 | ret = clk_get_set_enable(clk_name, 100000000, true); |
| 74 | } |
| 75 | else if(freq == MMC_CLK_192MHZ) |
| 76 | { |
| 77 | ret = clk_get_set_enable(clk_name, 192000000, true); |
| 78 | } |
| 79 | else |
| 80 | { |
| 81 | dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq); |
| 82 | ASSERT(0); |
| 83 | } |
| 84 | |
| 85 | if(ret) |
| 86 | { |
| 87 | dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret); |
| 88 | ASSERT(0); |
| 89 | } |
| 90 | } |
| 91 | |
| 92 | /* Configure UART clock based on the UART block id*/ |
| 93 | void clock_config_uart_dm(uint8_t id) |
| 94 | { |
| 95 | int ret; |
| 96 | char iclk[64]; |
| 97 | char cclk[64]; |
| 98 | |
| 99 | snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id); |
| 100 | snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id); |
| 101 | |
| 102 | ret = clk_get_set_enable(iclk, 0, true); |
| 103 | if(ret) |
| 104 | { |
| 105 | dprintf(CRITICAL, "failed to set uart%u_iface_clk ret = %d\n", id, ret); |
| 106 | ASSERT(0); |
| 107 | } |
| 108 | |
| 109 | ret = clk_get_set_enable(cclk, 7372800, true); |
| 110 | if(ret) |
| 111 | { |
| 112 | dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret); |
| 113 | ASSERT(0); |
| 114 | } |
| 115 | } |
| 116 | |
| 117 | /* Function to asynchronously reset CE (Crypto Engine). |
| 118 | * Function assumes that all the CE clocks are off. |
| 119 | */ |
| 120 | static void ce_async_reset(uint8_t instance) |
| 121 | { |
| 122 | } |
| 123 | |
| 124 | void clock_ce_enable(uint8_t instance) |
| 125 | { |
| 126 | } |
| 127 | |
| 128 | void clock_ce_disable(uint8_t instance) |
| 129 | { |
| 130 | } |
| 131 | |
| 132 | void clock_config_ce(uint8_t instance) |
| 133 | { |
| 134 | /* Need to enable the clock before disabling since the clk_disable() |
| 135 | * has a check to default to nop when the clk_enable() is not called |
| 136 | * on that particular clock. |
| 137 | */ |
| 138 | clock_ce_enable(instance); |
| 139 | |
| 140 | clock_ce_disable(instance); |
| 141 | |
| 142 | ce_async_reset(instance); |
| 143 | |
| 144 | clock_ce_enable(instance); |
| 145 | |
| 146 | } |
| 147 | |
| 148 | void clock_usb30_gdsc_enable(void) |
| 149 | { |
| 150 | uint32_t reg = readl(GCC_USB30_GDSCR); |
| 151 | |
| 152 | reg &= ~(0x1); |
| 153 | |
| 154 | writel(reg, GCC_USB30_GDSCR); |
| 155 | } |
| 156 | |
| 157 | /* enables usb30 clocks */ |
| 158 | void clock_usb30_init(void) |
| 159 | { |
| 160 | int ret; |
| 161 | |
| 162 | ret = clk_get_set_enable("usb30_iface_clk", 0, true); |
| 163 | if(ret) |
| 164 | { |
| 165 | dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret); |
| 166 | ASSERT(0); |
| 167 | } |
| 168 | |
| 169 | clock_usb30_gdsc_enable(); |
| 170 | |
| 171 | ret = clk_get_set_enable("usb30_master_clk", 125000000, true); |
| 172 | if(ret) |
| 173 | { |
| 174 | dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret); |
| 175 | ASSERT(0); |
| 176 | } |
| 177 | |
| 178 | ret = clk_get_set_enable("usb30_phy_aux_clk", 1200000, true); |
| 179 | if(ret) |
| 180 | { |
| 181 | dprintf(CRITICAL, "failed to set usb30_phy_aux_clk. ret = %d\n", ret); |
| 182 | ASSERT(0); |
| 183 | } |
| 184 | |
| 185 | ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, true); |
| 186 | if(ret) |
| 187 | { |
| 188 | dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret); |
| 189 | ASSERT(0); |
| 190 | } |
| 191 | |
| 192 | ret = clk_get_set_enable("usb30_sleep_clk", 0, true); |
| 193 | if(ret) |
| 194 | { |
| 195 | dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret); |
| 196 | ASSERT(0); |
| 197 | } |
| 198 | |
| 199 | ret = clk_get_set_enable("usb_phy_cfg_ahb2phy_clk", 0, true); |
| 200 | if(ret) |
| 201 | { |
| 202 | dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret); |
| 203 | ASSERT(0); |
| 204 | } |
| 205 | |
| 206 | pm8x41_lnbb_clock_ctrl(1); |
| 207 | } |
| 208 | |
| 209 | void clock_bumpup_pipe3_clk() |
| 210 | { |
| 211 | int ret = 0; |
| 212 | |
| 213 | ret = clk_get_set_enable("usb30_pipe_clk", 0, true); |
| 214 | if(ret) |
| 215 | { |
| 216 | dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret); |
| 217 | ASSERT(0); |
| 218 | } |
| 219 | |
| 220 | return; |
| 221 | } |
| 222 | |
| 223 | void clock_reset_usb_phy() |
| 224 | { |
| 225 | int ret; |
| 226 | |
| 227 | struct clk *phy_reset_clk = NULL; |
| 228 | struct clk *pipe_reset_clk = NULL; |
| 229 | |
| 230 | /* Look if phy com clock is present */ |
| 231 | phy_reset_clk = clk_get("usb30_phy_reset"); |
| 232 | ASSERT(phy_reset_clk); |
| 233 | |
| 234 | pipe_reset_clk = clk_get("usb30_pipe_clk"); |
| 235 | ASSERT(pipe_reset_clk); |
| 236 | |
| 237 | /* ASSERT */ |
| 238 | ret = clk_reset(phy_reset_clk, CLK_RESET_ASSERT); |
| 239 | |
| 240 | if (ret) |
| 241 | { |
| 242 | dprintf(CRITICAL, "Failed to assert usb30_phy_reset clk\n"); |
| 243 | return; |
| 244 | } |
| 245 | |
| 246 | ret = clk_reset(pipe_reset_clk, CLK_RESET_ASSERT); |
| 247 | if (ret) |
| 248 | { |
| 249 | dprintf(CRITICAL, "Failed to assert usb30_pipe_clk\n"); |
| 250 | goto deassert_phy_clk; |
| 251 | } |
| 252 | |
| 253 | udelay(100); |
| 254 | |
| 255 | /* DEASSERT */ |
| 256 | ret = clk_reset(pipe_reset_clk, CLK_RESET_DEASSERT); |
| 257 | if (ret) |
| 258 | { |
| 259 | dprintf(CRITICAL, "Failed to deassert usb_pipe_clk\n"); |
| 260 | return; |
| 261 | } |
| 262 | |
| 263 | deassert_phy_clk: |
| 264 | |
| 265 | ret = clk_reset(phy_reset_clk, CLK_RESET_DEASSERT); |
| 266 | if (ret) |
| 267 | { |
| 268 | dprintf(CRITICAL, "Failed to deassert usb30_phy_com_reset clk\n"); |
| 269 | return; |
| 270 | } |
| 271 | } |