Dhaval Patel | bb40871 | 2014-03-18 11:45:53 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <mipi_dsi.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 32 | #include <platform/iomap.h> |
| 33 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 34 | #if (DISPLAY_TYPE_MDSS == 0) |
| 35 | #define MIPI_DSI0_BASE MIPI_DSI_BASE |
| 36 | #define MIPI_DSI1_BASE MIPI_DSI_BASE |
| 37 | #endif |
| 38 | |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame^] | 39 | #define MMSS_DSI_CLKOUT_TIMING_CTRL 0x0c4 |
| 40 | #define MMSS_DSI_PHY_TIMING_CTRL_0 0x0140 |
| 41 | #define MMSS_DSI_PHY_CTRL_0 0x0170 |
| 42 | #define MMSS_DSI_PHY_CTRL_1 0x0174 |
| 43 | #define MMSS_DSI_PHY_CTRL_2 0x0178 |
| 44 | #define MMSS_DSI_PHY_STRENGTH_CTRL_0 0x0184 |
| 45 | #define MMSS_DSI_PHY_STRENGTH_CTRL_1 0x0188 |
| 46 | #define MMSS_DSI_PHY_BIST_CTRL_0 0x01b4 |
| 47 | #define MMSS_DSI_PHY_GLBL_TEST_CTRL 0x01d4 |
| 48 | #define MMSS_DSI_PHY_LDO_CTRL 0x01dc |
| 49 | |
| 50 | #define TOTAL_TIMING_CTRL_CONFIG 12 |
| 51 | #define TOTAL_BIST_CTRL_CONFIG 6 |
| 52 | /* 4 data lanes and 1 clock lanes */ |
| 53 | #define TOTAL_LANE_COUNT 5 |
| 54 | #define CONFIG_REG_FOR_EACH_LANE 9 |
| 55 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 56 | static void mipi_dsi_calibration(void) |
| 57 | { |
| 58 | uint32_t i = 0; |
| 59 | uint32_t term_cnt = 5000; |
| 60 | int32_t cal_busy = readl(MIPI_DSI_BASE + 0x550); |
| 61 | |
| 62 | /* DSI1_DSIPHY_REGULATOR_CAL_PWR_CFG */ |
| 63 | writel(0x01, MIPI_DSI_BASE + 0x0518); |
| 64 | |
| 65 | /* DSI1_DSIPHY_CAL_SW_CFG2 */ |
| 66 | writel(0x0, MIPI_DSI_BASE + 0x0534); |
| 67 | /* DSI1_DSIPHY_CAL_HW_CFG1 */ |
| 68 | writel(0x5a, MIPI_DSI_BASE + 0x053c); |
| 69 | /* DSI1_DSIPHY_CAL_HW_CFG3 */ |
| 70 | writel(0x10, MIPI_DSI_BASE + 0x0544); |
| 71 | /* DSI1_DSIPHY_CAL_HW_CFG4 */ |
| 72 | writel(0x01, MIPI_DSI_BASE + 0x0548); |
| 73 | /* DSI1_DSIPHY_CAL_HW_CFG0 */ |
| 74 | writel(0x01, MIPI_DSI_BASE + 0x0538); |
| 75 | |
| 76 | /* DSI1_DSIPHY_CAL_HW_TRIGGER */ |
| 77 | writel(0x01, MIPI_DSI_BASE + 0x0528); |
| 78 | |
| 79 | /* DSI1_DSIPHY_CAL_HW_TRIGGER */ |
| 80 | writel(0x00, MIPI_DSI_BASE + 0x0528); |
| 81 | |
| 82 | cal_busy = readl(MIPI_DSI_BASE + 0x550); |
| 83 | while (cal_busy & 0x10) { |
| 84 | i++; |
| 85 | if (i > term_cnt) { |
| 86 | dprintf(CRITICAL, "DSI1 PHY REGULATOR NOT READY," |
| 87 | "exceeded polling TIMEOUT!\n"); |
| 88 | break; |
| 89 | } |
| 90 | cal_busy = readl(MIPI_DSI_BASE + 0x550); |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo) |
| 95 | { |
| 96 | struct mipi_dsi_phy_ctrl *pd; |
| 97 | uint32_t i, off = 0; |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 98 | int mdp_rev; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 99 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 100 | mdp_rev = mdp_get_revision(); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 101 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 102 | if (MDP_REV_303 == mdp_rev || MDP_REV_41 == mdp_rev) { |
| 103 | writel(0x00000001, DSIPHY_SW_RESET); |
| 104 | writel(0x00000000, DSIPHY_SW_RESET); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 105 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 106 | pd = (pinfo->dsi_phy_config); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 107 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 108 | off = 0x02cc; /* regulator ctrl 0 */ |
| 109 | for (i = 0; i < 4; i++) { |
| 110 | writel(pd->regulator[i], MIPI_DSI_BASE + off); |
| 111 | off += 4; |
| 112 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 113 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 114 | off = 0x0260; /* phy timig ctrl 0 */ |
| 115 | for (i = 0; i < 11; i++) { |
| 116 | writel(pd->timing[i], MIPI_DSI_BASE + off); |
| 117 | off += 4; |
| 118 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 119 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 120 | /* T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing |
| 121 | length should > data lane HS timing length */ |
| 122 | writel(0xa1e, DSI_CLKOUT_TIMING_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 123 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 124 | off = 0x0290; /* ctrl 0 */ |
| 125 | for (i = 0; i < 4; i++) { |
| 126 | writel(pd->ctrl[i], MIPI_DSI_BASE + off); |
| 127 | off += 4; |
| 128 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 129 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 130 | off = 0x02a0; /* strength 0 */ |
| 131 | for (i = 0; i < 4; i++) { |
| 132 | writel(pd->strength[i], MIPI_DSI_BASE + off); |
| 133 | off += 4; |
| 134 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 135 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 136 | if (1 == pinfo->num_of_lanes) |
| 137 | pd->pll[10] |= 0x8; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 138 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 139 | off = 0x0204; /* pll ctrl 1, skip 0 */ |
| 140 | for (i = 1; i < 21; i++) { |
| 141 | writel(pd->pll[i], MIPI_DSI_BASE + off); |
| 142 | off += 4; |
| 143 | } |
| 144 | |
| 145 | /* pll ctrl 0 */ |
| 146 | writel(pd->pll[0], MIPI_DSI_BASE + 0x200); |
| 147 | writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200); |
| 148 | /* lane swp ctrol */ |
| 149 | if (pinfo->lane_swap) |
| 150 | writel(pinfo->lane_swap, MIPI_DSI_BASE + 0xac); |
| 151 | } else { |
| 152 | writel(0x0001, MIPI_DSI_BASE + 0x128); /* start phy sw reset */ |
| 153 | writel(0x0000, MIPI_DSI_BASE + 0x128); /* end phy w reset */ |
| 154 | writel(0x0003, MIPI_DSI_BASE + 0x500); /* regulator_ctrl_0 */ |
| 155 | writel(0x0001, MIPI_DSI_BASE + 0x504); /* regulator_ctrl_1 */ |
| 156 | writel(0x0001, MIPI_DSI_BASE + 0x508); /* regulator_ctrl_2 */ |
| 157 | writel(0x0000, MIPI_DSI_BASE + 0x50c); /* regulator_ctrl_3 */ |
| 158 | writel(0x0100, MIPI_DSI_BASE + 0x510); /* regulator_ctrl_4 */ |
| 159 | |
| 160 | pd = (pinfo->dsi_phy_config); |
| 161 | |
| 162 | off = 0x0480; /* strength 0 - 2 */ |
| 163 | for (i = 0; i < 3; i++) { |
| 164 | writel(pd->strength[i], MIPI_DSI_BASE + off); |
| 165 | off += 4; |
| 166 | } |
| 167 | |
| 168 | off = 0x0470; /* ctrl 0 - 3 */ |
| 169 | for (i = 0; i < 4; i++) { |
| 170 | writel(pd->ctrl[i], MIPI_DSI_BASE + off); |
| 171 | off += 4; |
| 172 | } |
| 173 | |
| 174 | off = 0x0500; /* regulator ctrl 0 - 4 */ |
| 175 | for (i = 0; i < 5; i++) { |
| 176 | writel(pd->regulator[i], MIPI_DSI_BASE + off); |
| 177 | off += 4; |
| 178 | } |
| 179 | mipi_dsi_calibration(); |
| 180 | |
| 181 | off = 0x0204; /* pll ctrl 1 - 19, skip 0 */ |
| 182 | for (i = 1; i < 20; i++) { |
| 183 | writel(pd->pll[i], MIPI_DSI_BASE + off); |
| 184 | off += 4; |
| 185 | } |
| 186 | |
| 187 | /* pll ctrl 0 */ |
| 188 | writel(pd->pll[0], MIPI_DSI_BASE + 0x200); |
| 189 | writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200); |
| 190 | |
| 191 | /* Check that PHY is ready */ |
| 192 | while (!(readl(DSIPHY_PLL_RDY) & 0x01)) |
| 193 | udelay(1); |
| 194 | |
| 195 | writel(0x202D, DSI_CLKOUT_TIMING_CTRL); |
| 196 | |
| 197 | off = 0x0440; /* phy timing ctrl 0 - 11 */ |
| 198 | for (i = 0; i < 12; i++) { |
| 199 | writel(pd->timing[i], MIPI_DSI_BASE + off); |
| 200 | off += 4; |
| 201 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 202 | } |
| 203 | return 0; |
| 204 | } |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 205 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 206 | void mdss_dsi_phy_sw_reset(uint32_t ctl_base) |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 207 | { |
| 208 | /* start phy sw reset */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 209 | writel(0x0001, ctl_base + 0x012c); |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 210 | udelay(1000); |
| 211 | |
| 212 | /* end phy sw reset */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 213 | writel(0x0000, ctl_base + 0x012c); |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 214 | udelay(100); |
| 215 | } |
| 216 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 217 | int mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd) |
| 218 | { |
| 219 | /* DSI0 and DSI1 have a common regulator */ |
| 220 | |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 221 | uint32_t off = 0x0280; /* phy regulator ctrl settings */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 222 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 223 | /* Regulator ctrl 0 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 224 | writel(0x00, DSI0_PHY_BASE + off + (4 * 0)); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 225 | /* Regulator ctrl - CAL_PWD_CFG */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 226 | writel(pd->regulator[6], DSI0_PHY_BASE + off + (4 * 6)); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 227 | /* Regulator ctrl - TEST */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 228 | writel(pd->regulator[5], DSI0_PHY_BASE + off + (4 * 5)); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 229 | /* Regulator ctrl 3 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 230 | writel(pd->regulator[3], DSI0_PHY_BASE + off + (4 * 3)); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 231 | /* Regulator ctrl 2 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 232 | writel(pd->regulator[2], DSI0_PHY_BASE + off + (4 * 2)); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 233 | /* Regulator ctrl 1 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 234 | writel(pd->regulator[1], DSI0_PHY_BASE + off + (4 * 1)); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 235 | /* Regulator ctrl 0 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 236 | writel(pd->regulator[0], DSI0_PHY_BASE + off + (4 * 0)); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 237 | /* Regulator ctrl 4 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 238 | writel(pd->regulator[4], DSI0_PHY_BASE + off + (4 * 4)); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 239 | dmb(); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 240 | } |
| 241 | |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 242 | int mdss_dsi_v2_phy_init(struct mipi_dsi_panel_config *pinfo, uint32_t ctl_base) |
| 243 | { |
| 244 | struct mdss_dsi_phy_ctrl *pd; |
| 245 | uint32_t i, ln, off = 0, offset; |
| 246 | |
| 247 | pd = pinfo->mdss_dsi_phy_config; |
| 248 | /* DSI PHY configuration */ |
| 249 | off = 0x480; |
| 250 | writel(pd->strength[0], ctl_base + off + (4 * 0)); |
| 251 | writel(pd->strength[1], ctl_base + off + (4 * 2)); |
| 252 | |
| 253 | off = 0x470; |
| 254 | writel(0x10, ctl_base + off + (4 * 3)); |
| 255 | writel(0x5F, ctl_base + off + (4 * 0)); |
| 256 | |
| 257 | off = 0x500; |
Xiaoming Zhou | 7c9e1ee | 2013-07-18 10:51:41 -0400 | [diff] [blame] | 258 | /* use LDO mode */ |
| 259 | writel(0x25, ctl_base + 0x4B0); |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 260 | for (i = 0; i < 5; i++) |
| 261 | writel(pd->regulator[i], ctl_base + off + (4 * i)); |
| 262 | |
| 263 | mipi_dsi_calibration(); |
| 264 | |
| 265 | /* 4 lanes + clk lane configuration */ |
| 266 | /* lane config n * (0 - 4) & DataPath setup */ |
| 267 | for (ln = 0; ln < 5; ln++) { |
| 268 | off = 0x0300 + (ln * 0x40); |
| 269 | for (i = 0; i < 9; i++) { |
| 270 | offset = i + (ln * 9); |
| 271 | writel(pd->laneCfg[offset], ctl_base + off); |
| 272 | dmb(); |
| 273 | off += 4; |
| 274 | } |
| 275 | } |
| 276 | |
| 277 | off = 0x440; |
| 278 | for (i = 0; i < 12; i++) |
| 279 | writel(pd->timing[i], ctl_base + off + (4 * i)); |
| 280 | |
| 281 | if (1 == pinfo->num_of_lanes) |
| 282 | writel(0x8, ctl_base + 0x200 + (4 * 11)); |
| 283 | |
| 284 | |
| 285 | if (pinfo->lane_swap) |
| 286 | writel(pinfo->lane_swap, ctl_base + 0x0ac); |
| 287 | |
| 288 | /* T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing |
| 289 | length should > data lane HS timing length */ |
| 290 | writel(0x41b, ctl_base + 0x0c0); |
| 291 | return 0; |
| 292 | } |
| 293 | |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame^] | 294 | static int mdss_dsi_phy_28nm_init(struct mipi_dsi_panel_config *pinfo, |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 295 | uint32_t ctl_base, uint32_t phy_base) |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 296 | { |
| 297 | struct mdss_dsi_phy_ctrl *pd; |
| 298 | uint32_t i, off = 0, ln, offset; |
| 299 | |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 300 | if (mdp_get_revision() == MDP_REV_304) |
| 301 | return mdss_dsi_v2_phy_init(pinfo, ctl_base); |
| 302 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 303 | pd = (pinfo->mdss_dsi_phy_config); |
| 304 | |
| 305 | /* Strength ctrl 0 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 306 | writel(pd->strength[0], phy_base + 0x0184); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 307 | |
Mao Flynn | 5f137ed | 2014-04-18 14:59:47 +0800 | [diff] [blame] | 308 | if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE) |
| 309 | pd->regulator[0] = 0x2; /* LDO mode */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 310 | mdss_dsi_phy_regulator_init(pd); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 311 | |
Mao Flynn | 5f137ed | 2014-04-18 14:59:47 +0800 | [diff] [blame] | 312 | /* DSIPHY_REGULATOR_CTRL_0 */ |
| 313 | if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE) |
| 314 | writel(0x25, phy_base + 0x01dc); /* LDO mode */ |
| 315 | else |
| 316 | writel(0x00, phy_base + 0x01dc); /* DCDC mode */ |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 317 | |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 318 | off = 0x0140; /* phy timing ctrl 0 - 11 */ |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 319 | for (i = 0; i < 12; i++) { |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 320 | writel(pd->timing[i], phy_base + off); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 321 | dmb(); |
| 322 | off += 4; |
| 323 | } |
| 324 | |
| 325 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 326 | writel(0x00, phy_base + 0x0174); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 327 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 328 | writel(0x5f, phy_base + 0x0170); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 329 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 330 | dmb(); |
| 331 | /* 4 lanes + clk lane configuration */ |
| 332 | /* lane config n * (0 - 4) & DataPath setup */ |
| 333 | for (ln = 0; ln < 5; ln++) { |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 334 | off = (ln * 0x40); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 335 | for (i = 0; i < 9; i++) { |
| 336 | offset = i + (ln * 9); |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 337 | writel(pd->laneCfg[offset], phy_base + off); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 338 | dmb(); |
| 339 | off += 4; |
| 340 | } |
| 341 | } |
| 342 | |
| 343 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 344 | writel(0x5f, phy_base + 0x0170); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 345 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 346 | /* DSI_PHY_DSIPHY_GLBL_TEST_CTRL */ |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 347 | if (phy_base == DSI0_PHY_BASE || |
| 348 | (readl(MIPI_DSI0_BASE) == DSI_HW_REV_103_1)) |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 349 | writel(0x01, phy_base + 0x01d4); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 350 | else |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 351 | writel(0x00, phy_base + 0x01d4); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 352 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 353 | dmb(); |
| 354 | |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 355 | off = 0x01b4; /* phy BIST ctrl 0 - 5 */ |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 356 | for (i = 0; i < 6; i++) { |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 357 | writel(pd->bistCtrl[i], phy_base + off); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 358 | off += 4; |
| 359 | } |
| 360 | dmb(); |
| 361 | |
| 362 | /* DSI_0_CLKOUT_TIMING_CTRL */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 363 | writel(0x41b, ctl_base + 0x0c4); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 364 | dmb(); |
| 365 | |
| 366 | } |
Xiaoming Zhou | 03fd48b | 2014-07-31 15:24:41 -0400 | [diff] [blame] | 367 | |
| 368 | void mdss_dsi_phy_contention_detection( |
| 369 | struct mipi_dsi_panel_config *pinfo, |
| 370 | uint32_t phy_base) |
| 371 | { |
| 372 | struct mdss_dsi_phy_ctrl *pd; |
| 373 | |
| 374 | if (mdp_get_revision() == MDP_REV_304) |
| 375 | return; |
| 376 | |
| 377 | pd = (pinfo->mdss_dsi_phy_config); |
| 378 | writel(pd->strength[1], phy_base + 0x0188); |
| 379 | dmb(); |
| 380 | } |
| 381 | |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame^] | 382 | static int mdss_dsi_phy_20nm_init(struct mipi_dsi_panel_config *pinfo, |
| 383 | uint32_t ctl_base, uint32_t phy_base) |
| 384 | { |
| 385 | struct mdss_dsi_phy_ctrl *pd = pinfo->mdss_dsi_phy_config; |
| 386 | uint32_t i, off = 0, ln, offset; |
| 387 | |
| 388 | /* Strength ctrl 0 */ |
| 389 | writel(pd->strength[0], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_0); |
| 390 | |
| 391 | if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE) |
| 392 | pd->regulator[0] = 0x2; /* LDO mode */ |
| 393 | mdss_dsi_phy_regulator_init(pd); |
| 394 | |
| 395 | if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE) |
| 396 | writel(0x25, phy_base + MMSS_DSI_PHY_LDO_CTRL); /* LDO mode */ |
| 397 | else |
| 398 | writel(0x00, phy_base + MMSS_DSI_PHY_LDO_CTRL); /* DCDC mode */ |
| 399 | |
| 400 | off = MMSS_DSI_PHY_TIMING_CTRL_0; |
| 401 | for (i = 0; i < TOTAL_TIMING_CTRL_CONFIG; i++, off += 4) { |
| 402 | writel(pd->timing[i], phy_base + off); |
| 403 | dmb(); |
| 404 | } |
| 405 | |
| 406 | /* Currently the Phy settings for the DSI 0 is done in clk prepare*/ |
| 407 | if (phy_base == DSI1_PHY_BASE) { |
| 408 | writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_1); |
| 409 | writel(0x05, phy_base + MMSS_DSI_PHY_CTRL_0); |
| 410 | dmb(); |
| 411 | |
| 412 | writel(0x7f, phy_base + MMSS_DSI_PHY_CTRL_0); |
| 413 | dmb(); |
| 414 | |
| 415 | /* BITCLK_HS_SEL should be set to 0 for left */ |
| 416 | writel(0x00, phy_base + MMSS_DSI_PHY_GLBL_TEST_CTRL); |
| 417 | |
| 418 | writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_2); |
| 419 | writel(0x02, phy_base + MMSS_DSI_PHY_CTRL_2); |
| 420 | writel(0x03, phy_base + MMSS_DSI_PHY_CTRL_2); |
| 421 | dmb(); |
| 422 | } |
| 423 | |
| 424 | writel(pd->strength[1], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_1); |
| 425 | dmb(); |
| 426 | |
| 427 | for (ln = 0; ln < TOTAL_LANE_COUNT; ln++) { |
| 428 | off = (ln * 0x40); |
| 429 | for (i = 0; i < CONFIG_REG_FOR_EACH_LANE; i++, off += 4) { |
| 430 | offset = i + (ln * CONFIG_REG_FOR_EACH_LANE); |
| 431 | writel(pd->laneCfg[offset], phy_base + off); |
| 432 | dmb(); |
| 433 | } |
| 434 | } |
| 435 | |
| 436 | dmb(); |
| 437 | |
| 438 | off = MMSS_DSI_PHY_BIST_CTRL_0; |
| 439 | for (i = 0; i < TOTAL_BIST_CTRL_CONFIG; i++, off +=4) { |
| 440 | writel(pd->bistCtrl[i], phy_base + off); |
| 441 | } |
| 442 | dmb(); |
| 443 | |
| 444 | writel(0x41b, ctl_base + MMSS_DSI_CLKOUT_TIMING_CTRL); |
| 445 | dmb(); |
| 446 | } |
| 447 | |
| 448 | int mdss_dsi_phy_init (struct mipi_dsi_panel_config *pinfo, |
| 449 | uint32_t ctl_base, uint32_t phy_base) |
| 450 | { |
| 451 | int ret; |
| 452 | |
| 453 | if (pinfo->mdss_dsi_phy_config->is_pll_20nm) |
| 454 | ret = mdss_dsi_phy_20nm_init(pinfo, ctl_base, phy_base); |
| 455 | else |
| 456 | ret = mdss_dsi_phy_28nm_init(pinfo, ctl_base, phy_base); |
| 457 | |
| 458 | return ret; |
| 459 | } |