blob: 3ef40f66ba35fd1ea6fabb0b103e5649a321a8c4 [file] [log] [blame]
Ajay Dudani513fb742010-05-24 20:39:26 -07001/*
2 * Copyright (c) 2008, Google Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in
12 * the documentation and/or other materials provided with the
13 * distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
18 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
19 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
25 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifndef __PLATFORM_QSD8K_GPIO_HW_H
30#define __PLATFORM_QSD8K_GPIO_HW_H
31
32#define MSM_GPIO1_BASE 0xA9000000
33#define MSM_GPIO2_BASE 0xA9100000
34
35#define GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
36#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
37
38/* output value */
39#define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */
40#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 42-16 */
41#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-43 */
42#define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */
43#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 103-95 */
44#define GPIO_OUT_5 GPIO1_REG(0x10) /* gpio 121-104 */
45#define GPIO_OUT_6 GPIO1_REG(0x14) /* gpio 152-122 */
46#define GPIO_OUT_7 GPIO1_REG(0x18) /* gpio 164-153 */
47
48/* same pin map as above, output enable */
49#define GPIO_OE_0 GPIO1_REG(0x20)
50#define GPIO_OE_1 GPIO2_REG(0x08)
51#define GPIO_OE_2 GPIO1_REG(0x24)
52#define GPIO_OE_3 GPIO1_REG(0x28)
53#define GPIO_OE_4 GPIO1_REG(0x2C)
54#define GPIO_OE_5 GPIO1_REG(0x30)
55#define GPIO_OE_6 GPIO1_REG(0x34)
56#define GPIO_OE_7 GPIO1_REG(0x38)
57
58/* same pin map as above, input read */
59#define GPIO_IN_0 GPIO1_REG(0x50)
60#define GPIO_IN_1 GPIO2_REG(0x20)
61#define GPIO_IN_2 GPIO1_REG(0x54)
62#define GPIO_IN_3 GPIO1_REG(0x58)
63#define GPIO_IN_4 GPIO1_REG(0x5C)
64#define GPIO_IN_5 GPIO1_REG(0x60)
65#define GPIO_IN_6 GPIO1_REG(0x64)
66#define GPIO_IN_7 GPIO1_REG(0x68)
67
68/* same pin map as above, 1=edge 0=level interrup */
69#define GPIO_INT_EDGE_0 GPIO1_REG(0x70)
70#define GPIO_INT_EDGE_1 GPIO2_REG(0x50)
71#define GPIO_INT_EDGE_2 GPIO1_REG(0x74)
72#define GPIO_INT_EDGE_3 GPIO1_REG(0x78)
73#define GPIO_INT_EDGE_4 GPIO1_REG(0x7C)
74#define GPIO_INT_EDGE_5 GPIO1_REG(0x80)
75#define GPIO_INT_EDGE_6 GPIO1_REG(0x84)
76#define GPIO_INT_EDGE_7 GPIO1_REG(0x88)
77
78/* same pin map as above, 1=positive 0=negative */
79#define GPIO_INT_POS_0 GPIO1_REG(0x90)
80#define GPIO_INT_POS_1 GPIO2_REG(0x58)
81#define GPIO_INT_POS_2 GPIO1_REG(0x94)
82#define GPIO_INT_POS_3 GPIO1_REG(0x98)
83#define GPIO_INT_POS_4 GPIO1_REG(0x9C)
84#define GPIO_INT_POS_5 GPIO1_REG(0xA0)
85#define GPIO_INT_POS_6 GPIO1_REG(0xA4)
86#define GPIO_INT_POS_7 GPIO1_REG(0xA8)
87
88/* same pin map as above, interrupt enable */
89#define GPIO_INT_EN_0 GPIO1_REG(0xB0)
90#define GPIO_INT_EN_1 GPIO2_REG(0x60)
91#define GPIO_INT_EN_2 GPIO1_REG(0xB4)
92#define GPIO_INT_EN_3 GPIO1_REG(0xB8)
93#define GPIO_INT_EN_4 GPIO1_REG(0xBC)
94#define GPIO_INT_EN_5 GPIO1_REG(0xC0)
95#define GPIO_INT_EN_6 GPIO1_REG(0xC4)
96#define GPIO_INT_EN_7 GPIO1_REG(0xC8)
97
98/* same pin map as above, write 1 to clear interrupt */
99#define GPIO_INT_CLEAR_0 GPIO1_REG(0xD0)
100#define GPIO_INT_CLEAR_1 GPIO2_REG(0x68)
101#define GPIO_INT_CLEAR_2 GPIO1_REG(0xD4)
102#define GPIO_INT_CLEAR_3 GPIO1_REG(0xD8)
103#define GPIO_INT_CLEAR_4 GPIO1_REG(0xDC)
104#define GPIO_INT_CLEAR_5 GPIO1_REG(0xE0)
105#define GPIO_INT_CLEAR_6 GPIO1_REG(0xE4)
106#define GPIO_INT_CLEAR_7 GPIO1_REG(0xE8)
107
108/* same pin map as above, 1=interrupt pending */
109#define GPIO_INT_STATUS_0 GPIO1_REG(0xF0)
110#define GPIO_INT_STATUS_1 GPIO2_REG(0x70)
111#define GPIO_INT_STATUS_2 GPIO1_REG(0xF4)
112#define GPIO_INT_STATUS_3 GPIO1_REG(0xF8)
113#define GPIO_INT_STATUS_4 GPIO1_REG(0xFC)
114#define GPIO_INT_STATUS_5 GPIO1_REG(0x100)
115#define GPIO_INT_STATUS_6 GPIO1_REG(0x103)
116#define GPIO_INT_STATUS_7 GPIO1_REG(0x108)
117
118#endif