Abhimanyu Kapur | 002ddf9 | 2013-01-28 17:13:13 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
Amol Jadi | 42d7b5a | 2012-05-04 14:50:32 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
Deepa Dinamani | 28c0ffe | 2012-09-24 11:45:21 -0700 | [diff] [blame] | 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
Amol Jadi | 42d7b5a | 2012-05-04 14:50:32 -0700 | [diff] [blame] | 15 | * |
Deepa Dinamani | 28c0ffe | 2012-09-24 11:45:21 -0700 | [diff] [blame] | 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Amol Jadi | 42d7b5a | 2012-05-04 14:50:32 -0700 | [diff] [blame] | 27 | */ |
| 28 | |
| 29 | #ifndef _PLATFORM_MDM9625_IOMAP_H_ |
| 30 | #define _PLATFORM_MDM9625_IOMAP_H_ |
| 31 | |
Deepa Dinamani | 61e3a0c | 2012-10-19 14:33:37 -0700 | [diff] [blame] | 32 | #define MSM_IOMAP_BASE 0xF9000000 |
| 33 | #define MSM_IOMAP_END 0xFEFFFFFF |
Deepa Dinamani | 28c0ffe | 2012-09-24 11:45:21 -0700 | [diff] [blame] | 34 | |
Amol Jadi | 42d7b5a | 2012-05-04 14:50:32 -0700 | [diff] [blame] | 35 | #define MSM_SHARED_BASE 0x00000000 |
| 36 | |
Deepa Dinamani | 61e3a0c | 2012-10-19 14:33:37 -0700 | [diff] [blame] | 37 | /*SDRAM start address */ |
| 38 | #define SDRAM_START_ADDR 0x00000000 |
| 39 | |
Abhimanyu Kapur | 89ef5d0 | 2013-02-20 13:57:41 -0800 | [diff] [blame] | 40 | #define MSM_SHARED_IMEM_BASE 0xFC42A800 |
Amol Jadi | 62d7bd2 | 2012-10-08 18:15:58 -0700 | [diff] [blame] | 41 | #define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C) |
| 42 | |
Abhimanyu Kapur | f6d7667 | 2013-02-04 16:45:31 -0800 | [diff] [blame] | 43 | #define MSM_SHARED_IMEM_BASE_V2 0xFE807800 |
Abhimanyu Kapur | 002ddf9 | 2013-01-28 17:13:13 -0800 | [diff] [blame] | 44 | #define RESTART_REASON_ADDR_V2 (MSM_SHARED_IMEM_BASE_V2 + 0x65C) |
| 45 | |
Amol Jadi | 42d7b5a | 2012-05-04 14:50:32 -0700 | [diff] [blame] | 46 | #define ELAN_A5SS_BASE 0xF9000000 |
| 47 | |
| 48 | /* Peripheral subsystem */ |
| 49 | #define PERIPH_SS_BASE 0xF9800000 |
| 50 | #define PERIPH_SS_QPIC_BASE 0xF9AC4000 |
| 51 | |
| 52 | #define CLK_CTL_BASE 0xFC400000 /* GCC base */ |
Amol Jadi | fd507d5 | 2013-03-18 15:17:36 -0700 | [diff] [blame] | 53 | |
| 54 | /* MPM2_MPM */ |
| 55 | #define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000 |
| 56 | #define MPM2_MPM_PS_HOLD 0xFC4AB000 |
| 57 | |
Amol Jadi | 62d7bd2 | 2012-10-08 18:15:58 -0700 | [diff] [blame] | 58 | #define SPMI_BASE 0xFC4C0000 |
| 59 | #define SPMI_GENI_BASE (SPMI_BASE + 0xA000) |
| 60 | #define SPMI_PIC_BASE (SPMI_BASE + 0xB000) |
Amol Jadi | 42d7b5a | 2012-05-04 14:50:32 -0700 | [diff] [blame] | 61 | #define TLMM_BASE_ADDR 0xFD500000 |
| 62 | |
| 63 | /* QGIC2 */ |
| 64 | #define MSM_GIC_DIST_BASE (ELAN_A5SS_BASE + 0x0000) |
| 65 | #define MSM_GIC_CPU_BASE (ELAN_A5SS_BASE + 0x2000) |
| 66 | |
| 67 | /* QTMR */ |
| 68 | #define APCS_F0_QTMR_V1_BASE (ELAN_A5SS_BASE + 0x21000) |
| 69 | #define QTMR_BASE APCS_F0_QTMR_V1_BASE |
| 70 | |
| 71 | /* GPIO */ |
Deepa Dinamani | 28c0ffe | 2012-09-24 11:45:21 -0700 | [diff] [blame] | 72 | #define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x10000 + 0x1000 + (x)*0x10) |
| 73 | #define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x10000 + 0x1004 + (x)*0x10) |
Amol Jadi | 42d7b5a | 2012-05-04 14:50:32 -0700 | [diff] [blame] | 74 | |
| 75 | /* USB */ |
| 76 | #define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000) |
| 77 | |
Deepa Dinamani | dca5c66 | 2012-12-03 14:13:07 -0800 | [diff] [blame] | 78 | /* UART */ |
| 79 | #define MSM_UART2_BASE 0xF991F000 |
| 80 | |
Deepa Dinamani | e4573be | 2012-08-03 16:32:29 -0700 | [diff] [blame] | 81 | /* NAND */ |
| 82 | #define MSM_NAND_BASE 0xF9AF0000 |
| 83 | /* NAND BAM */ |
| 84 | #define MSM_NAND_BAM_BASE 0xF9AC4000 |
| 85 | |
Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 86 | /************ CLOCKS ***********/ |
| 87 | |
| 88 | /* GPLL */ |
| 89 | #define GPLL0_STATUS (CLK_CTL_BASE + 0x001C) |
| 90 | #define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480) |
| 91 | |
| 92 | /* UART */ |
Deepa Dinamani | dca5c66 | 2012-12-03 14:13:07 -0800 | [diff] [blame] | 93 | |
| 94 | #define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4) |
| 95 | |
Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 96 | #define BLSP1_UART1_APPS_CBCR (CLK_CTL_BASE + 0x684) |
| 97 | #define BLSP1_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0x68C) |
| 98 | #define BLSP1_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0x690) |
| 99 | #define BLSP1_UART1_APPS_M (CLK_CTL_BASE + 0x694) |
| 100 | #define BLSP1_UART1_APPS_N (CLK_CTL_BASE + 0x698) |
| 101 | #define BLSP1_UART1_APPS_D (CLK_CTL_BASE + 0x69C) |
| 102 | |
| 103 | #define BLSP1_UART3_APPS_CBCR (CLK_CTL_BASE + 0x784) |
| 104 | #define BLSP1_UART3_APPS_CMD_RCGR (CLK_CTL_BASE + 0x78C) |
| 105 | #define BLSP1_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0x790) |
| 106 | #define BLSP1_UART3_APPS_M (CLK_CTL_BASE + 0x794) |
| 107 | #define BLSP1_UART3_APPS_N (CLK_CTL_BASE + 0x798) |
| 108 | #define BLSP1_UART3_APPS_D (CLK_CTL_BASE + 0x79C) |
| 109 | |
Deepa Dinamani | dca5c66 | 2012-12-03 14:13:07 -0800 | [diff] [blame] | 110 | #define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x704) |
| 111 | #define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x70C) |
| 112 | #define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x710) |
| 113 | #define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x714) |
| 114 | #define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x718) |
| 115 | #define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x71C) |
| 116 | |
| 117 | #define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484) |
| 118 | |
Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 119 | /* USB */ |
| 120 | #define USB_HS_BCR (CLK_CTL_BASE + 0x480) |
| 121 | #define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484) |
| 122 | #define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x488) |
| 123 | #define GCC_USB_HS_INACTIVITY_TIMERS_CBCR (CLK_CTL_BASE + 0x48C) |
| 124 | #define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490) |
| 125 | #define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494) |
| 126 | |
Amol Jadi | 42d7b5a | 2012-05-04 14:50:32 -0700 | [diff] [blame] | 127 | #endif |