blob: c7699a024eb4b82a5d6b54379fc1edd3ca1b9915 [file] [log] [blame]
Asaf Penso7ba5fc52013-05-01 10:48:05 +03001/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29
30#include <stdint.h>
31#include <msm_panel.h>
32#include <mipi_dsi.h>
33#include <sys/types.h>
34#include <err.h>
35#include <reg.h>
36#include <mdp4.h>
37
38int mipi_sharp_video_qhd_config(void *pdata)
39{
40 int ret = NO_ERROR;
41
42 /* 2 Lanes -- Enables Data Lane0, 1 */
43 uint8_t lane_en = 0x3;
44 uint64_t low_pwr_stop_mode = 0;
45
46 /* Needed or else will have blank line at top of display */
47 uint8_t eof_bllp_pwr = 0x9;
48
49 uint8_t interleav = 0;
50 struct lcdc_panel_info *lcdc = NULL;
51 struct msm_panel_info *pinfo = (struct msm_panel_info *)pdata;
52
53 if (!pinfo)
54 return ERR_INVALID_ARGS;
55
56 lcdc = &(pinfo->lcdc);
57 if (!lcdc)
58 return ERR_INVALID_ARGS;
59
60 ret = mipi_dsi_video_mode_config((pinfo->xres + lcdc->xres_pad),
61 (pinfo->yres + lcdc->yres_pad),
62 (pinfo->xres),
63 (pinfo->yres),
64 (lcdc->h_front_porch),
65 (lcdc->h_back_porch + lcdc->h_pulse_width),
66 (lcdc->v_front_porch),
67 (lcdc->v_back_porch + lcdc->v_pulse_width),
68 (lcdc->h_pulse_width),
69 (lcdc->v_pulse_width),
70 pinfo->mipi.dst_format,
71 pinfo->mipi.traffic_mode,
72 lane_en,
73 low_pwr_stop_mode,
74 eof_bllp_pwr,
75 interleav);
76 return ret;
77}
78
79int mipi_sharp_video_qhd_on()
80{
81 return NO_ERROR;
82}
83
84int mipi_sharp_video_qhd_off()
85{
86 return NO_ERROR;
87}
88
89static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db = {
90 /* 540x960, RGB888, 2 Lane 60 fps video mode */
91 /* regulator */
92 {0x07, 0x09, 0x03, 0x00, 0x20, 0x00, 0x01},
93 /* timing */
94 {0x46, 0x1d, 0x20, 0x00, 0x39, 0x3a, 0x21, 0x21,
95 0x32, 0x03, 0x04, 0x00},
96 /* phy ctrl */
97 {0x5f, 0x00, 0x00, 0x10},
98 /* strength */
99 {0xff, 0x06},
100 /* bist control */
101 {0x00, 0x00, 0xb1, 0xff, 0x00, 0x00},
102 /* lanes config */
103 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x97,
104 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x97,
105 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x01, 0x97,
106 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x01, 0x97,
107 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xbb},
108};
109
110void mipi_sharp_video_qhd_init(struct msm_panel_info *pinfo)
111{
112 if (!pinfo)
113 return;
114
115 pinfo->xres = 540;
116 pinfo->yres = 960;
117 pinfo->type = MIPI_VIDEO_PANEL;
118 pinfo->wait_cycle = 0;
119 pinfo->bpp = 24;
120 pinfo->lcdc.h_back_porch = 80;
121 pinfo->lcdc.h_front_porch = 48;
122 pinfo->lcdc.h_pulse_width = 32;
123 pinfo->lcdc.v_back_porch = 15;
124 pinfo->lcdc.v_front_porch = 3;
125 pinfo->lcdc.v_pulse_width = 10;
126 pinfo->lcdc.border_clr = 0; /* blk */
127 pinfo->lcdc.underflow_clr = 0xff; /* blue */
128 pinfo->lcdc.hsync_skew = 0;
129 pinfo->clk_rate = 500000000;
130
131 pinfo->mipi.mode = DSI_VIDEO_MODE;
132 pinfo->mipi.pulse_mode_hsa_he = FALSE;
133 pinfo->mipi.hfp_power_stop = FALSE;
134 pinfo->mipi.hbp_power_stop = FALSE;
135 pinfo->mipi.hsa_power_stop = FALSE;
136 pinfo->mipi.eof_bllp_power_stop = FALSE;
137 pinfo->mipi.bllp_power_stop = FALSE;
138 pinfo->mipi.traffic_mode = DSI_NON_BURST_SYNCH_PULSE;
139 pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
140 pinfo->mipi.vc = 0;
141 pinfo->mipi.rgb_swap = DSI_RGB_SWAP_RGB;
142 pinfo->mipi.data_lane0 = TRUE;
143 pinfo->mipi.data_lane1 = TRUE;
144 pinfo->mipi.data_lane2 = FALSE;
145 pinfo->mipi.data_lane3 = FALSE;
146 pinfo->mipi.t_clk_post = 0x04;
147 pinfo->mipi.t_clk_pre = 0x1c;
148 pinfo->mipi.stream = 0; /* dma_p */
149 pinfo->mipi.mdp_trigger = 0;
150 pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
151 pinfo->mipi.frame_rate = 60;
152 pinfo->mipi.mdss_dsi_phy_db = &dsi_video_mode_phy_db;
153 pinfo->mipi.tx_eot_append = TRUE;
154 pinfo->mipi.num_of_lanes = 2;
155
156 pinfo->mipi.panel_cmds = sharp_qhd_video_mode_cmds;
157 pinfo->mipi.num_of_panel_cmds =
158 ARRAY_SIZE(sharp_qhd_video_mode_cmds);
159
160 pinfo->on = mipi_sharp_video_qhd_on;
161 pinfo->off = mipi_sharp_video_qhd_off;
162 pinfo->config = mipi_sharp_video_qhd_config;
163}