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gerrit-public.fairphone.software / kernel / lk / refs/heads/rel/p/fp2/20.12.0-beta / . / platform / msm_shared / include / qpic_nand.h
blob: 06763017967956bcf413a13d9ab00441d7e70e58 [file] [log] [blame]
Deepa Dinamanie4573be2012-08-03 16:32:29 -0700[diff] [blame]1/*
2 * Copyright (c) 2008, Google Inc.
3 * All rights reserved.
Deepa Dinamani16663a62013-02-07 16:25:59 -0800[diff] [blame]4 * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
Deepa Dinamanie4573be2012-08-03 16:32:29 -0700[diff] [blame]5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in
13 * the documentation and/or other materials provided with the
14 * distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
19 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
20 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
23 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#ifndef __QPIC_NAND_H
31#define __QPIC_NAND_H
32
33#include <debug.h>
34#include <dev/flash.h>
35#include <platform/iomap.h>
36
37#define NAND_REG(off) (nand_base + (off))
38
39#define NAND_FLASH_CMD NAND_REG(0x0000)
40#define NAND_ADDR0 NAND_REG(0x0004)
41#define NAND_ADDR1 NAND_REG(0x0008)
42#define NAND_FLASH_CHIP_SELECT NAND_REG(0x000C)
43#define NAND_EXEC_CMD NAND_REG(0x0010)
44#define NAND_FLASH_STATUS NAND_REG(0x0014)
45#define NAND_BUFFER_STATUS NAND_REG(0x0018)
46#define NAND_DEV0_CFG0 NAND_REG(0x0020)
47#define NAND_DEV0_CFG1 NAND_REG(0x0024)
48#define NAND_DEV0_ECC_CFG NAND_REG(0x0028)
49#define NAND_DEV1_CFG0 NAND_REG(0x0030)
50#define NAND_DEV1_CFG1 NAND_REG(0x0034)
51#define NAND_SFLASHC_CMD NAND_REG(0x0038)
52#define NAND_SFLASHC_EXEC_CMD NAND_REG(0x003C)
53#define NAND_READ_ID NAND_REG(0x0040)
54#define NAND_READ_STATUS NAND_REG(0x0044)
55#define NAND_CONFIG_DATA NAND_REG(0x0050)
56#define NAND_CONFIG NAND_REG(0x0054)
57#define NAND_CONFIG_MODE NAND_REG(0x0058)
58#define NAND_CONFIG_STATUS NAND_REG(0x0060)
59#define NAND_MACRO1_REG NAND_REG(0x0064)
60#define NAND_XFR_STEP1 NAND_REG(0x0070)
61#define NAND_XFR_STEP2 NAND_REG(0x0074)
62#define NAND_XFR_STEP3 NAND_REG(0x0078)
63#define NAND_XFR_STEP4 NAND_REG(0x007C)
64#define NAND_XFR_STEP5 NAND_REG(0x0080)
65#define NAND_XFR_STEP6 NAND_REG(0x0084)
66#define NAND_XFR_STEP7 NAND_REG(0x0088)
67#define NAND_GENP_REG0 NAND_REG(0x0090)
68#define NAND_GENP_REG1 NAND_REG(0x0094)
69#define NAND_GENP_REG2 NAND_REG(0x0098)
70#define NAND_GENP_REG3 NAND_REG(0x009C)
71#define NAND_SFLASHC_STATUS NAND_REG(0x001C)
72#define NAND_DEV_CMD0 NAND_REG(0x00A0)
73#define NAND_DEV_CMD1 NAND_REG(0x00A4)
74#define NAND_DEV_CMD2 NAND_REG(0x00A8)
75#define NAND_DEV_CMD_VLD NAND_REG(0x00AC)
76#define NAND_EBI2_MISR_SIG_REG NAND_REG(0x00B0)
77#define NAND_ADDR2 NAND_REG(0x00C0)
78#define NAND_ADDR3 NAND_REG(0x00C4)
79#define NAND_ADDR4 NAND_REG(0x00C8)
80#define NAND_ADDR5 NAND_REG(0x00CC)
81#define NAND_DEV_CMD3 NAND_REG(0x00D0)
82#define NAND_DEV_CMD4 NAND_REG(0x00D4)
83#define NAND_DEV_CMD5 NAND_REG(0x00D8)
84#define NAND_DEV_CMD6 NAND_REG(0x00DC)
85#define NAND_SFLASHC_BURST_CFG NAND_REG(0x00E0)
86#define NAND_ADDR6 NAND_REG(0x00E4)
Deepa Dinamani19530062012-10-03 14:43:05 -0700[diff] [blame]87#define NAND_ERASED_CW_DETECT_CFG NAND_REG(0x00E8)
88#define NAND_ERASED_CW_DETECT_STATUS NAND_REG(0x00EC)
Deepa Dinamanie4573be2012-08-03 16:32:29 -0700[diff] [blame]89#define NAND_EBI2_ECC_BUF_CFG NAND_REG(0x00F0)
Deepa Dinamanie4573be2012-08-03 16:32:29 -0700[diff] [blame]90#define NAND_HW_INFO NAND_REG(0x00FC)
Deepa Dinamani19530062012-10-03 14:43:05 -0700[diff] [blame]91#define NAND_FLASH_BUFFER NAND_REG(0x0100)
Deepa Dinamanie4573be2012-08-03 16:32:29 -0700[diff] [blame]92
93/* NANDc registers used during BAM transfer */
94#define NAND_READ_LOCATION_n(n) (NAND_REG(0xF20) + 4 * (n))
95#define NAND_RD_LOC_LAST_BIT(x) ((x) << 31)
96#define NAND_RD_LOC_SIZE(x) ((x) << 16)
97#define NAND_RD_LOC_OFFSET(x) ((x) << 0)
98
99/* Shift Values */
100#define NAND_DEV0_CFG1_WIDE_BUS_SHIFT 1
101#define NAND_DEV0_CFG0_DIS_STS_AFTER_WR_SHIFT 4
102#define NAND_DEV0_CFG0_CW_PER_PAGE_SHIFT 6
103#define NAND_DEV0_CFG0_UD_SIZE_BYTES_SHIFT 9
104#define NAND_DEV0_CFG0_ADDR_CYCLE_SHIFT 27
105#define NAND_DEV0_CFG0_SPARE_SZ_BYTES_SHIFT 23
106
107#define NAND_DEV0_CFG1_RECOVERY_CYCLES_SHIFT 2
108#define NAND_DEV0_CFG1_CS_ACTIVE_BSY_SHIFT 5
109#define NAND_DEV0_CFG1_BAD_BLK_BYTE_NUM_SHIFT 6
110#define NAND_DEV0_CFG1_BAD_BLK_IN_SPARE_SHIFT 16
111#define NAND_DEV0_CFG1_WR_RD_BSY_GAP_SHIFT 17
112#define NAND_DEV0_ECC_DISABLE_SHIFT 0
113#define NAND_DEV0_ECC_SW_RESET_SHIFT 1
114#define NAND_DEV0_ECC_MODE_SHIFT 4
115#define NAND_DEV0_ECC_DISABLE_SHIFT 0
116#define NAND_DEV0_ECC_PARITY_SZ_BYTES_SHIFT 8
117#define NAND_DEV0_ECC_NUM_DATA_BYTES 16
118#define NAND_DEV0_ECC_FORCE_CLK_OPEN_SHIFT 30
119
Deepa Dinamani19530062012-10-03 14:43:05 -0700[diff] [blame]120#define NAND_ERASED_CW_DETECT_STATUS_PAGE_ALL_ERASED 7
121#define NAND_ERASED_CW_DETECT_STATUS_CODEWORD_ALL_ERASED 6
122#define NAND_ERASED_CW_DETECT_STATUS_CODEWORD_ERASED 4
123
124#define NAND_ERASED_CW_DETECT_CFG_RESET_CTRL 1
125#define NAND_ERASED_CW_DETECT_CFG_ACTIVATE_CTRL 0
126#define NAND_ERASED_CW_DETECT_ERASED_CW_ECC_MASK (1 << 1)
127#define NAND_ERASED_CW_DETECT_ERASED_CW_ECC_NO_MASK (0 << 1)
128
Deepa Dinamanie4573be2012-08-03 16:32:29 -0700[diff] [blame]129/* device commands */
130#define NAND_CMD_SOFT_RESET 0x01
131#define NAND_CMD_PAGE_READ 0x32
132#define NAND_CMD_PAGE_READ_ECC 0x33
133#define NAND_CMD_PAGE_READ_ALL 0x34
134#define NAND_CMD_SEQ_PAGE_READ 0x15
135#define NAND_CMD_PRG_PAGE 0x36
136#define NAND_CMD_PRG_PAGE_ECC 0x37
137#define NAND_CMD_PRG_PAGE_ALL 0x39
138#define NAND_CMD_BLOCK_ERASE 0x3A
139#define NAND_CMD_FETCH_ID 0x0B
140#define NAND_CMD_STATUS 0x0C
141#define NAND_CMD_RESET 0x0D
142
143/* NAND Status errors */
144#define NAND_FLASH_MPU_ERR (1 << 8)
145#define NAND_FLASH_TIMEOUT_ERR (1 << 6)
146#define NAND_FLASH_OP_ERR (1 << 4)
147
148#define NAND_FLASH_ERR (NAND_FLASH_MPU_ERR | \
Deepa Dinamani19530062012-10-03 14:43:05 -0700[diff] [blame]149 NAND_FLASH_TIMEOUT_ERR | \
150 NAND_FLASH_OP_ERR)
Deepa Dinamanie4573be2012-08-03 16:32:29 -0700[diff] [blame]151
152#define PROG_ERASE_OP_RESULT (1 << 7)
153
154#define DATA_CONSUMER_PIPE_INDEX 0
155#define DATA_PRODUCER_PIPE_INDEX 1
156#define CMD_PIPE_INDEX 2
157
158/* Define BAM pipe lock groups for NANDc*/
159#define P_LOCK_GROUP_0 0
160
161/* Define BAM pipe lock super groups for NANDc
162 * Note: This is configured by TZ.
163 */
164#define P_LOCK_SUPERGROUP_0 0
165#define P_LOCK_SUPERGROUP_1 1
166
167#define ONFI_SIGNATURE 0x49464E4F
168
169#define ONFI_CRC_POLYNOMIAL 0x8005
170#define ONFI_CRC_INIT_VALUE 0x4F4E
171
172#define ONFI_READ_PARAM_PAGE_ADDR_CYCLES 1
173#define ONFI_READ_ID_ADDR_CYCLES 1
174
175#define ONFI_READ_ID_CMD 0x90
176#define ONFI_READ_PARAM_PAGE_CMD 0xEC
177#define ONFI_READ_ID_ADDR 0x20
178#define ONFI_READ_PARAM_PAGE_ADDR 0x00
179
180#define NAND_CFG0_RAW_ONFI_ID 0x88000800
181#define NAND_CFG0_RAW_ONFI_PARAM_PAGE 0x88040000
182#define NAND_CFG1_RAW_ONFI_ID 0x0005045D
183#define NAND_CFG1_RAW_ONFI_PARAM_PAGE 0x0005045D
184#define NAND_CFG0 0x290409c0
185#define NAND_CFG1 0x08045d5c
186#define NAND_ECC_BCH_CFG 0x42040d10
187#define NAND_Bad_Block 0x00000175
188#define NAND_ECC_BUF_CFG 0x00000203
189
190#define ONFI_READ_ID_BUFFER_SIZE 0x4
191#define ONFI_READ_PARAM_PAGE_BUFFER_SIZE 0x200
192#define ONFI_PARAM_PAGE_SIZE 0x100
193
194#define NAND_8BIT_DEVICE 0x01
195#define NAND_16BIT_DEVICE 0x02
196
197#define NAND_CW_SIZE_4_BIT_ECC 528
198#define NAND_CW_SIZE_8_BIT_ECC 532
199
200/* Indicates the data bytes in the user data portion of the code word. */
201#define USER_DATA_BYTES_PER_CW 512
202
203/* Indicates the number of bytes covered by BCH ECC logic when
204 * a codeword is written to a NAND flash device.
205 * This is also the number of bytes that are part of the image in CW.
206 * 516 bytes = (512 bytes of user data and 4 bytes of spare data)
207 */
208#define DATA_BYTES_IN_IMG_PER_CW 516
209
210#define NAND_CW_DIV_RIGHT_SHIFT 9
211
Deepa Dinamani16663a62013-02-07 16:25:59 -0800[diff] [blame]212/* Number of max cw's the driver allows to flash. */
213#define QPIC_NAND_MAX_CWS_IN_PAGE 10
214
Deepa Dinamanie4573be2012-08-03 16:32:29 -0700[diff] [blame]215/* Reset Values for Status registers */
216#define NAND_FLASH_STATUS_RESET 0x00000020
217#define NAND_READ_STATUS_RESET 0x000000C0
218
219/* result type */
220typedef enum {
221 NANDC_RESULT_SUCCESS = 0,
222 NANDC_RESULT_FAILURE = 1,
223 NANDC_RESULT_TIMEOUT = 2,
224 NANDC_RESULT_PARAM_INVALID = 3,
225 NANDC_RESULT_DEV_NOT_SUPPORTED = 4,
226 NANDC_RESULT_BAD_PAGE = 5,
227 NANDC_RESULT_BAD_BLOCK = 6,
228} nand_result_t;
229
230enum nand_bad_block_value
231{
232 NAND_BAD_BLK_VALUE_NOT_READ,
233 NAND_BAD_BLK_VALUE_IS_BAD,
234 NAND_BAD_BLK_VALUE_IS_GOOD,
235};
236
237enum nand_cfg_value
238{
239 NAND_CFG_RAW,
240 NAND_CFG,
241};
242
243struct onfi_param_page
244{
245 uint32_t signature;
246 uint16_t rev;
247 uint16_t feature_supported;
248 uint16_t opt_cmd_supported;
249 uint8_t reserved_1[22];
250 uint8_t mib[12];
251 uint8_t device_model[20];
252 uint8_t manufacturer_id;
253 uint16_t date_code;
254 uint8_t reserved_2[13];
255 uint32_t data_per_pg;
256 uint16_t spare_per_pg;
257 uint32_t data_per_partial_pg;
258 uint16_t spare_per_partial_pg;
259 uint32_t pgs_per_blk;
260 uint32_t blks_per_LUN;
261 uint8_t num_LUN;
262 uint8_t num_addr_cycles;
263 uint8_t num_bits_per_cell;
264 uint16_t bad_blks_max_per_LUN;
265 uint16_t blk_endurance;
266 uint8_t guaranteed_vld_blks_at_start;
267 uint16_t blk_endurance_for_garunteed_vld_blks;
268 uint8_t num_prg_per_pg;
269 uint8_t partial_prog_attr;
270 uint8_t num_bits_ecc_correctability;
271 uint8_t num_interleaved_addr_bits;
272 uint8_t interleaved_op_attr;
273 uint8_t reserved_3[13];
274 uint8_t io_pin_capcacitance;
275 uint16_t timing_mode_support;
276 uint16_t prog_cache_timing_mode_support;
277 uint16_t max_pg_prog_time_us;
278 uint16_t max_blk_erase_time_us;
279 uint16_t max_pr_rd_time_us;
280 uint16_t min_chg_col_setup_time_us;
281 uint8_t reserved_4[23];
282 uint16_t vendor_rev;
283 uint8_t vendor_specific[88];
284 uint16_t interity_crc;
285}__PACKED;
286
287struct cfg_params
288{
289 uint32_t addr0;
290 uint32_t addr1;
291 uint32_t cfg0;
292 uint32_t cfg1;
293 uint32_t cmd;
294 uint32_t ecc_cfg;
295 uint32_t addr_loc_0;
296 uint32_t exec;
297};
298
299struct onfi_probe_params
300{
301 uint32_t vld;
302 uint32_t dev_cmd1;
303 struct cfg_params cfg;
304};
305
306/* This stucture is used to create a static list of devices we support.
307 * This include a subset of values defined in the flash_info struct as
308 * other values can be derived.
309 */
310struct flash_id
311{
312 unsigned flash_id;
313 unsigned mask;
314 unsigned density;
315 unsigned widebus;
316 unsigned pagesize;
317 unsigned blksize;
318 unsigned oobsize;
Deepa Dinamanie4573be2012-08-03 16:32:29 -0700[diff] [blame]319 unsigned ecc_8_bits;
320};
321
322/* Structure to hold the pipe numbers */
323struct qpic_nand_bam_pipes
324{
325 unsigned read_pipe;
326 unsigned write_pipe;
327 unsigned cmd_pipe;
Deepa Dinamani536d3f82013-07-09 13:05:56 -0700[diff] [blame]328 uint8_t read_pipe_grp;
329 uint8_t write_pipe_grp;
330 uint8_t cmd_pipe_grp;
Deepa Dinamanie4573be2012-08-03 16:32:29 -0700[diff] [blame]331};
332
333/* Structure to define the initial nand config */
334struct qpic_nand_init_config
335{
336 uint32_t nand_base;
337 uint32_t bam_base;
Deepa Dinamanie9ded132012-11-27 15:03:38 -0800[diff] [blame]338 uint32_t ee;
339 uint32_t max_desc_len;
Deepa Dinamanie4573be2012-08-03 16:32:29 -0700[diff] [blame]340 struct qpic_nand_bam_pipes pipes;
341};
342
343void
344qpic_nand_init(struct qpic_nand_init_config *config);
Deepa Dinamani28c0ffe2012-09-24 11:45:21 -0700[diff] [blame]345unsigned
346flash_block_size(void);
Deepa Dinamani87feab82012-10-04 14:28:05 -0700[diff] [blame]347void
348qpic_nand_uninit();
Deepa Dinamanie4573be2012-08-03 16:32:29 -0700[diff] [blame]349
350#endif