| Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2008 Travis Geiselbrecht |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining |
| 5 | * a copy of this software and associated documentation files |
| 6 | * (the "Software"), to deal in the Software without restriction, |
| 7 | * including without limitation the rights to use, copy, modify, merge, |
| 8 | * publish, distribute, sublicense, and/or sell copies of the Software, |
| 9 | * and to permit persons to whom the Software is furnished to do so, |
| 10 | * subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be |
| 13 | * included in all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 18 | * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
| 19 | * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 20 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 21 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | #ifndef __PLATFORM_OMAP3_H |
| 24 | #define __PLATFORM_OMAP3_H |
| 25 | |
| 26 | #define SDRAM_BASE 0x80000000 |
| 27 | |
| 28 | #define L4_BASE 0x48000000 |
| 29 | #define L4_WKUP_BASE 0x48300000 |
| 30 | #define L4_PER_BASE 0x49000000 |
| 31 | #define L4_EMU_BASE 0x54000000 |
| 32 | #define GFX_BASE 0x50000000 |
| 33 | #define L3_BASE 0x68000000 |
| 34 | #define SMS_BASE 0x6C000000 |
| 35 | #define SDRC_BASE 0x6D000000 |
| 36 | #define GPMC_BASE 0x6E000000 |
| 37 | #define SCM_BASE 0x48002000 |
| 38 | |
| 39 | /* clocks */ |
| 40 | #define CM_CLKSEL_PER (L4_BASE + 0x5040) |
| 41 | |
| Travis Geiselbrecht | 2c691e8 | 2008-09-04 02:41:01 -0700 | [diff] [blame] | 42 | /* PRCM */ |
| 43 | #define CM_FCLKEN_IVA2 (L4_BASE + 0x4000) |
| 44 | #define CM_CLKEN_PLL_IVA2 (L4_BASE + 0x4004) |
| 45 | #define CM_IDLEST_PLL_IVA2 (L4_BASE + 0x4024) |
| 46 | #define CM_CLKSEL1_PLL_IVA2 (L4_BASE + 0x4040) |
| 47 | #define CM_CLKSEL2_PLL_IVA2 (L4_BASE + 0x4044) |
| 48 | #define CM_CLKEN_PLL_MPU (L4_BASE + 0x4904) |
| 49 | #define CM_IDLEST_PLL_MPU (L4_BASE + 0x4924) |
| 50 | #define CM_CLKSEL1_PLL_MPU (L4_BASE + 0x4940) |
| 51 | #define CM_CLKSEL2_PLL_MPU (L4_BASE + 0x4944) |
| 52 | #define CM_FCLKEN1_CORE (L4_BASE + 0x4a00) |
| 53 | #define CM_ICLKEN1_CORE (L4_BASE + 0x4a10) |
| 54 | #define CM_ICLKEN2_CORE (L4_BASE + 0x4a14) |
| 55 | #define CM_CLKSEL_CORE (L4_BASE + 0x4a40) |
| 56 | #define CM_FCLKEN_GFX (L4_BASE + 0x4b00) |
| 57 | #define CM_ICLKEN_GFX (L4_BASE + 0x4b10) |
| 58 | #define CM_CLKSEL_GFX (L4_BASE + 0x4b40) |
| 59 | #define CM_FCLKEN_WKUP (L4_BASE + 0x4c00) |
| 60 | #define CM_ICLKEN_WKUP (L4_BASE + 0x4c10) |
| 61 | #define CM_CLKSEL_WKUP (L4_BASE + 0x4c40) |
| 62 | #define CM_IDLEST_WKUP (L4_BASE + 0x4c20) |
| 63 | #define CM_CLKEN_PLL (L4_BASE + 0x4d00) |
| 64 | #define CM_IDLEST_CKGEN (L4_BASE + 0x4d20) |
| 65 | #define CM_CLKSEL1_PLL (L4_BASE + 0x4d40) |
| 66 | #define CM_CLKSEL2_PLL (L4_BASE + 0x4d44) |
| 67 | #define CM_CLKSEL3_PLL (L4_BASE + 0x4d48) |
| 68 | #define CM_FCLKEN_DSS (L4_BASE + 0x4e00) |
| 69 | #define CM_ICLKEN_DSS (L4_BASE + 0x4e10) |
| 70 | #define CM_CLKSEL_DSS (L4_BASE + 0x4e40) |
| 71 | #define CM_FCLKEN_CAM (L4_BASE + 0x4f00) |
| 72 | #define CM_ICLKEN_CAM (L4_BASE + 0x4f10) |
| 73 | #define CM_CLKSEL_CAM (L4_BASE + 0x4F40) |
| 74 | #define CM_FCLKEN_PER (L4_BASE + 0x5000) |
| 75 | #define CM_ICLKEN_PER (L4_BASE + 0x5010) |
| 76 | #define CM_CLKSEL_PER (L4_BASE + 0x5040) |
| 77 | #define CM_CLKSEL1_EMU (L4_BASE + 0x5140) |
| 78 | |
| 79 | #define PRM_CLKSEL (L4_BASE + 0x306d40) |
| 80 | #define PRM_RSTCTRL (L4_BASE + 0x307250) |
| 81 | #define PRM_CLKSRC_CTRL (L4_BASE + 0x307270) |
| 82 | |
| Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 83 | /* General Purpose Timers */ |
| 84 | #define OMAP34XX_GPT1 (L4_BASE + 0x318000) |
| 85 | #define OMAP34XX_GPT2 (L4_BASE + 0x1032000) |
| 86 | #define OMAP34XX_GPT3 (L4_BASE + 0x1034000) |
| 87 | #define OMAP34XX_GPT4 (L4_BASE + 0x1036000) |
| 88 | #define OMAP34XX_GPT5 (L4_BASE + 0x1038000) |
| 89 | #define OMAP34XX_GPT6 (L4_BASE + 0x103A000) |
| 90 | #define OMAP34XX_GPT7 (L4_BASE + 0x103C000) |
| 91 | #define OMAP34XX_GPT8 (L4_BASE + 0x103E000) |
| 92 | #define OMAP34XX_GPT9 (L4_BASE + 0x1040000) |
| 93 | #define OMAP34XX_GPT10 (L4_BASE + 0x86000) |
| 94 | #define OMAP34XX_GPT11 (L4_BASE + 0x88000) |
| 95 | #define OMAP34XX_GPT12 (L4_BASE + 0x304000) |
| 96 | |
| 97 | #define TIDR 0x00 |
| 98 | #define TIOCP_CFG 0x10 |
| 99 | #define TISTAT 0x14 |
| 100 | #define TISR 0x18 |
| 101 | #define TIER 0x1C |
| 102 | #define TWER 0x20 |
| 103 | #define TCLR 0x24 |
| 104 | #define TCRR 0x28 |
| 105 | #define TLDR 0x2C |
| 106 | #define TTGR 0x30 |
| 107 | #define TWPS 0x34 |
| 108 | #define TMAR 0x38 |
| 109 | #define TCAR1 0x3C |
| 110 | #define TSICR 0x40 |
| 111 | #define TCAR2 0x44 |
| 112 | #define TPIR 0x48 |
| 113 | #define TNIR 0x4C |
| 114 | #define TCVR 0x50 |
| 115 | #define TOCR 0x54 |
| 116 | #define TOWR 0x58 |
| 117 | |
| 118 | /* WatchDog Timers (1 secure, 3 GP) */ |
| 119 | #define WD1_BASE (0x4830C000) |
| 120 | #define WD2_BASE (0x48314000) |
| 121 | #define WD3_BASE (0x49030000) |
| 122 | |
| 123 | #define WIDR 0x00 |
| 124 | #define WD_SYSCONFIG 0x10 |
| 125 | #define WD_SYSSTATUS 0x14 |
| 126 | #define WISR 0x18 |
| 127 | #define WIER 0x1C |
| 128 | #define WCLR 0x24 |
| 129 | #define WCRR 0x28 |
| 130 | #define WLDR 0x2C |
| 131 | #define WTGR 0x30 |
| 132 | #define WWPS 0x34 |
| 133 | #define WSPR 0x48 |
| 134 | |
| 135 | #define W_PEND_WCLR (1<<0) |
| 136 | #define W_PEND_WCRR (1<<1) |
| 137 | #define W_PEND_WLDR (1<<2) |
| 138 | #define W_PEND_WTGR (1<<3) |
| 139 | #define W_PEND_WSPR (1<<4) |
| 140 | |
| 141 | #define WD_UNLOCK1 0xAAAA |
| 142 | #define WD_UNLOCK2 0x5555 |
| 143 | |
| 144 | /* 32KTIMER */ |
| 145 | #define TIMER32K_BASE (L4_BASE + 0x320000) |
| 146 | #define TIMER32K_REV (TIMER32K_BASE + 0x00) |
| 147 | #define TIMER32K_CR (TIMER32K_BASE + 0x10) |
| 148 | |
| 149 | /* UART */ |
| 150 | #define OMAP_UART1_BASE (L4_BASE + 0x6a000) |
| 151 | #define OMAP_UART2_BASE (L4_BASE + 0x6c000) |
| 152 | #define OMAP_UART3_BASE (L4_BASE + 0x01020000) |
| 153 | |
| 154 | #define UART_RHR 0 |
| 155 | #define UART_THR 0 |
| 156 | #define UART_DLL 0 |
| 157 | #define UART_IER 1 |
| 158 | #define UART_DLH 1 |
| 159 | #define UART_IIR 2 |
| 160 | #define UART_FCR 2 |
| 161 | #define UART_EFR 2 |
| 162 | #define UART_LCR 3 |
| 163 | #define UART_MCR 4 |
| 164 | #define UART_LSR 5 |
| 165 | #define UART_MSR 6 |
| 166 | #define UART_TCR 6 |
| 167 | #define UART_SPR 7 |
| 168 | #define UART_TLR 7 |
| 169 | #define UART_MDR1 8 |
| 170 | #define UART_MDR2 9 |
| 171 | #define UART_SFLSR 10 |
| 172 | #define UART_RESUME 11 |
| 173 | #define UART_TXFLL 10 |
| 174 | #define UART_TXFLH 11 |
| 175 | #define UART_SFREGL 12 |
| 176 | #define UART_SFREGH 13 |
| 177 | #define UART_RXFLL 12 |
| 178 | #define UART_RXFLH 13 |
| 179 | #define UART_BLR 14 |
| 180 | #define UART_UASR 14 |
| 181 | #define UART_ACREG 15 |
| 182 | #define UART_SCR 16 |
| 183 | #define UART_SSR 17 |
| 184 | #define UART_EBLR 18 |
| 185 | #define UART_MVR 19 |
| 186 | #define UART_SYSC 20 |
| 187 | |
| 188 | /* MPU INTC */ |
| 189 | #define INTC_BASE (L4_BASE + 0x200000) |
| 190 | #define INTC_REVISION (INTC_BASE + 0x000) |
| 191 | #define INTC_SYSCONFIG (INTC_BASE + 0x010) |
| 192 | #define INTC_SYSSTATUS (INTC_BASE + 0x014) |
| 193 | #define INTC_SIR_IRQ (INTC_BASE + 0x040) |
| 194 | #define INTC_SIR_FIQ (INTC_BASE + 0x044) |
| 195 | #define INTC_CONTROL (INTC_BASE + 0x048) |
| 196 | #define INTC_PROTECTION (INTC_BASE + 0x04C) |
| 197 | #define INTC_IDLE (INTC_BASE + 0x050) |
| 198 | #define INTC_IRQ_PRIORITY (INTC_BASE + 0x060) |
| 199 | #define INTC_FIQ_PRIORITY (INTC_BASE + 0x064) |
| 200 | #define INTC_THRESHOLD (INTC_BASE + 0x068) |
| 201 | #define INTC_ITR(n) (INTC_BASE + 0x080 + (n) * 0x20) |
| 202 | #define INTC_MIR(n) (INTC_BASE + 0x084 + (n) * 0x20) |
| 203 | #define INTC_MIR_CLEAR(n) (INTC_BASE + 0x088 + (n) * 0x20) |
| 204 | #define INTC_MIR_SET(n) (INTC_BASE + 0x08C + (n) * 0x20) |
| 205 | #define INTC_ISR_SET(n) (INTC_BASE + 0x090 + (n) * 0x20) |
| 206 | #define INTC_ISR_CLEAR(n) (INTC_BASE + 0x094 + (n) * 0x20) |
| 207 | #define INTC_PENDING_IRQ(n) (INTC_BASE + 0x098 + (n) * 0x20) |
| 208 | #define INTC_PENDING_FIQ(n) (INTC_BASE + 0x09C + (n) * 0x20) |
| 209 | #define INTC_ILR(n) (INTC_BASE + 0x100 + (n) * 4) |
| 210 | |
| 211 | /* interrupts */ |
| 212 | #define INT_VECTORS 96 |
| 213 | #define GPT2_IRQ 38 |
| 214 | |
| Travis Geiselbrecht | 2c691e8 | 2008-09-04 02:41:01 -0700 | [diff] [blame] | 215 | /* HS USB */ |
| 216 | #define USB_HS_BASE (L4_BASE + 0xab000) |
| 217 | |
| 218 | /* USB OTG */ |
| 219 | #define OTG_BASE (L4_BASE + 0xab400) |
| 220 | |
| 221 | #define OTG_REVISION (OTG_BASE + 0x00) |
| 222 | #define OTG_SYSCONFIG (OTG_BASE + 0x04) |
| 223 | #define OTG_SYSSTATUS (OTG_BASE + 0x08) |
| 224 | #define OTG_INTERFSEL (OTG_BASE + 0x0C) |
| 225 | #define OTG_SIMENABLE (OTG_BASE + 0x10) |
| 226 | #define OTG_FORCESTDBY (OTG_BASE + 0x14) |
| 227 | |
| Travis Geiselbrecht | bea5a4a | 2008-09-06 01:32:02 -0700 | [diff] [blame] | 228 | /* I2C */ |
| 229 | #define I2C1_BASE (L4_BASE + 0x70000) |
| 230 | #define I2C2_BASE (L4_BASE + 0x72000) |
| 231 | #define I2C3_BASE (L4_BASE + 0x60000) |
| 232 | |
| 233 | #define I2C_REV (0x00) |
| 234 | #define I2C_IE (0x04) |
| 235 | #define I2C_STAT (0x08) |
| 236 | #define I2C_WE (0x0C) |
| 237 | #define I2C_SYSS (0x10) |
| 238 | #define I2C_BUF (0x14) |
| 239 | #define I2C_CNT (0x18) |
| 240 | #define I2C_DATA (0x1C) |
| 241 | #define I2C_SYSC (0x20) |
| 242 | #define I2C_CON (0x24) |
| 243 | #define I2C_OA0 (0x28) |
| 244 | #define I2C_SA (0x2C) |
| 245 | #define I2C_PSC (0x30) |
| 246 | #define I2C_SCLL (0x34) |
| 247 | #define I2C_SCLH (0x38) |
| 248 | #define I2C_SYSTEST (0x3C) |
| 249 | #define I2C_BUFSTAT (0x40) |
| 250 | #define I2C_OA1 (0x44) |
| 251 | #define I2C_OA2 (0x48) |
| 252 | #define I2C_OA3 (0x4C) |
| 253 | #define I2C_ACTOA (0x50) |
| 254 | #define I2C_SBLOCK (0x54) |
| 255 | |
| Travis Geiselbrecht | 1d0df69 | 2008-09-01 02:26:09 -0700 | [diff] [blame] | 256 | #endif |
| 257 | |