Blame - target/surf-msm7k/panel.c - kernel/lk

Dima Zavin

36785e3

2009-01-28 17:26:43 -0800

[diff] [blame]

#include <debug.h>

#include <dev/gpio.h>

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#include <kernel/thread.h>

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#include <platform/mddi.h>

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#define MDDI_CLIENT_CORE_BASE 0x108000

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#define LCD_CONTROL_BLOCK_BASE 0x110000

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#define SPI_BLOCK_BASE 0x120000

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#define I2C_BLOCK_BASE 0x130000

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#define PWM_BLOCK_BASE 0x140000

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#define GPIO_BLOCK_BASE 0x150000

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#define SYSTEM_BLOCK1_BASE 0x160000

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#define SYSTEM_BLOCK2_BASE 0x170000

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#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)

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#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)

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#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)

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#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)

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#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)

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#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)

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#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)

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#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)

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#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)

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#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)

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#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)

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#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)

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#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)

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#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)

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#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)

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#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)

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#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)

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#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)

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#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)

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#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)

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#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)

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#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)

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#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)

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#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)

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#define START (LCD_CONTROL_BLOCK_BASE|0x08)

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#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)

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#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)

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#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)

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#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)

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#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)

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#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)

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#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)

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#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)

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#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)

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#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)

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#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)

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#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)

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#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)

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#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)

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#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)

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#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)

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#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)

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#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)

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#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)

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#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)

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#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)

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#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)

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#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)

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#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)

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#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)

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#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)

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#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)

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#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)

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#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)

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#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)

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#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)

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#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)

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#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0)

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#define Current (LCD_CONTROL_BLOCK_BASE|0xC0)

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#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)

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#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)

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#define SSICTL (SPI_BLOCK_BASE|0x00)

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#define SSITIME (SPI_BLOCK_BASE|0x04)

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#define SSITX (SPI_BLOCK_BASE|0x08)

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#define SSIRX (SPI_BLOCK_BASE|0x0C)

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#define SSIINTC (SPI_BLOCK_BASE|0x10)

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#define SSIINTS (SPI_BLOCK_BASE|0x14)

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#define SSIDBG1 (SPI_BLOCK_BASE|0x18)

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#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)

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#define SSIID (SPI_BLOCK_BASE|0x20)

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#define I2CSETUP (I2C_BLOCK_BASE|0x00)

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#define I2CCTRL (I2C_BLOCK_BASE|0x04)

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#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)

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#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)

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#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)

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#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C)

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#define TIMER0RIS (PWM_BLOCK_BASE|0x10)

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#define TIMER0MIS (PWM_BLOCK_BASE|0x14)

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#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18)

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#define PWM0OFF (PWM_BLOCK_BASE|0x1C)

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#define TIMER1LOAD (PWM_BLOCK_BASE|0x20)

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#define TIMER1VALUE (PWM_BLOCK_BASE|0x24)

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#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28)

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#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C)

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#define TIMER1RIS (PWM_BLOCK_BASE|0x30)

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#define TIMER1MIS (PWM_BLOCK_BASE|0x34)

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#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38)

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#define PWM1OFF (PWM_BLOCK_BASE|0x3C)

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#define TIMERITCR (PWM_BLOCK_BASE|0x60)

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#define TIMERITOP (PWM_BLOCK_BASE|0x64)

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#define PWMCR (PWM_BLOCK_BASE|0x68)

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#define PWMID (PWM_BLOCK_BASE|0x6C)

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#define PWMMON (PWM_BLOCK_BASE|0x70)

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#define GPIODATA (GPIO_BLOCK_BASE|0x00)

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#define GPIODIR (GPIO_BLOCK_BASE|0x04)

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#define GPIOIS (GPIO_BLOCK_BASE|0x08)

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#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)

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#define GPIOIEV (GPIO_BLOCK_BASE|0x10)

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#define GPIOIE (GPIO_BLOCK_BASE|0x14)

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#define GPIORIS (GPIO_BLOCK_BASE|0x18)

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#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)

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#define GPIOIC (GPIO_BLOCK_BASE|0x20)

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#define GPIOOMS (GPIO_BLOCK_BASE|0x24)

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#define GPIOPC (GPIO_BLOCK_BASE|0x28)

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#define GPIOID (GPIO_BLOCK_BASE|0x30)

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#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)

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#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)

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#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)

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#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)

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#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)

struct init_table {

unsigned int reg;

unsigned int val;

};

static struct init_table toshiba_480x640_init_table[] = {

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{ DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters

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{ DPSET1, 0x00000113 }, // # MDC.DPSET1

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{ DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable

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{ DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL

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{ 0, 14 }, // wait_ms(14);

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{ SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output

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{ CLKENB, 0x000000EF }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)

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{ GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0

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{ GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)

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{ SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control

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{ GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut

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{ SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment

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{ GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO

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{ GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO

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{ GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear

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{ GPIO_BLOCK_BASE, 0x00060006 }, // # GPI .GPIODATA # Release LCDD reset

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{ GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply

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{ GPIO_BLOCK_BASE, 0x02000200 }, // # GPI .GPIODATA # TEST LED ON

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{ DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up

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{ TIMER0CONTROL, 0x00000060 }, // # PWM.Timer0Control # PWM0 output stop

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{ PWM_BLOCK_BASE, 0x00001388 }, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF)

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//{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF

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#if 0

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{ PWM0OFF, 0x00001387 }, // SURF 100% backlight

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{ PWM0OFF, 0x00000000 }, // FFA 100% backlight

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#endif

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{ PWM0OFF, 0x000009C3 }, // 50% BL

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{ TIMER1CONTROL, 0x00000060 }, // # PWM.Timer1Control # PWM1 output stop

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{ TIMER1LOAD, 0x00001388 }, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF)

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//{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF

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{ PWM1OFF, 0x00001387 },

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{ TIMER0CONTROL, 0x000000E0 }, // # PWM.Timer0Control # PWM0 output start

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{ TIMER1CONTROL, 0x000000E0 }, // # PWM.Timer1Control # PWM1 output start

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{ PWMCR, 0x00000003 }, // # PWM.PWMCR # PWM output enable

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{ 0, 1 }, // wait_ms(1);

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{ SPI_BLOCK_BASE, 0x00000799 }, // # SPI .SSICTL # SPI operation mode setting

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{ SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting

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{ SPI_BLOCK_BASE, 0x0000079b }, // # SPI .SSICTL # Set SPI active mode

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{ SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode

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{ 0, 1 }, // wait_ms(1);

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{ SSITX, 0x00000000 }, // # SPI.SSITX

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{ 0, 1 }, // wait_ms(1);

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{ SSITX, 0x00000000 }, // # SPI.SSITX

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{ 0, 1 }, // wait_ms(1);

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{ SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block

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{ SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black

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{ SSITX, 0x00080036 }, // # Command setting of SPI block

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{ SSITX, 0x00000100 }, // # Memory access control

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800BB }, // # Command setting of SPI block

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{ SSITX, 0x00000100 }, // # Display mode setup(2)

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{ SSITX, 0x0008003A }, // # Command setting of SPI block

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{ SSITX, 0x00000160 }, // # RGB Interface data format

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800BF }, // # Command setting of SPI block

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{ SSITX, 0x00000100 }, // # Drivnig method

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{ SSITX, 0x000800B1 }, // # Command setting of SPI block

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{ SSITX, 0x0000015D }, // # Booster operation setup

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800B2 }, // # Command setting of SPI block

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{ SSITX, 0x00000133 }, // # Booster mode setup

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{ SSITX, 0x000800B3 }, // # Command setting of SPI block

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{ SSITX, 0x00000122 }, // # Booster frequencies setup

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800B4 }, // # Command setting of SPI block

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{ SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup

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{ SSITX, 0x000800B5 }, // # Command setting of SPI block

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{ SSITX, 0x0000011F }, // # VCS Voltage adjustment (1C->1F for Rev 2)

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800B6 }, // # Command setting of SPI block

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{ SSITX, 0x00000128 }, // # VCOM Voltage adjustment

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{ SSITX, 0x000800B7 }, // # Command setting of SPI block

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{ SSITX, 0x00000103 }, // # Configure an external display signal

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800B9 }, // # Command setting of SPI block

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{ SSITX, 0x00000120 }, // # DCCK/DCEV timing setup

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{ SSITX, 0x000800BD }, // # Command setting of SPI block

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{ SSITX, 0x00000102 }, // # ASW signal control

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800BE }, // # Command setting of SPI block

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{ SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation

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{ SSITX, 0x000800C0 }, // # Command setting of SPI block

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{ SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800C1 }, // # Command setting of SPI block

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{ SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)

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{ SSITX, 0x000800C2 }, // # Command setting of SPI block

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{ SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800C3 }, // # Command setting of SPI block

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{ SSITX, 0x0008010A }, // # wait_ms(-in line clock count setup (D)

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{ SSITX, 0x0000010A }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800C4 }, // # Command setting of SPI block

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{ SSITX, 0x00080160 }, // # Seep-in line clock count setup (E)

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{ SSITX, 0x00000160 }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800C5 }, // # Command setting of SPI block

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{ SSITX, 0x00080160 }, // # wait_ms(-in line clock count setup (F)

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{ SSITX, 0x00000160 }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800C6 }, // # Command setting of SPI block

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{ SSITX, 0x00080160 }, // # wait_ms(-in line clock setup (G)

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{ SSITX, 0x00000160 }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800C7 }, // # Command setting of SPI block

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{ SSITX, 0x00080133 }, // # Gamma 1 fine tuning (1)

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{ SSITX, 0x00000143 }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800C8 }, // # Command setting of SPI block

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{ SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)

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{ SSITX, 0x000800C9 }, // # Command setting of SPI block

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{ SSITX, 0x00000133 }, // # Gamma 1 inclination adjustment

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800CA }, // # Command setting of SPI block

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{ SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800EC }, // # Command setting of SPI block

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{ SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]

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{ SSITX, 0x00000118 }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800CF }, // # Command setting of SPI block

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{ SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800D0 }, // # Command setting of SPI block

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{ SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]

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{ SSITX, 0x00000104 }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800D1 }, // # Command setting of SPI block

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{ SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800D2 }, // # Command setting of SPI block

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{ SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]

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{ SSITX, 0x0000013A }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800D3 }, // # Command setting of SPI block

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{ SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]

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{ SSITX, 0x0000013A }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800D4 }, // # Command setting of SPI block

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{ SSITX, 0x00080124 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]

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{ SSITX, 0x0000016E }, //

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{ 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty

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{ SSITX, 0x000800D5 }, // # Command setting of SPI block

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{ SSITX, 0x00000124 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800ED }, // # Command setting of SPI block

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{ SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]

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{ SSITX, 0x0000010A }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800D6 }, // # Command setting of SPI block

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{ SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA]

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800D7 }, // # Command setting of SPI block

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{ SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA]

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{ SSITX, 0x0000010A }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800D8 }, // # Command setting of SPI block

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{ SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA]

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800D9 }, // # Command setting of SPI block

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{ SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA]

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{ SSITX, 0x00000114 }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800DE }, // # Command setting of SPI block

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{ SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table2 for QVGA]

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{ SSITX, 0x00000114 }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800DF }, // # Command setting of SPI block

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{ SSITX, 0x00080112 }, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA]

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{ SSITX, 0x0000013F }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800E0 }, // # Command setting of SPI block

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{ SSITX, 0x0000010B }, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA]

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{ SSITX, 0x000800E2 }, // # Command setting of SPI block

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{ SSITX, 0x00000101 }, // # Built-in oscillator frequency division setup [Frequency division ratio : 2 (60Hq)

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800E3 }, // # Command setting of SPI block

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{ SSITX, 0x00000136 }, // # Built-in oscillator clock count setup

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800E4 }, // # Command setting of SPI block

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{ SSITX, 0x00080100 }, // # CKV timing control for using build-in osc

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{ SSITX, 0x00000103 }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800E5 }, // # Command setting of SPI block

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{ SSITX, 0x00080102 }, // # OEV timing control for using build-in osc

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{ SSITX, 0x00000104 }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800E6 }, // # Command setting of SPI block

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{ SSITX, 0x00000103 }, // # DCEV timing control for using build-in osc

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800E7 }, // # Command setting of SPI block

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{ SSITX, 0x00080104 }, // # ASW timing setup for using build-in osc(1)

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{ SSITX, 0x0000010A }, //

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{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty

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{ SSITX, 0x000800E8 }, // # Command setting of SPI block

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{ SSITX, 0x00000104 }, // # ASW timing setup for using build-in osc(2)

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{ CLKENB, 0x000001EF }, // # SYS.CLKENB # DCLK enable

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{ START, 0x00000000 }, // # LCD.START # LCDC wait_ms( mode

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{ WRSTB, 0x0000003F }, // # LCD.WRSTB # write_client_reg( strobe

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{ RDSTB, 0x00000432 }, // # LCD.RDSTB # Read strobe

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{ PORT_ENB, 0x00000002 }, // # LCD.PORT_ENB # Asynchronous port enable

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{ VSYNIF, 0x00000000 }, // # LCD.VSYNCIF # VSYNC I/F mode set

357

{ ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # Index setting of SUB LCDD

358

{ ASY_DATB, 0x00000001 }, // # Oscillator start

359

{ ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable

360

{ ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable

361

{ 0, 10 }, // wait_ms(10);

362

{ ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # DUMMY write_client_reg(@*NOTE2

363

{ ASY_DATB, 0x80000000 }, //

364

{ ASY_DATC, 0x80000000 }, //

365

{ ASY_DATD, 0x80000000 }, //

366

{ ASY_CMDSET, 0x00000009 }, // # LCD.ASY_CMDSET

367

{ ASY_CMDSET, 0x00000008 }, // # LCD.ASY_CMDSET

368

{ ASY_DATA, 0x80000007 }, // # LCD.ASY_DATx # Index setting of SUB LCDD

369

{ ASY_DATB, 0x00004005 }, // # LCD driver control

370

{ ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable

371

{ ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable

372

{ 0, 20 }, // wait_ms(20);

373

{ ASY_DATA, 0x80000059 }, // # LCD.ASY_DATx # Index setting of SUB LCDD

374

{ ASY_DATB, 0x00000000 }, // # LTPS I/F control

375

{ ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable

376

{ ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable

377

378

{ VSYNIF, 0x00000001 }, // # LCD.VSYNCIF # VSYNC I/F mode OFF

379

{ PORT_ENB, 0x00000001 }, // # LCD.PORT_ENB # SYNC I/F output select

380

381

/******************************/

382

383

{ VSYNIF, 0x00000001 }, // VSYNC I/F mode OFF

384

{ PORT_ENB, 0x00000001 }, // SYNC I/F mode ON

385

386

{ BITMAP1, 0x01E000F0 }, // MDC.BITMAP2 ); // Setup of PITCH size to Frame buffer1

387

{ BITMAP2, 0x01E000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2

388

{ BITMAP3, 0x01E000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3

389

{ BITMAP4, 0x00DC00B0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4

390

{ CLKENB, 0x000001EF }, // SYS.CLKENB ); // DCLK supply

391

{ PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable

392

{ PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active

393

{ PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)

394

{ MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer

395

{ HCYCLE, 0x0000010b }, // LCD.HCYCLE ); // Setup to VGA size

396

{ HSW, 0x00000003 }, // LCD.HSW

397

{ HDE_START, 0x00000007 }, // LCD.HDE_START

398

{ HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE

399

{ VCYCLE, 0x00000285 }, // LCD.VCYCLE

400

{ VSW, 0x00000001 }, // LCD.VSW

401

{ VDE_START, 0x00000003 }, // LCD.VDE_START

402

{ VDE_SIZE, 0x0000027F }, // LCD.VDE_SIZE

403

404

{ START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start

405

406

{ 0, 10 }, // wait_ms( 10 );

407

{ SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block

408

{ SSITX, 0x00000180 }, // Display data setup

409

{ SSITX, 0x0008003B }, // Command setting of SPI block

410

{ SSITX, 0x00000100 }, // Quad Data configuration - VGA

411

{ 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty

412

{ SSITX, 0x000800B0 }, // Command setting of SPI block

413

{ SSITX, 0x00000116 }, // Power supply ON/OFF control

414

{ 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty

415

{ SSITX, 0x000800B8 }, // Command setting of SPI block

416

{ SSITX, 0x000801FF }, // Output control

417

{ SSITX, 0x000001F5 },

418

{ 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty

419

{ SSITX, 0x00000011 }, // wait_ms(-out (Command only)

420

{ SSITX, 0x00000029 }, // Display on (Command only)

421

422

{ SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO

{ 0, 0 }

};

static void _panel_init(struct init_table *init_table)

{

unsigned n;

dprintf(INFO, "panel_init()\n");

432

433

n = 0;

434

while (init_table[n].reg != 0 || init_table[n].val != 0) {

435

if (init_table[n].reg != 0)

436

mddi_remote_write(init_table[n].val, init_table[n].reg);

437

else

438

thread_sleep(init_table[n].val);//mdelay(init_table[n].val);

n++;

}

dprintf(INFO, "panel_init() done\n");

443

}

444

445

void panel_init(struct mddi_client_caps *client_caps)

446

{

447

switch(client_caps->manufacturer_name) {

448

case 0xd263: // Toshiba

449

dprintf(INFO, "Found Toshiba panel\n");

450

_panel_init(toshiba_480x640_init_table);

451

break;

452

case 0x4474: //??

453

if (client_caps->product_code == 0xc065)

454

dprintf(INFO, "Found WVGA panel\n");

break;

}

}

void panel_poweron(void)

460

{

461

gpio_set(88, 0);

462

gpio_config(88, GPIO_OUTPUT);

463

thread_sleep(1); //udelay(10);

464

gpio_set(88, 1);

465

thread_sleep(10); //mdelay(10);

466

467

//mdelay(1000); // uncomment for second stage boot

468

}

469

470

void panel_backlight(int on)

471

{}