Amol Jadi | f2f4560 | 2011-05-24 15:46:01 -0700 | [diff] [blame] | 1 | /* |
Sangani Suryanarayana Raju | 6a2e9df | 2013-06-07 16:44:01 +0530 | [diff] [blame] | 2 | * Copyright (c) 2011-2013, Linux Foundation. All rights reserved. |
Amol Jadi | f2f4560 | 2011-05-24 15:46:01 -0700 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are |
| 6 | * met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above |
| 10 | * copyright notice, this list of conditions and the following |
| 11 | * disclaimer in the documentation and/or other materials provided |
| 12 | * with the distribution. |
Channagoud Kadabi | c7b9091 | 2012-10-25 14:17:42 +0530 | [diff] [blame] | 13 | * * Neither the name of Linux Foundation, Inc. nor the names of its |
Amol Jadi | f2f4560 | 2011-05-24 15:46:01 -0700 | [diff] [blame] | 14 | * contributors may be used to endorse or promote products derived |
| 15 | * from this software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 21 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 24 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 25 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 26 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 27 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | */ |
Channagoud Kadabi | c7b9091 | 2012-10-25 14:17:42 +0530 | [diff] [blame] | 29 | #include <bits.h> |
Amol Jadi | f2f4560 | 2011-05-24 15:46:01 -0700 | [diff] [blame] | 30 | |
Amol Jadi | 3570f9d | 2011-05-27 13:57:44 -0700 | [diff] [blame] | 31 | #define PBL_ACCESS_2 0x005 |
| 32 | #define PBL_ACCESS_2_ENUM_TIMER_STOP (1 << 1) |
Amol Jadi | f2f4560 | 2011-05-24 15:46:01 -0700 | [diff] [blame] | 33 | |
Amol Jadi | 3570f9d | 2011-05-27 13:57:44 -0700 | [diff] [blame] | 34 | #define SYS_CONFIG_2 0x007 |
| 35 | #define SYS_CONFIG_2_BOOT_DONE (1 << 6) |
| 36 | #define SYS_CONFIG_2_ADAPTIVE_BOOT_DISABLE (1 << 7) |
| 37 | |
Amol Jadi | 60a5597 | 2011-06-10 18:50:47 -0700 | [diff] [blame] | 38 | #define PM8921_LDO_REG_BASE 0x0AE |
| 39 | #define PM8921_LDO_CTRL_REG(id) (PM8921_LDO_REG_BASE + (2 * (id-1))) |
| 40 | #define PM8921_LDO_TEST_REG(id) (PM8921_LDO_CTRL_REG(id) + 1) |
| 41 | |
| 42 | /* Bit offsets LDO CTRL register */ |
| 43 | #define PM8921_LDO_CTRL_REG_ENABLE 7 |
| 44 | #define PM8921_LDO_CTRL_REG_PULL_DOWN 6 |
| 45 | #define PM8921_LDO_CTRL_REG_POWER_MODE 5 |
| 46 | #define PM8921_LDO_CTRL_REG_VOLTAGE 0 |
| 47 | |
| 48 | /* Bit offsets LDO Test register */ |
| 49 | #define PM8921_LDO_TEST_REG_BANK_SEL 4 |
| 50 | #define PM8921_LDO_TEST_REG_RW 7 |
| 51 | #define PM8921_LDO_TEST_REG_BANK2_RANGE_SEL 2 |
| 52 | #define PM8921_LDO_TEST_REG_BANK2_FINE_STEP 1 |
| 53 | #define PM8921_LDO_TEST_REG_BANK4_RANGE_EXT 0 |
| 54 | |
Amol Jadi | 3570f9d | 2011-05-27 13:57:44 -0700 | [diff] [blame] | 55 | #define GPIO_CNTL_BASE 0x150 |
| 56 | #define GPIO_CNTL(n) (GPIO_CNTL_BASE + n) |
| 57 | |
| 58 | /* GPIO Bank register programming */ |
| 59 | #define PM_GPIO_BANK_MASK 0x70 |
| 60 | #define PM_GPIO_BANK_SHIFT 4 |
| 61 | #define PM_GPIO_WRITE 0x80 |
| 62 | |
| 63 | /* Bank 0 */ |
| 64 | #define PM_GPIO_VIN_MASK 0x0E |
| 65 | #define PM_GPIO_VIN_SHIFT 1 |
| 66 | #define PM_GPIO_MODE_ENABLE 0x01 |
| 67 | |
| 68 | /* Bank 1 */ |
| 69 | #define PM_GPIO_MODE_MASK 0x0C |
| 70 | #define PM_GPIO_MODE_SHIFT 2 |
| 71 | #define PM_GPIO_OUT_BUFFER_OPEN_DRAIN 0x02 |
| 72 | #define PM_GPIO_OUT_INVERT 0x01 |
| 73 | |
| 74 | #define PM_GPIO_MODE_OFF 3 |
| 75 | #define PM_GPIO_MODE_OUTPUT 2 |
| 76 | #define PM_GPIO_MODE_INPUT 0 |
| 77 | #define PM_GPIO_MODE_BOTH 1 |
| 78 | |
| 79 | /* Bank 2 */ |
| 80 | #define PM_GPIO_PULL_MASK 0x0E |
| 81 | #define PM_GPIO_PULL_SHIFT 1 |
| 82 | |
| 83 | /* Bank 3 */ |
| 84 | #define PM_GPIO_OUT_STRENGTH_MASK 0x0C |
| 85 | #define PM_GPIO_OUT_STRENGTH_SHIFT 2 |
| 86 | #define PM_GPIO_PIN_ENABLE 0x00 |
| 87 | #define PM_GPIO_PIN_DISABLE 0x01 |
| 88 | |
| 89 | /* Bank 4 */ |
| 90 | #define PM_GPIO_FUNC_MASK 0x0E |
| 91 | #define PM_GPIO_FUNC_SHIFT 1 |
| 92 | |
| 93 | /* Bank 5 */ |
| 94 | #define PM_GPIO_NON_INT_POL_INV 0x08 |
| 95 | |
Shashank Mittal | 3950326 | 2011-07-19 11:41:35 -0700 | [diff] [blame] | 96 | /* PON CTRL 1 register */ |
| 97 | #define PM8921_PON_CTRL_1_REG 0x01C |
| 98 | |
| 99 | #define PON_CTRL_1_PULL_UP_MASK 0xE0 |
| 100 | #define PON_CTRL_1_USB_PWR_EN 0x10 |
| 101 | |
| 102 | #define PON_CTRL_1_WD_EN_MASK 0x08 |
| 103 | #define PON_CTRL_1_WD_EN_RESET 0x08 |
| 104 | #define PON_CTRL_1_WD_EN_PWR_OFF 0x00 |
| 105 | |
| 106 | /* SLEEP CTRL register */ |
| 107 | #define PM8921_SLEEP_CTRL_REG 0x10A |
| 108 | |
| 109 | #define SLEEP_CTRL_SMPL_EN_MASK 0x04 |
| 110 | #define SLEEP_CTRL_SMPL_EN_RESET 0x04 |
| 111 | #define SLEEP_CTRL_SMPL_EN_PWR_OFF 0x00 |
| 112 | |
Amol Jadi | 63f3da3 | 2011-09-15 18:57:40 -0700 | [diff] [blame] | 113 | #define IRQ_BLOCK_SEL_USR_ADDR 0x1C0 |
| 114 | #define IRQ_STATUS_RT_USR_ADDR 0x1C3 |
| 115 | |
Shashank Mittal | 1e2aad7 | 2012-03-08 17:10:14 -0800 | [diff] [blame] | 116 | #define PM8921_LVS_REG_BASE 0x060 |
| 117 | #define PM8921_LVS_CTRL_REG(id) (PM8921_LVS_REG_BASE + (2 * (id-1))) |
| 118 | #define PM8921_LVS_TEST_REG(id) (PM8921_LVS_CTRL_REG(id) + 1) |
| 119 | |
Channagoud Kadabi | d1412be | 2012-06-07 16:47:57 +0530 | [diff] [blame] | 120 | #define PM8921_RTC_CTRL 0x11D |
| 121 | #define PM8921_RTC_ALARM_ENABLE (1 << 1) |
| 122 | |
Shashank Mittal | 1e2aad7 | 2012-03-08 17:10:14 -0800 | [diff] [blame] | 123 | #define PM8921_LVS_100_CTRL_SW_EN (1 << 7) |
| 124 | #define PM8921_LVS_100_CTRL_SLEEP_B_IGNORE (1 << 4) |
| 125 | #define PM8921_LVS_100_TEST_VOUT_OK (1 << 6) |
| 126 | |
| 127 | #define PM8921_MPP_REG_BASE 0x050 |
| 128 | #define PM8921_MPP_CTRL_REG(id) (PM8921_MPP_REG_BASE + (id-1)) |
| 129 | |
| 130 | #define PM8921_MPP_CTRL_DIGITAL_OUTPUT (1 << 5) |
| 131 | #define PM8921_MPP_CTRL_VIO_1 (1 << 2) |
| 132 | #define PM8921_MPP_CTRL_OUTPUT_HIGH (1 << 0) |
Channagoud Kadabi | c7b9091 | 2012-10-25 14:17:42 +0530 | [diff] [blame] | 133 | |
| 134 | #define PM89XX_BAT_UP_THRESH_VOL 4 |
| 135 | #define PM89XX_BAT_ALRM_THRESH 0x23 |
| 136 | #define PM89XX_BAT_ALRM_CTRL 0x24 |
| 137 | #define PM89XX_USB_OVP_CTRL 0x21C |
| 138 | |
| 139 | #define PM89XX_BAT_ALRM_ENABLE BIT(7) |
| 140 | #define PM89XX_BAT_UPR_STATUS BIT(1) |
| 141 | #define PM89XX_BAT_LWR_STATUS BIT(0) |
| 142 | |
| 143 | #define PM89XX_VBUS_INPUT_STATUS BIT(0) |
| 144 | |
| 145 | /* voltages are specified in mV */ |
| 146 | #define PLDO_MV_VMIN 1500 |
| 147 | #define PLDO_MV_VMAX 3000 |
| 148 | #define PLDO_MV_VSTEP 50 |
| 149 | |
| 150 | #define NLDO_MV_VMIN 750 |
| 151 | #define NLDO_MV_VMAX 1525 |
| 152 | #define NLDO_MV_VSTEP 25 |
| 153 | |
| 154 | #define PLDO_TYPE 0 |
| 155 | #define NLDO_TYPE 1 |
| 156 | |
Sangani Suryanarayana Raju | 6a2e9df | 2013-06-07 16:44:01 +0530 | [diff] [blame] | 157 | #define SSBI_REG_ADDR_WLED_CTRL_BASE 0x25A |
| 158 | #define SSBI_REG_ADDR_WLED_CTRL(n) (SSBI_REG_ADDR_WLED_CTRL_BASE + (n) - 1) |
| 159 | |
| 160 | /* wled control registers */ |
| 161 | #define WLED_MOD_CTRL_REG SSBI_REG_ADDR_WLED_CTRL(1) |
| 162 | #define WLED_SYNC_REG SSBI_REG_ADDR_WLED_CTRL(11) |
| 163 | #define WLED_BOOST_CFG_REG SSBI_REG_ADDR_WLED_CTRL(14) |
| 164 | #define WLED_HIGH_POLE_CAP_REG SSBI_REG_ADDR_WLED_CTRL(16) |
| 165 | #define WLED_SYNC_VAL 0x07 |
| 166 | #define WLED_SYNC_RESET_VAL 0x00 |
| 167 | #define WLED_SYNC_MASK 0xF8 |
| 168 | |
Ajay Singh Parmar | cc6345a | 2013-02-13 20:30:49 +0530 | [diff] [blame] | 169 | #define PM8921_MVS_5V_HDMI_SWITCH 0x70 |
| 170 | |
Channagoud Kadabi | c7b9091 | 2012-10-25 14:17:42 +0530 | [diff] [blame] | 171 | #define LDO(_name, _type, _test_reg, _ctrl_reg) \ |
| 172 | {\ |
| 173 | .name = _name,\ |
| 174 | .type = _type,\ |
| 175 | .test_reg = _test_reg,\ |
| 176 | .ctrl_reg = _ctrl_reg, \ |
| 177 | } |
| 178 | |
| 179 | struct pm89xx_vreg ldo_data[] = { |
| 180 | LDO("LDO30", PLDO_TYPE, 0x0A3, 0x0A4), |
| 181 | LDO("LDO31", PLDO_TYPE, 0x0A5, 0x0A6), |
| 182 | LDO("LDO32", PLDO_TYPE, 0x0A7, 0x0A8), |
| 183 | LDO("LDO33", PLDO_TYPE, 0x0C6, 0x0C7), |
| 184 | LDO("LDO34", PLDO_TYPE, 0x0D2, 0x0D3), |
| 185 | LDO("LDO35", PLDO_TYPE, 0x0D4, 0x0D5), |
| 186 | LDO("LDO36", PLDO_TYPE, 0x0A9, 0x0AA), |
| 187 | }; |