blob: 5a614d3837c77051ec93e2cad8c7a3d71f741dab [file] [log] [blame]
Deepa Dinamani554b0622013-05-16 15:00:30 -07001/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29
30#ifndef __IRQS_APQ8084_H
31#define __IRQS_APQ8084_H
32
33/* MSM ACPU Interrupt Numbers */
34
35/* 0-15: STI/SGI (software triggered/generated interrupts)
36 * 16-31: PPI (private peripheral interrupts)
37 * 32+: SPI (shared peripheral interrupts)
38 */
39
40#define GIC_PPI_START 16
41#define GIC_SPI_START 32
42
43#define INT_QTMR_NON_SECURE_PHY_TIMER_EXP (GIC_PPI_START + 3)
44#define INT_QTMR_VIRTUAL_TIMER_EXP (GIC_PPI_START + 4)
45
46#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP (GIC_SPI_START + 8)
47
Deepa Dinamanieafb5ee2013-09-16 13:47:30 -070048#define UFS_IRQ (GIC_SPI_START + 28)
49
Amol Jadi0a4c9b42013-10-11 14:22:11 -070050#define USB30_EE1_IRQ (GIC_SPI_START + 131)
Deepa Dinamani554b0622013-05-16 15:00:30 -070051#define USB1_HS_BAM_IRQ (GIC_SPI_START + 135)
52#define USB1_HS_IRQ (GIC_SPI_START + 134)
53#define USB2_IRQ (GIC_SPI_START + 141)
54#define USB1_IRQ (GIC_SPI_START + 142)
55
56/* Retrofit universal macro names */
57#define INT_USB_HS USB1_HS_IRQ
58
59#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ (GIC_SPI_START + 190)
60
61#define NR_MSM_IRQS 256
62#define NR_GPIO_IRQS 173
63#define NR_BOARD_IRQS 0
64
65#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + \
66 NR_BOARD_IRQS)
67
Sundarajan Srinivasanf7ef47f2013-09-05 17:46:24 -070068#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 138)
69#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
70#define SDCC3_PWRCTL_IRQ (GIC_SPI_START + 224)
71#define SDCC4_PWRCTL_IRQ (GIC_SPI_START + 227)
Deepa Dinamani554b0622013-05-16 15:00:30 -070072#endif /* __IRQS_APQ8084_H */