blob: 7c93c8cbcd6680351ac6829419d781245a674b95 [file] [log] [blame]
Ajay Dudania66de4f2009-11-22 08:57:39 -08001/* Copyright 2007, Google Inc. */
2
3#include <debug.h>
4#include <dev/gpio.h>
5#include <kernel/thread.h>
Chandan Uddaraju2943fd62010-06-21 10:56:39 -07006#include <mddi.h>
Ajay Dudania66de4f2009-11-22 08:57:39 -08007
8#define MDDI_CLIENT_CORE_BASE 0x108000
9#define LCD_CONTROL_BLOCK_BASE 0x110000
10#define SPI_BLOCK_BASE 0x120000
11#define I2C_BLOCK_BASE 0x130000
12#define PWM_BLOCK_BASE 0x140000
13#define GPIO_BLOCK_BASE 0x150000
14#define SYSTEM_BLOCK1_BASE 0x160000
15#define SYSTEM_BLOCK2_BASE 0x170000
16
17
18#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
19#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
20#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
21#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
22#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
23#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
24#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
25#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
26#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
27#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
28#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
29#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
30#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
31#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
32#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
33#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
34#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
35#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
36#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
37#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
38#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
39#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
40
41
42#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
43#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
44#define START (LCD_CONTROL_BLOCK_BASE|0x08)
45#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
46#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
47#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
48#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
49#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
50#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
51#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
52#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
53
54#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
55#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
56#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
57#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
58#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
59#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
60#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
61#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
62#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
63#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
64#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
65#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
66#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
67#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
68#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
69#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
70#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
71#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
72#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
73#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
74#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
75#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
76#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
77#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
78
79#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0)
80
81#define Current (LCD_CONTROL_BLOCK_BASE|0xC0)
82#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)
83#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)
84
85
86#define SSICTL (SPI_BLOCK_BASE|0x00)
87#define SSITIME (SPI_BLOCK_BASE|0x04)
88#define SSITX (SPI_BLOCK_BASE|0x08)
89#define SSIRX (SPI_BLOCK_BASE|0x0C)
90#define SSIINTC (SPI_BLOCK_BASE|0x10)
91#define SSIINTS (SPI_BLOCK_BASE|0x14)
92#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
93#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
94#define SSIID (SPI_BLOCK_BASE|0x20)
95
96
97#define I2CSETUP (I2C_BLOCK_BASE|0x00)
98#define I2CCTRL (I2C_BLOCK_BASE|0x04)
99
100
101#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)
102#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)
103#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)
104#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C)
105#define TIMER0RIS (PWM_BLOCK_BASE|0x10)
106#define TIMER0MIS (PWM_BLOCK_BASE|0x14)
107#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18)
108#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
109#define TIMER1LOAD (PWM_BLOCK_BASE|0x20)
110#define TIMER1VALUE (PWM_BLOCK_BASE|0x24)
111#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28)
112#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C)
113#define TIMER1RIS (PWM_BLOCK_BASE|0x30)
114#define TIMER1MIS (PWM_BLOCK_BASE|0x34)
115#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38)
116#define PWM1OFF (PWM_BLOCK_BASE|0x3C)
117#define TIMERITCR (PWM_BLOCK_BASE|0x60)
118#define TIMERITOP (PWM_BLOCK_BASE|0x64)
119#define PWMCR (PWM_BLOCK_BASE|0x68)
120#define PWMID (PWM_BLOCK_BASE|0x6C)
121#define PWMMON (PWM_BLOCK_BASE|0x70)
122
123
124#define GPIODATA (GPIO_BLOCK_BASE|0x00)
125#define GPIODIR (GPIO_BLOCK_BASE|0x04)
126#define GPIOIS (GPIO_BLOCK_BASE|0x08)
127#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
128#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
129#define GPIOIE (GPIO_BLOCK_BASE|0x14)
130#define GPIORIS (GPIO_BLOCK_BASE|0x18)
131#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
132#define GPIOIC (GPIO_BLOCK_BASE|0x20)
133#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
134#define GPIOPC (GPIO_BLOCK_BASE|0x28)
135
136#define GPIOID (GPIO_BLOCK_BASE|0x30)
137
138
139#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
140#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
141#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
142#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
143#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
144
145struct init_table {
146 unsigned int reg;
147 unsigned int val;
148};
149
150static struct init_table toshiba_480x640_init_table[] = {
151 { DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
152 { DPSET1, 0x00000113 }, // # MDC.DPSET1
153 { DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
154 { DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
155 { 0, 14 }, // wait_ms(14);
156 { SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
157 { CLKENB, 0x000000EF }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
158 { GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
159 { GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
160 { SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
161 { GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
162 { SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
163 { GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
164 { GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
165 { GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
166 { GPIO_BLOCK_BASE, 0x00060006 }, // # GPI .GPIODATA # Release LCDD reset
167 { GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
168 { GPIO_BLOCK_BASE, 0x02000200 }, // # GPI .GPIODATA # TEST LED ON
169 { DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
170 { TIMER0CONTROL, 0x00000060 }, // # PWM.Timer0Control # PWM0 output stop
171 { PWM_BLOCK_BASE, 0x00001388 }, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF)
172 //{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF
173#if 0
174 { PWM0OFF, 0x00001387 }, // SURF 100% backlight
175 { PWM0OFF, 0x00000000 }, // FFA 100% backlight
176#endif
177 { PWM0OFF, 0x000009C3 }, // 50% BL
178 { TIMER1CONTROL, 0x00000060 }, // # PWM.Timer1Control # PWM1 output stop
179 { TIMER1LOAD, 0x00001388 }, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF)
180 //{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF
181 { PWM1OFF, 0x00001387 },
182 { TIMER0CONTROL, 0x000000E0 }, // # PWM.Timer0Control # PWM0 output start
183 { TIMER1CONTROL, 0x000000E0 }, // # PWM.Timer1Control # PWM1 output start
184 { PWMCR, 0x00000003 }, // # PWM.PWMCR # PWM output enable
185 { 0, 1 }, // wait_ms(1);
186 { SPI_BLOCK_BASE, 0x00000799 }, // # SPI .SSICTL # SPI operation mode setting
187 { SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
188 { SPI_BLOCK_BASE, 0x0000079b }, // # SPI .SSICTL # Set SPI active mode
189
190 { SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
191 { 0, 1 }, // wait_ms(1);
192 { SSITX, 0x00000000 }, // # SPI.SSITX
193 { 0, 1 }, // wait_ms(1);
194 { SSITX, 0x00000000 }, // # SPI.SSITX
195 { 0, 1 }, // wait_ms(1);
196 { SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
197 { SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
198 { SSITX, 0x00080036 }, // # Command setting of SPI block
199 { SSITX, 0x00000100 }, // # Memory access control
200 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
201 { SSITX, 0x000800BB }, // # Command setting of SPI block
202 { SSITX, 0x00000100 }, // # Display mode setup(2)
203 { SSITX, 0x0008003A }, // # Command setting of SPI block
204 { SSITX, 0x00000160 }, // # RGB Interface data format
205 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
206 { SSITX, 0x000800BF }, // # Command setting of SPI block
207 { SSITX, 0x00000100 }, // # Drivnig method
208 { SSITX, 0x000800B1 }, // # Command setting of SPI block
209 { SSITX, 0x0000015D }, // # Booster operation setup
210 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
211 { SSITX, 0x000800B2 }, // # Command setting of SPI block
212 { SSITX, 0x00000133 }, // # Booster mode setup
213 { SSITX, 0x000800B3 }, // # Command setting of SPI block
214 { SSITX, 0x00000122 }, // # Booster frequencies setup
215 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
216 { SSITX, 0x000800B4 }, // # Command setting of SPI block
217 { SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
218 { SSITX, 0x000800B5 }, // # Command setting of SPI block
219 { SSITX, 0x0000011F }, // # VCS Voltage adjustment (1C->1F for Rev 2)
220 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
221 { SSITX, 0x000800B6 }, // # Command setting of SPI block
222 { SSITX, 0x00000128 }, // # VCOM Voltage adjustment
223 { SSITX, 0x000800B7 }, // # Command setting of SPI block
224 { SSITX, 0x00000103 }, // # Configure an external display signal
225 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
226 { SSITX, 0x000800B9 }, // # Command setting of SPI block
227 { SSITX, 0x00000120 }, // # DCCK/DCEV timing setup
228 { SSITX, 0x000800BD }, // # Command setting of SPI block
229 { SSITX, 0x00000102 }, // # ASW signal control
230 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
231 { SSITX, 0x000800BE }, // # Command setting of SPI block
232 { SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
233 { SSITX, 0x000800C0 }, // # Command setting of SPI block
234 { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
235 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
236 { SSITX, 0x000800C1 }, // # Command setting of SPI block
237 { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
238 { SSITX, 0x000800C2 }, // # Command setting of SPI block
239 { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
240 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
241 { SSITX, 0x000800C3 }, // # Command setting of SPI block
242 { SSITX, 0x0008010A }, // # wait_ms(-in line clock count setup (D)
243 { SSITX, 0x0000010A }, //
244 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
245 { SSITX, 0x000800C4 }, // # Command setting of SPI block
246 { SSITX, 0x00080160 }, // # Seep-in line clock count setup (E)
247 { SSITX, 0x00000160 }, //
248 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
249 { SSITX, 0x000800C5 }, // # Command setting of SPI block
250 { SSITX, 0x00080160 }, // # wait_ms(-in line clock count setup (F)
251 { SSITX, 0x00000160 }, //
252 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
253 { SSITX, 0x000800C6 }, // # Command setting of SPI block
254 { SSITX, 0x00080160 }, // # wait_ms(-in line clock setup (G)
255 { SSITX, 0x00000160 }, //
256 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
257 { SSITX, 0x000800C7 }, // # Command setting of SPI block
258 { SSITX, 0x00080133 }, // # Gamma 1 fine tuning (1)
259 { SSITX, 0x00000143 }, //
260 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
261 { SSITX, 0x000800C8 }, // # Command setting of SPI block
262 { SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
263 { SSITX, 0x000800C9 }, // # Command setting of SPI block
264 { SSITX, 0x00000133 }, // # Gamma 1 inclination adjustment
265 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
266 { SSITX, 0x000800CA }, // # Command setting of SPI block
267 { SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
268 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
269 { SSITX, 0x000800EC }, // # Command setting of SPI block
270 { SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
271 { SSITX, 0x00000118 }, //
272 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
273 { SSITX, 0x000800CF }, // # Command setting of SPI block
274 { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
275 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
276 { SSITX, 0x000800D0 }, // # Command setting of SPI block
277 { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
278 { SSITX, 0x00000104 }, //
279 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
280 { SSITX, 0x000800D1 }, // # Command setting of SPI block
281 { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
282 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
283 { SSITX, 0x000800D2 }, // # Command setting of SPI block
284 { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
285 { SSITX, 0x0000013A }, //
286 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
287 { SSITX, 0x000800D3 }, // # Command setting of SPI block
288 { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
289 { SSITX, 0x0000013A }, //
290 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
291 { SSITX, 0x000800D4 }, // # Command setting of SPI block
292 { SSITX, 0x00080124 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
293 { SSITX, 0x0000016E }, //
294 { 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
295 { SSITX, 0x000800D5 }, // # Command setting of SPI block
296 { SSITX, 0x00000124 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
297 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
298 { SSITX, 0x000800ED }, // # Command setting of SPI block
299 { SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
300 { SSITX, 0x0000010A }, //
301 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
302 { SSITX, 0x000800D6 }, // # Command setting of SPI block
303 { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA]
304 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
305 { SSITX, 0x000800D7 }, // # Command setting of SPI block
306 { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA]
307 { SSITX, 0x0000010A }, //
308 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
309 { SSITX, 0x000800D8 }, // # Command setting of SPI block
310 { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA]
311 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
312 { SSITX, 0x000800D9 }, // # Command setting of SPI block
313 { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA]
314 { SSITX, 0x00000114 }, //
315 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
316 { SSITX, 0x000800DE }, // # Command setting of SPI block
317 { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table2 for QVGA]
318 { SSITX, 0x00000114 }, //
319 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
320 { SSITX, 0x000800DF }, // # Command setting of SPI block
321 { SSITX, 0x00080112 }, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA]
322 { SSITX, 0x0000013F }, //
323 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
324 { SSITX, 0x000800E0 }, // # Command setting of SPI block
325 { SSITX, 0x0000010B }, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA]
326 { SSITX, 0x000800E2 }, // # Command setting of SPI block
327 { SSITX, 0x00000101 }, // # Built-in oscillator frequency division setup [Frequency division ratio : 2 (60Hq)
328 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
329 { SSITX, 0x000800E3 }, // # Command setting of SPI block
330 { SSITX, 0x00000136 }, // # Built-in oscillator clock count setup
331 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
332 { SSITX, 0x000800E4 }, // # Command setting of SPI block
333 { SSITX, 0x00080100 }, // # CKV timing control for using build-in osc
334 { SSITX, 0x00000103 }, //
335 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
336 { SSITX, 0x000800E5 }, // # Command setting of SPI block
337 { SSITX, 0x00080102 }, // # OEV timing control for using build-in osc
338 { SSITX, 0x00000104 }, //
339 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
340 { SSITX, 0x000800E6 }, // # Command setting of SPI block
341 { SSITX, 0x00000103 }, // # DCEV timing control for using build-in osc
342 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
343 { SSITX, 0x000800E7 }, // # Command setting of SPI block
344 { SSITX, 0x00080104 }, // # ASW timing setup for using build-in osc(1)
345 { SSITX, 0x0000010A }, //
346 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
347 { SSITX, 0x000800E8 }, // # Command setting of SPI block
348 { SSITX, 0x00000104 }, // # ASW timing setup for using build-in osc(2)
349
350
351 { CLKENB, 0x000001EF }, // # SYS.CLKENB # DCLK enable
352 { START, 0x00000000 }, // # LCD.START # LCDC wait_ms( mode
353 { WRSTB, 0x0000003F }, // # LCD.WRSTB # write_client_reg( strobe
354 { RDSTB, 0x00000432 }, // # LCD.RDSTB # Read strobe
355 { PORT_ENB, 0x00000002 }, // # LCD.PORT_ENB # Asynchronous port enable
356 { VSYNIF, 0x00000000 }, // # LCD.VSYNCIF # VSYNC I/F mode set
357 { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
358 { ASY_DATB, 0x00000001 }, // # Oscillator start
359 { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
360 { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
361 { 0, 10 }, // wait_ms(10);
362 { ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # DUMMY write_client_reg(@*NOTE2
363 { ASY_DATB, 0x80000000 }, //
364 { ASY_DATC, 0x80000000 }, //
365 { ASY_DATD, 0x80000000 }, //
366 { ASY_CMDSET, 0x00000009 }, // # LCD.ASY_CMDSET
367 { ASY_CMDSET, 0x00000008 }, // # LCD.ASY_CMDSET
368 { ASY_DATA, 0x80000007 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
369 { ASY_DATB, 0x00004005 }, // # LCD driver control
370 { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
371 { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
372 { 0, 20 }, // wait_ms(20);
373 { ASY_DATA, 0x80000059 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
374 { ASY_DATB, 0x00000000 }, // # LTPS I/F control
375 { ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
376 { ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
377
378 { VSYNIF, 0x00000001 }, // # LCD.VSYNCIF # VSYNC I/F mode OFF
379 { PORT_ENB, 0x00000001 }, // # LCD.PORT_ENB # SYNC I/F output select
380
381 /******************************/
382
383 { VSYNIF, 0x00000001 }, // VSYNC I/F mode OFF
384 { PORT_ENB, 0x00000001 }, // SYNC I/F mode ON
385
386 { BITMAP1, 0x01E000F0 }, // MDC.BITMAP2 ); // Setup of PITCH size to Frame buffer1
387 { BITMAP2, 0x01E000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
388 { BITMAP3, 0x01E000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
389 { BITMAP4, 0x00DC00B0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
390 { CLKENB, 0x000001EF }, // SYS.CLKENB ); // DCLK supply
391 { PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
392 { PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
393 { PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
394 { MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
395 { HCYCLE, 0x0000010b }, // LCD.HCYCLE ); // Setup to VGA size
396 { HSW, 0x00000003 }, // LCD.HSW
397 { HDE_START, 0x00000007 }, // LCD.HDE_START
398 { HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
399 { VCYCLE, 0x00000285 }, // LCD.VCYCLE
400 { VSW, 0x00000001 }, // LCD.VSW
401 { VDE_START, 0x00000003 }, // LCD.VDE_START
402 { VDE_SIZE, 0x0000027F }, // LCD.VDE_SIZE
403
404 { START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
405
406 { 0, 10 }, // wait_ms( 10 );
407 { SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
408 { SSITX, 0x00000180 }, // Display data setup
409 { SSITX, 0x0008003B }, // Command setting of SPI block
410 { SSITX, 0x00000100 }, // Quad Data configuration - VGA
411 { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
412 { SSITX, 0x000800B0 }, // Command setting of SPI block
413 { SSITX, 0x00000116 }, // Power supply ON/OFF control
414 { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
415 { SSITX, 0x000800B8 }, // Command setting of SPI block
416 { SSITX, 0x000801FF }, // Output control
417 { SSITX, 0x000001F5 },
418 { 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
419 { SSITX, 0x00000011 }, // wait_ms(-out (Command only)
420 { SSITX, 0x00000029 }, // Display on (Command only)
421
422 { SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
423
424 { 0, 0 }
425};
426
427static void _panel_init(struct init_table *init_table)
428{
429 unsigned n;
430
431 dprintf(INFO, "panel_init()\n");
432
433 n = 0;
434 while (init_table[n].reg != 0 || init_table[n].val != 0) {
435 if (init_table[n].reg != 0)
436 mddi_remote_write(init_table[n].val, init_table[n].reg);
437 else
Chandan Uddaraju61e6d7c2010-07-20 17:57:06 -0700438 mdelay(init_table[n].val);
Ajay Dudania66de4f2009-11-22 08:57:39 -0800439 n++;
440 }
441
442 dprintf(INFO, "panel_init() done\n");
443}
444
445void panel_init(struct mddi_client_caps *client_caps)
446{
447 switch(client_caps->manufacturer_name) {
448 case 0xd263: // Toshiba
449 dprintf(INFO, "Found Toshiba panel\n");
450 _panel_init(toshiba_480x640_init_table);
451 break;
452 case 0x4474: //??
453 if (client_caps->product_code == 0xc065)
454 dprintf(INFO, "Found WVGA panel\n");
455 break;
456 }
457}
458
459void panel_poweron(void)
460{
461 gpio_set(88, 0);
462 gpio_config(88, GPIO_OUTPUT);
Chandan Uddaraju61e6d7c2010-07-20 17:57:06 -0700463 udelay(10);
Ajay Dudania66de4f2009-11-22 08:57:39 -0800464 gpio_set(88, 1);
Chandan Uddaraju61e6d7c2010-07-20 17:57:06 -0700465 mdelay(10);
Ajay Dudania66de4f2009-11-22 08:57:39 -0800466
467 //mdelay(1000); // uncomment for second stage boot
468}
469
470void panel_backlight(int on)
471{}