blob: df0804674fccb61d74d7b3769cd27319424f993e [file] [log] [blame]
Deepa Dinamani7dc3d4b2013-02-08 16:40:38 -08001/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MSM8610_CLOCK_H
30#define __MSM8610_CLOCK_H
31
32#include <clock.h>
33#include <clock_lib2.h>
34
Terence Hampson711a9c22013-06-18 14:35:43 -040035#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
36
37#define VSYNC_CMD_RCGR REG_MM(0x2080)
38#define VSYNC_CFG_RCGR REG_MM(0x2084)
39#define AXI_CMD_RCGR REG_MM(0x5040)
40#define AXI_CFG_RCGR REG_MM(0x5044)
41
42#define MDP_AXI_CBCR REG_MM(0x2314)
43#define MDP_AHB_CBCR REG_MM(0x2318)
44#define MDP_VSYNC_CBCR REG_MM(0x231C)
45#define MDP_DSI_CBCR REG_MM(0x2320)
46#define MDP_LCDC_CBCR REG_MM(0x2340)
47
48#define MMSS_S0_AXI_CBCR REG_MM(0x5064)
49#define MMSS_MMSSNOC_AXI_CBCR REG_MM(0x506C)
50
51#define DSI_CBCR REG_MM(0x2324)
52#define DSI_BYTE_CBCR REG_MM(0x2328)
53#define DSI_ESC_CBCR REG_MM(0x232C)
54#define DSI_AHB_CBCR REG_MM(0x2330)
55#define DSI_PCLK_CBCR REG_MM(0x233C)
56
57#define DSI_CMD_RCGR REG_MM(0x2020)
58#define DSI_CFG_RCGR REG_MM(0x2024)
59#define DSI_PCLK_CMD_RCGR REG_MM(0x2000)
60#define DSI_PCLK_CFG_RCGR REG_MM(0x2004)
61#define DSI_BYTE_CMD_RCGR REG_MM(0x2120)
62#define DSI_BYTE_CFG_RCGR REG_MM(0x2124)
63
Deepa Dinamani7dc3d4b2013-02-08 16:40:38 -080064#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
65
Terence Hampson711a9c22013-06-18 14:35:43 -040066#define VCO_MAX_DIVIDER 256
67#define VCO_MIN_RATE 600000000
68#define VCO_MAX_RATE 1200000000
69#define VCO_PREF_DIV_RATIO 26
70#define VCO_PARENT_RATE 19200000
71
Deepa Dinamani7dc3d4b2013-02-08 16:40:38 -080072void platform_clock_init(void);
73
74void clock_init_mmc(uint32_t interface);
75void clock_config_mmc(uint32_t interface, uint32_t freq);
76void clock_config_uart_dm(uint8_t id);
77void hsusb_clock_init(void);
Terence Hampson711a9c22013-06-18 14:35:43 -040078void mdp_clock_enable(void);
79void mdp_clock_disable(void);
80void dsi_clock_enable(uint32_t dsiclk_rate, uint32_t byteclk_rate);
81void dsi_clock_disable(void);
Amol Jadif2139012013-08-23 18:44:10 -070082void clock_ce_enable(uint8_t instance);
83void clock_ce_disable(uint8_t instance);
Deepa Dinamani7dc3d4b2013-02-08 16:40:38 -080084
85#endif