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gerrit-public.fairphone.software / kernel / lk / refs/tags/FP3-REL-Q.3.A.0134 / . / platform / mdm9607 / include / platform / iomap.h
blob: 00c98a5a191e7c1a6b312624561a527533682aeb [file] [log] [blame]
vijay kumarca1672a2015-04-09 16:45:40 +0530[diff] [blame]1/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
vijay kumardb062a32015-10-30 12:32:15 +0530[diff] [blame]29#ifndef _PLATFORM_MDM9607_IOMAP_H_
30#define _PLATFORM_MDM9607_IOMAP_H_
vijay kumarca1672a2015-04-09 16:45:40 +0530[diff] [blame]31
32#define MSM_IOMAP_BASE 0x00000000
33#define MSM_IOMAP_END 0x08000000
34
35#define A7_SS_BASE 0x0B000000
36#define A7_SS_END 0x0B200000
37
38#define SDRAM_START_ADDR 0x80000000
39
40#define SYSTEM_IMEM_BASE 0x08600000
41#define MSM_SHARED_BASE 0x87D00000
42#define MSM_SHARED_IMEM_BASE 0x08600000
43
44#define BS_INFO_OFFSET (0x6B0)
45#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
46
47#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
48
49#define MSM_NAND_BASE 0x79B0000
50/* NAND BAM */
51#define MSM_NAND_BAM_BASE 0x7984000
52
53#define APPS_SS_BASE 0x0B000000
54
55#define MSM_GIC_DIST_BASE APPS_SS_BASE
56#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
57#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
58#define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000)
59#define APCS_ALIAS0_IPC_INTERRUPT (APPS_SS_BASE + 0x00011008)
60#define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE
61
62#define PERIPH_SS_BASE 0x07800000
63
64
65#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000)
66#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000)
vijay kumar97f00272015-09-29 12:16:30 +0530[diff] [blame]67#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x000B3000)
vijay kumarca1672a2015-04-09 16:45:40 +0530[diff] [blame]68#define MSM_USB_BASE (PERIPH_SS_BASE + 0x000D9000)
69
70#define CLK_CTL_BASE 0x1800000
71
72#define SPMI_BASE 0x02000000
73#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
74#define SPMI_PIC_BASE (SPMI_BASE + 0x01800000)
75#define PMIC_ARB_CORE 0x200F000
76
77#define TLMM_BASE_ADDR 0x1000000
78#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
79#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x00000004 + (x)*0x1000)
80
81#define MPM2_MPM_CTRL_BASE 0x004A0000
82#define MPM2_MPM_PS_HOLD 0x004AB000
83#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000
84
85/* CRYPTO ENGINE */
86#define MSM_CE1_BASE 0x073A000
87#define MSM_CE1_BAM_BASE 0x0704000
vijay kumar70dbe3e2015-11-20 13:07:30 +0530[diff] [blame]88#define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000)
89#define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004)
90#define GCC_CRYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008)
91#define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C)
92#define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020)
93#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
vijay kumarca1672a2015-04-09 16:45:40 +0530[diff] [blame]94
95
96/* GPLL */
vijay kumar20627da2015-10-01 13:28:58 +0530[diff] [blame]97#define GPLL0_MODE (CLK_CTL_BASE + 0x21000)
vijay kumarca1672a2015-04-09 16:45:40 +0530[diff] [blame]98#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
99#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
100
101/* UART */
102#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
vijay kumar20627da2015-10-01 13:28:58 +0530[diff] [blame]103#define BLSP1_UART5_APPS_CBCR (CLK_CTL_BASE + 0x603c)
104#define BLSP1_UART5_APPS_CMD_RCGR (CLK_CTL_BASE + 0x6044)
105#define BLSP1_UART5_APPS_CFG_RCGR (CLK_CTL_BASE + 0x6048)
106#define BLSP1_UART5_APPS_M (CLK_CTL_BASE + 0x604C)
107#define BLSP1_UART5_APPS_N (CLK_CTL_BASE + 0x6050)
108#define BLSP1_UART5_APPS_D (CLK_CTL_BASE + 0x6054)
vijay kumarca1672a2015-04-09 16:45:40 +0530[diff] [blame]109
110/* USB */
111#define USB_HS_BCR (CLK_CTL_BASE + 0x41000)
112#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x41004)
113#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008)
114#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
115#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
116
117#define TCSR_TZ_WONCE 0x193D000
118#define TCSR_BOOT_MISC_DETECT 0x193D100
119#endif