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gerrit-public.fairphone.software / kernel / lk / refs/tags/FP3-REL-Q.3.A.0134 / . / platform / msm_shared / mdss_hdmi_pll_8996.c
blob: ef0a6d9ee34caec66867e3d95eebc980594ddf08 [file] [log] [blame]
Tatenda Chipeperekwa357f2dd2015-11-10 14:05:32 -0800[diff] [blame]1/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions
5 * are met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in
10 * the documentation and/or other materials provided with the
11 * distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
19 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
20 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
23 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <debug.h>
31#include <err.h>
32#include <reg.h>
33#include <smem.h>
34#include <bits.h>
35#include <msm_panel.h>
36#include <platform/timer.h>
37#include <platform/iomap.h>
38
39/* PLL REGISTERS */
40#define HDMI_PLL_BASE_OFFSET (0x9A0600)
41#define QSERDES_COM_ATB_SEL1 (HDMI_PLL_BASE_OFFSET + 0x000)
42#define QSERDES_COM_ATB_SEL2 (HDMI_PLL_BASE_OFFSET + 0x004)
43#define QSERDES_COM_FREQ_UPDATE (HDMI_PLL_BASE_OFFSET + 0x008)
44#define QSERDES_COM_BG_TIMER (HDMI_PLL_BASE_OFFSET + 0x00C)
45#define QSERDES_COM_SSC_EN_CENTER (HDMI_PLL_BASE_OFFSET + 0x010)
46#define QSERDES_COM_SSC_ADJ_PER1 (HDMI_PLL_BASE_OFFSET + 0x014)
47#define QSERDES_COM_SSC_ADJ_PER2 (HDMI_PLL_BASE_OFFSET + 0x018)
48#define QSERDES_COM_SSC_PER1 (HDMI_PLL_BASE_OFFSET + 0x01C)
49#define QSERDES_COM_SSC_PER2 (HDMI_PLL_BASE_OFFSET + 0x020)
50#define QSERDES_COM_SSC_STEP_SIZE1 (HDMI_PLL_BASE_OFFSET + 0x024)
51#define QSERDES_COM_SSC_STEP_SIZE2 (HDMI_PLL_BASE_OFFSET + 0x028)
52#define QSERDES_COM_POST_DIV (HDMI_PLL_BASE_OFFSET + 0x02C)
53#define QSERDES_COM_POST_DIV_MUX (HDMI_PLL_BASE_OFFSET + 0x030)
54#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN (HDMI_PLL_BASE_OFFSET + 0x034)
55#define QSERDES_COM_CLK_ENABLE1 (HDMI_PLL_BASE_OFFSET + 0x038)
56#define QSERDES_COM_SYS_CLK_CTRL (HDMI_PLL_BASE_OFFSET + 0x03C)
57#define QSERDES_COM_SYSCLK_BUF_ENABLE (HDMI_PLL_BASE_OFFSET + 0x040)
58#define QSERDES_COM_PLL_EN (HDMI_PLL_BASE_OFFSET + 0x044)
59#define QSERDES_COM_PLL_IVCO (HDMI_PLL_BASE_OFFSET + 0x048)
60#define QSERDES_COM_LOCK_CMP1_MODE0 (HDMI_PLL_BASE_OFFSET + 0x04C)
61#define QSERDES_COM_LOCK_CMP2_MODE0 (HDMI_PLL_BASE_OFFSET + 0x050)
62#define QSERDES_COM_LOCK_CMP3_MODE0 (HDMI_PLL_BASE_OFFSET + 0x054)
63#define QSERDES_COM_LOCK_CMP1_MODE1 (HDMI_PLL_BASE_OFFSET + 0x058)
64#define QSERDES_COM_LOCK_CMP2_MODE1 (HDMI_PLL_BASE_OFFSET + 0x05C)
65#define QSERDES_COM_LOCK_CMP3_MODE1 (HDMI_PLL_BASE_OFFSET + 0x060)
66#define QSERDES_COM_LOCK_CMP1_MODE2 (HDMI_PLL_BASE_OFFSET + 0x064)
67#define QSERDES_COM_CMN_RSVD0 (HDMI_PLL_BASE_OFFSET + 0x064)
68#define QSERDES_COM_LOCK_CMP2_MODE2 (HDMI_PLL_BASE_OFFSET + 0x068)
69#define QSERDES_COM_EP_CLOCK_DETECT_CTRL (HDMI_PLL_BASE_OFFSET + 0x068)
70#define QSERDES_COM_LOCK_CMP3_MODE2 (HDMI_PLL_BASE_OFFSET + 0x06C)
71#define QSERDES_COM_SYSCLK_DET_COMP_STATUS (HDMI_PLL_BASE_OFFSET + 0x06C)
72#define QSERDES_COM_BG_TRIM (HDMI_PLL_BASE_OFFSET + 0x070)
73#define QSERDES_COM_CLK_EP_DIV (HDMI_PLL_BASE_OFFSET + 0x074)
74#define QSERDES_COM_CP_CTRL_MODE0 (HDMI_PLL_BASE_OFFSET + 0x078)
75#define QSERDES_COM_CP_CTRL_MODE1 (HDMI_PLL_BASE_OFFSET + 0x07C)
76#define QSERDES_COM_CP_CTRL_MODE2 (HDMI_PLL_BASE_OFFSET + 0x080)
77#define QSERDES_COM_CMN_RSVD1 (HDMI_PLL_BASE_OFFSET + 0x080)
78#define QSERDES_COM_PLL_RCTRL_MODE0 (HDMI_PLL_BASE_OFFSET + 0x084)
79#define QSERDES_COM_PLL_RCTRL_MODE1 (HDMI_PLL_BASE_OFFSET + 0x088)
80#define QSERDES_COM_PLL_RCTRL_MODE2 (HDMI_PLL_BASE_OFFSET + 0x08C)
81#define QSERDES_COM_CMN_RSVD2 (HDMI_PLL_BASE_OFFSET + 0x08C)
82#define QSERDES_COM_PLL_CCTRL_MODE0 (HDMI_PLL_BASE_OFFSET + 0x090)
83#define QSERDES_COM_PLL_CCTRL_MODE1 (HDMI_PLL_BASE_OFFSET + 0x094)
84#define QSERDES_COM_PLL_CCTRL_MODE2 (HDMI_PLL_BASE_OFFSET + 0x098)
85#define QSERDES_COM_CMN_RSVD3 (HDMI_PLL_BASE_OFFSET + 0x098)
86#define QSERDES_COM_PLL_CNTRL (HDMI_PLL_BASE_OFFSET + 0x09C)
87#define QSERDES_COM_PHASE_SEL_CTRL (HDMI_PLL_BASE_OFFSET + 0x0A0)
88#define QSERDES_COM_PHASE_SEL_DC (HDMI_PLL_BASE_OFFSET + 0x0A4)
89#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL (HDMI_PLL_BASE_OFFSET + 0x0A8)
90#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM (HDMI_PLL_BASE_OFFSET + 0x0A8)
91#define QSERDES_COM_SYSCLK_EN_SEL (HDMI_PLL_BASE_OFFSET + 0x0AC)
92#define QSERDES_COM_CML_SYSCLK_SEL (HDMI_PLL_BASE_OFFSET + 0x0B0)
93#define QSERDES_COM_RESETSM_CNTRL (HDMI_PLL_BASE_OFFSET + 0x0B4)
94#define QSERDES_COM_RESETSM_CNTRL2 (HDMI_PLL_BASE_OFFSET + 0x0B8)
95#define QSERDES_COM_RESTRIM_CTRL (HDMI_PLL_BASE_OFFSET + 0x0BC)
96#define QSERDES_COM_RESTRIM_CTRL2 (HDMI_PLL_BASE_OFFSET + 0x0C0)
97#define QSERDES_COM_RESCODE_DIV_NUM (HDMI_PLL_BASE_OFFSET + 0x0C4)
98#define QSERDES_COM_LOCK_CMP_EN (HDMI_PLL_BASE_OFFSET + 0x0C8)
99#define QSERDES_COM_LOCK_CMP_CFG (HDMI_PLL_BASE_OFFSET + 0x0CC)
100#define QSERDES_COM_DEC_START_MODE0 (HDMI_PLL_BASE_OFFSET + 0x0D0)
101#define QSERDES_COM_DEC_START_MODE1 (HDMI_PLL_BASE_OFFSET + 0x0D4)
102#define QSERDES_COM_DEC_START_MODE2 (HDMI_PLL_BASE_OFFSET + 0x0D8)
103#define QSERDES_COM_VCOCAL_DEADMAN_CTRL (HDMI_PLL_BASE_OFFSET + 0x0D8)
104#define QSERDES_COM_DIV_FRAC_START1_MODE0 (HDMI_PLL_BASE_OFFSET + 0x0DC)
105#define QSERDES_COM_DIV_FRAC_START2_MODE0 (HDMI_PLL_BASE_OFFSET + 0x0E0)
106#define QSERDES_COM_DIV_FRAC_START3_MODE0 (HDMI_PLL_BASE_OFFSET + 0x0E4)
107#define QSERDES_COM_DIV_FRAC_START1_MODE1 (HDMI_PLL_BASE_OFFSET + 0x0E8)
108#define QSERDES_COM_DIV_FRAC_START2_MODE1 (HDMI_PLL_BASE_OFFSET + 0x0EC)
109#define QSERDES_COM_DIV_FRAC_START3_MODE1 (HDMI_PLL_BASE_OFFSET + 0x0F0)
110#define QSERDES_COM_DIV_FRAC_START1_MODE2 (HDMI_PLL_BASE_OFFSET + 0x0F4)
111#define QSERDES_COM_VCO_TUNE_MINVAL1 (HDMI_PLL_BASE_OFFSET + 0x0F4)
112#define QSERDES_COM_DIV_FRAC_START2_MODE2 (HDMI_PLL_BASE_OFFSET + 0x0F8)
113#define QSERDES_COM_VCO_TUNE_MINVAL2 (HDMI_PLL_BASE_OFFSET + 0x0F8)
114#define QSERDES_COM_DIV_FRAC_START3_MODE2 (HDMI_PLL_BASE_OFFSET + 0x0FC)
115#define QSERDES_COM_CMN_RSVD4 (HDMI_PLL_BASE_OFFSET + 0x0FC)
116#define QSERDES_COM_INTEGLOOP_INITVAL (HDMI_PLL_BASE_OFFSET + 0x100)
117#define QSERDES_COM_INTEGLOOP_EN (HDMI_PLL_BASE_OFFSET + 0x104)
118#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 (HDMI_PLL_BASE_OFFSET + 0x108)
119#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 (HDMI_PLL_BASE_OFFSET + 0x10C)
120#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 (HDMI_PLL_BASE_OFFSET + 0x110)
121#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 (HDMI_PLL_BASE_OFFSET + 0x114)
122#define QSERDES_COM_INTEGLOOP_GAIN0_MODE2 (HDMI_PLL_BASE_OFFSET + 0x118)
123#define QSERDES_COM_VCO_TUNE_MAXVAL1 (HDMI_PLL_BASE_OFFSET + 0x118)
124#define QSERDES_COM_INTEGLOOP_GAIN1_MODE2 (HDMI_PLL_BASE_OFFSET + 0x11C)
125#define QSERDES_COM_VCO_TUNE_MAXVAL2 (HDMI_PLL_BASE_OFFSET + 0x11C)
126#define QSERDES_COM_RES_TRIM_CONTROL2 (HDMI_PLL_BASE_OFFSET + 0x120)
127#define QSERDES_COM_VCO_TUNE_CTRL (HDMI_PLL_BASE_OFFSET + 0x124)
128#define QSERDES_COM_VCO_TUNE_MAP (HDMI_PLL_BASE_OFFSET + 0x128)
129#define QSERDES_COM_VCO_TUNE1_MODE0 (HDMI_PLL_BASE_OFFSET + 0x12C)
130#define QSERDES_COM_VCO_TUNE2_MODE0 (HDMI_PLL_BASE_OFFSET + 0x130)
131#define QSERDES_COM_VCO_TUNE1_MODE1 (HDMI_PLL_BASE_OFFSET + 0x134)
132#define QSERDES_COM_VCO_TUNE2_MODE1 (HDMI_PLL_BASE_OFFSET + 0x138)
133#define QSERDES_COM_VCO_TUNE1_MODE2 (HDMI_PLL_BASE_OFFSET + 0x13C)
134#define QSERDES_COM_VCO_TUNE_INITVAL1 (HDMI_PLL_BASE_OFFSET + 0x13C)
135#define QSERDES_COM_VCO_TUNE2_MODE2 (HDMI_PLL_BASE_OFFSET + 0x140)
136#define QSERDES_COM_VCO_TUNE_INITVAL2 (HDMI_PLL_BASE_OFFSET + 0x140)
137#define QSERDES_COM_VCO_TUNE_TIMER1 (HDMI_PLL_BASE_OFFSET + 0x144)
138#define QSERDES_COM_VCO_TUNE_TIMER2 (HDMI_PLL_BASE_OFFSET + 0x148)
139#define QSERDES_COM_SAR (HDMI_PLL_BASE_OFFSET + 0x14C)
140#define QSERDES_COM_SAR_CLK (HDMI_PLL_BASE_OFFSET + 0x150)
141#define QSERDES_COM_SAR_CODE_OUT_STATUS (HDMI_PLL_BASE_OFFSET + 0x154)
142#define QSERDES_COM_SAR_CODE_READY_STATUS (HDMI_PLL_BASE_OFFSET + 0x158)
143#define QSERDES_COM_CMN_STATUS (HDMI_PLL_BASE_OFFSET + 0x15C)
144#define QSERDES_COM_RESET_SM_STATUS (HDMI_PLL_BASE_OFFSET + 0x160)
145#define QSERDES_COM_RESTRIM_CODE_STATUS (HDMI_PLL_BASE_OFFSET + 0x164)
146#define QSERDES_COM_PLLCAL_CODE1_STATUS (HDMI_PLL_BASE_OFFSET + 0x168)
147#define QSERDES_COM_PLLCAL_CODE2_STATUS (HDMI_PLL_BASE_OFFSET + 0x16C)
148#define QSERDES_COM_BG_CTRL (HDMI_PLL_BASE_OFFSET + 0x170)
149#define QSERDES_COM_CLK_SELECT (HDMI_PLL_BASE_OFFSET + 0x174)
150#define QSERDES_COM_HSCLK_SEL (HDMI_PLL_BASE_OFFSET + 0x178)
151#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS (HDMI_PLL_BASE_OFFSET + 0x17C)
152#define QSERDES_COM_PLL_ANALOG (HDMI_PLL_BASE_OFFSET + 0x180)
153#define QSERDES_COM_CORECLK_DIV (HDMI_PLL_BASE_OFFSET + 0x184)
154#define QSERDES_COM_SW_RESET (HDMI_PLL_BASE_OFFSET + 0x188)
155#define QSERDES_COM_CORE_CLK_EN (HDMI_PLL_BASE_OFFSET + 0x18C)
156#define QSERDES_COM_C_READY_STATUS (HDMI_PLL_BASE_OFFSET + 0x190)
157#define QSERDES_COM_CMN_CONFIG (HDMI_PLL_BASE_OFFSET + 0x194)
158#define QSERDES_COM_CMN_RATE_OVERRIDE (HDMI_PLL_BASE_OFFSET + 0x198)
159#define QSERDES_COM_SVS_MODE_CLK_SEL (HDMI_PLL_BASE_OFFSET + 0x19C)
160#define QSERDES_COM_DEBUG_BUS0 (HDMI_PLL_BASE_OFFSET + 0x1A0)
161#define QSERDES_COM_DEBUG_BUS1 (HDMI_PLL_BASE_OFFSET + 0x1A4)
162#define QSERDES_COM_DEBUG_BUS2 (HDMI_PLL_BASE_OFFSET + 0x1A8)
163#define QSERDES_COM_DEBUG_BUS3 (HDMI_PLL_BASE_OFFSET + 0x1AC)
164#define QSERDES_COM_DEBUG_BUS_SEL (HDMI_PLL_BASE_OFFSET + 0x1B0)
165#define QSERDES_COM_CMN_MISC1 (HDMI_PLL_BASE_OFFSET + 0x1B4)
166#define QSERDES_COM_CMN_MISC2 (HDMI_PLL_BASE_OFFSET + 0x1B8)
167#define QSERDES_COM_CORECLK_DIV_MODE1 (HDMI_PLL_BASE_OFFSET + 0x1BC)
168#define QSERDES_COM_CORECLK_DIV_MODE2 (HDMI_PLL_BASE_OFFSET + 0x1C0)
169#define QSERDES_COM_CMN_RSVD5 (HDMI_PLL_BASE_OFFSET + 0x1C0)
170
171/* Tx Channel base addresses */
172#define HDMI_TX_L0_BASE_OFFSET (HDMI_PLL_BASE_OFFSET + 0x400)
173#define HDMI_TX_L1_BASE_OFFSET (HDMI_PLL_BASE_OFFSET + 0x600)
174#define HDMI_TX_L2_BASE_OFFSET (HDMI_PLL_BASE_OFFSET + 0x800)
175#define HDMI_TX_L3_BASE_OFFSET (HDMI_PLL_BASE_OFFSET + 0xA00)
176
177/* Tx Channel PHY registers */
178#define QSERDES_TX_L0_BIST_MODE_LANENO (0x000)
179#define QSERDES_TX_L0_BIST_INVERT (0x004)
180#define QSERDES_TX_L0_CLKBUF_ENABLE (0x008)
181#define QSERDES_TX_L0_CMN_CONTROL_ONE (0x00C)
182#define QSERDES_TX_L0_CMN_CONTROL_TWO (0x010)
183#define QSERDES_TX_L0_CMN_CONTROL_THREE (0x014)
184#define QSERDES_TX_L0_TX_EMP_POST1_LVL (0x018)
185#define QSERDES_TX_L0_TX_POST2_EMPH (0x01C)
186#define QSERDES_TX_L0_TX_BOOST_LVL_UP_DN (0x020)
187#define QSERDES_TX_L0_HP_PD_ENABLES (0x024)
188#define QSERDES_TX_L0_TX_IDLE_LVL_LARGE_AMP (0x028)
189#define QSERDES_TX_L0_TX_DRV_LVL (0x02C)
190#define QSERDES_TX_L0_TX_DRV_LVL_OFFSET (0x030)
191#define QSERDES_TX_L0_RESET_TSYNC_EN (0x034)
192#define QSERDES_TX_L0_PRE_STALL_LDO_BOOST_EN (0x038)
193#define QSERDES_TX_L0_TX_BAND (0x03C)
194#define QSERDES_TX_L0_SLEW_CNTL (0x040)
195#define QSERDES_TX_L0_INTERFACE_SELECT (0x044)
196#define QSERDES_TX_L0_LPB_EN (0x048)
197#define QSERDES_TX_L0_RES_CODE_LANE_TX (0x04C)
198#define QSERDES_TX_L0_RES_CODE_LANE_RX (0x050)
199#define QSERDES_TX_L0_RES_CODE_LANE_OFFSET (0x054)
200#define QSERDES_TX_L0_PERL_LENGTH1 (0x058)
201#define QSERDES_TX_L0_PERL_LENGTH2 (0x05C)
202#define QSERDES_TX_L0_SERDES_BYP_EN_OUT (0x060)
203#define QSERDES_TX_L0_DEBUG_BUS_SEL (0x064)
204#define QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN (0x068)
205#define QSERDES_TX_L0_TX_POL_INV (0x06C)
206#define QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN (0x070)
207#define QSERDES_TX_L0_BIST_PATTERN1 (0x074)
208#define QSERDES_TX_L0_BIST_PATTERN2 (0x078)
209#define QSERDES_TX_L0_BIST_PATTERN3 (0x07C)
210#define QSERDES_TX_L0_BIST_PATTERN4 (0x080)
211#define QSERDES_TX_L0_BIST_PATTERN5 (0x084)
212#define QSERDES_TX_L0_BIST_PATTERN6 (0x088)
213#define QSERDES_TX_L0_BIST_PATTERN7 (0x08C)
214#define QSERDES_TX_L0_BIST_PATTERN8 (0x090)
215#define QSERDES_TX_L0_LANE_MODE (0x094)
216#define QSERDES_TX_L0_IDAC_CAL_LANE_MODE (0x098)
217#define QSERDES_TX_L0_IDAC_CAL_LANE_MODE_CONFIGURATION (0x09C)
218#define QSERDES_TX_L0_ATB_SEL1 (0x0A0)
219#define QSERDES_TX_L0_ATB_SEL2 (0x0A4)
220#define QSERDES_TX_L0_RCV_DETECT_LVL (0x0A8)
221#define QSERDES_TX_L0_RCV_DETECT_LVL_2 (0x0AC)
222#define QSERDES_TX_L0_PRBS_SEED1 (0x0B0)
223#define QSERDES_TX_L0_PRBS_SEED2 (0x0B4)
224#define QSERDES_TX_L0_PRBS_SEED3 (0x0B8)
225#define QSERDES_TX_L0_PRBS_SEED4 (0x0BC)
226#define QSERDES_TX_L0_RESET_GEN (0x0C0)
227#define QSERDES_TX_L0_RESET_GEN_MUXES (0x0C4)
228#define QSERDES_TX_L0_TRAN_DRVR_EMP_EN (0x0C8)
229#define QSERDES_TX_L0_TX_INTERFACE_MODE (0x0CC)
230#define QSERDES_TX_L0_PWM_CTRL (0x0D0)
231#define QSERDES_TX_L0_PWM_ENCODED_OR_DATA (0x0D4)
232#define QSERDES_TX_L0_PWM_GEAR_1_DIVIDER_BAND2 (0x0D8)
233#define QSERDES_TX_L0_PWM_GEAR_2_DIVIDER_BAND2 (0x0DC)
234#define QSERDES_TX_L0_PWM_GEAR_3_DIVIDER_BAND2 (0x0E0)
235#define QSERDES_TX_L0_PWM_GEAR_4_DIVIDER_BAND2 (0x0E4)
236#define QSERDES_TX_L0_PWM_GEAR_1_DIVIDER_BAND0_1 (0x0E8)
237#define QSERDES_TX_L0_PWM_GEAR_2_DIVIDER_BAND0_1 (0x0EC)
238#define QSERDES_TX_L0_PWM_GEAR_3_DIVIDER_BAND0_1 (0x0F0)
239#define QSERDES_TX_L0_PWM_GEAR_4_DIVIDER_BAND0_1 (0x0F4)
240#define QSERDES_TX_L0_VMODE_CTRL1 (0x0F8)
241#define QSERDES_TX_L0_VMODE_CTRL2 (0x0FC)
242#define QSERDES_TX_L0_TX_ALOG_INTF_OBSV_CNTL (0x100)
243#define QSERDES_TX_L0_BIST_STATUS (0x104)
244#define QSERDES_TX_L0_BIST_ERROR_COUNT1 (0x108)
245#define QSERDES_TX_L0_BIST_ERROR_COUNT2 (0x10C)
246#define QSERDES_TX_L0_TX_ALOG_INTF_OBSV (0x110)
247
248/* HDMI PHY REGISTERS */
249#define HDMI_PHY_BASE_OFFSET (0x9A1200)
250#define HDMI_PHY_CFG (HDMI_PHY_BASE_OFFSET + 0x00)
251#define HDMI_PHY_PD_CTL (HDMI_PHY_BASE_OFFSET + 0x04)
252#define HDMI_PHY_MODE (HDMI_PHY_BASE_OFFSET + 0x08)
253#define HDMI_PHY_MISR_CLEAR (HDMI_PHY_BASE_OFFSET + 0x0C)
254#define HDMI_PHY_TX0_TX1_BIST_CFG0 (HDMI_PHY_BASE_OFFSET + 0x10)
255#define HDMI_PHY_TX0_TX1_BIST_CFG1 (HDMI_PHY_BASE_OFFSET + 0x14)
256#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE0 (HDMI_PHY_BASE_OFFSET + 0x18)
257#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE1 (HDMI_PHY_BASE_OFFSET + 0x1C)
258#define HDMI_PHY_TX0_TX1_BIST_PATTERN0 (HDMI_PHY_BASE_OFFSET + 0x20)
259#define HDMI_PHY_TX0_TX1_BIST_PATTERN1 (HDMI_PHY_BASE_OFFSET + 0x24)
260#define HDMI_PHY_TX2_TX3_BIST_CFG0 (HDMI_PHY_BASE_OFFSET + 0x28)
261#define HDMI_PHY_TX2_TX3_BIST_CFG1 (HDMI_PHY_BASE_OFFSET + 0x2C)
262#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE0 (HDMI_PHY_BASE_OFFSET + 0x30)
263#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE1 (HDMI_PHY_BASE_OFFSET + 0x34)
264#define HDMI_PHY_TX2_TX3_BIST_PATTERN0 (HDMI_PHY_BASE_OFFSET + 0x38)
265#define HDMI_PHY_TX2_TX3_BIST_PATTERN1 (HDMI_PHY_BASE_OFFSET + 0x3C)
266#define HDMI_PHY_DEBUG_BUS_SEL (HDMI_PHY_BASE_OFFSET + 0x40)
267#define HDMI_PHY_TXCAL_CFG0 (HDMI_PHY_BASE_OFFSET + 0x44)
268#define HDMI_PHY_TXCAL_CFG1 (HDMI_PHY_BASE_OFFSET + 0x48)
269#define HDMI_PHY_TX0_TX1_LANE_CTL (HDMI_PHY_BASE_OFFSET + 0x4C)
270#define HDMI_PHY_TX2_TX3_LANE_CTL (HDMI_PHY_BASE_OFFSET + 0x50)
271#define HDMI_PHY_LANE_BIST_CONFIG (HDMI_PHY_BASE_OFFSET + 0x54)
272#define HDMI_PHY_CLOCK (HDMI_PHY_BASE_OFFSET + 0x58)
273#define HDMI_PHY_MISC1 (HDMI_PHY_BASE_OFFSET + 0x5C)
274#define HDMI_PHY_MISC2 (HDMI_PHY_BASE_OFFSET + 0x60)
275#define HDMI_PHY_TX0_TX1_BIST_STATUS0 (HDMI_PHY_BASE_OFFSET + 0x64)
276#define HDMI_PHY_TX0_TX1_BIST_STATUS1 (HDMI_PHY_BASE_OFFSET + 0x68)
277#define HDMI_PHY_TX0_TX1_BIST_STATUS2 (HDMI_PHY_BASE_OFFSET + 0x6C)
278#define HDMI_PHY_TX2_TX3_BIST_STATUS0 (HDMI_PHY_BASE_OFFSET + 0x70)
279#define HDMI_PHY_TX2_TX3_BIST_STATUS1 (HDMI_PHY_BASE_OFFSET + 0x74)
280#define HDMI_PHY_TX2_TX3_BIST_STATUS2 (HDMI_PHY_BASE_OFFSET + 0x78)
281#define HDMI_PHY_PRE_MISR_STATUS0 (HDMI_PHY_BASE_OFFSET + 0x7C)
282#define HDMI_PHY_PRE_MISR_STATUS1 (HDMI_PHY_BASE_OFFSET + 0x80)
283#define HDMI_PHY_PRE_MISR_STATUS2 (HDMI_PHY_BASE_OFFSET + 0x84)
284#define HDMI_PHY_PRE_MISR_STATUS3 (HDMI_PHY_BASE_OFFSET + 0x88)
285#define HDMI_PHY_POST_MISR_STATUS0 (HDMI_PHY_BASE_OFFSET + 0x8C)
286#define HDMI_PHY_POST_MISR_STATUS1 (HDMI_PHY_BASE_OFFSET + 0x90)
287#define HDMI_PHY_POST_MISR_STATUS2 (HDMI_PHY_BASE_OFFSET + 0x94)
288#define HDMI_PHY_POST_MISR_STATUS3 (HDMI_PHY_BASE_OFFSET + 0x98)
289#define HDMI_PHY_STATUS (HDMI_PHY_BASE_OFFSET + 0x9C)
290#define HDMI_PHY_MISC3_STATUS (HDMI_PHY_BASE_OFFSET + 0xA0)
291#define HDMI_PHY_MISC4_STATUS (HDMI_PHY_BASE_OFFSET + 0xA4)
292#define HDMI_PHY_DEBUG_BUS0 (HDMI_PHY_BASE_OFFSET + 0xA8)
293#define HDMI_PHY_DEBUG_BUS1 (HDMI_PHY_BASE_OFFSET + 0xAC)
294#define HDMI_PHY_DEBUG_BUS2 (HDMI_PHY_BASE_OFFSET + 0xB0)
295#define HDMI_PHY_DEBUG_BUS3 (HDMI_PHY_BASE_OFFSET + 0xB4)
296#define HDMI_PHY_PHY_REVISION_ID0 (HDMI_PHY_BASE_OFFSET + 0xB8)
297#define HDMI_PHY_PHY_REVISION_ID1 (HDMI_PHY_BASE_OFFSET + 0xBC)
298#define HDMI_PHY_PHY_REVISION_ID2 (HDMI_PHY_BASE_OFFSET + 0xC0)
299#define HDMI_PHY_PHY_REVISION_ID3 (HDMI_PHY_BASE_OFFSET + 0xC4)
300
301#define HDMI_PLL_POLL_MAX_READS 2500
302#define HDMI_PLL_POLL_TIMEOUT_US 150000
303#define HDMI_CLK_RATE_148_MHZ 148500000
304#define HDMI_CLK_RATE_74_MHZ 74250000
305#define HDMI_CLK_RATE_25_MHZ 25200000
Tatenda Chipeperekwabf5c4072016-02-23 18:22:42 -0800[diff] [blame]306#define HDMI_CLK_RATE_297_MHZ 297000000
Tatenda Chipeperekwab99628c2016-03-15 09:54:37 -0700[diff] [blame]307#define HDMI_CLK_RATE_594_MHZ 594000000
Tatenda Chipeperekwa357f2dd2015-11-10 14:05:32 -0800[diff] [blame]308
309#define SW_RESET BIT(2)
310#define SW_RESET_PLL BIT(0)
311
312struct hdmi_8996_phy_pll_reg_cfg {
313 uint32_t tx_l0_lane_mode;
314 uint32_t tx_l2_lane_mode;
315 uint32_t tx_l0_tx_band;
316 uint32_t tx_l1_tx_band;
317 uint32_t tx_l2_tx_band;
318 uint32_t tx_l3_tx_band;
319 uint32_t com_svs_mode_clk_sel;
320 uint32_t com_hsclk_sel;
321 uint32_t com_pll_cctrl_mode0;
322 uint32_t com_pll_rctrl_mode0;
323 uint32_t com_cp_ctrl_mode0;
324 uint32_t com_dec_start_mode0;
325 uint32_t com_div_frac_start1_mode0;
326 uint32_t com_div_frac_start2_mode0;
327 uint32_t com_div_frac_start3_mode0;
328 uint32_t com_integloop_gain0_mode0;
329 uint32_t com_integloop_gain1_mode0;
330 uint32_t com_lock_cmp_en;
331 uint32_t com_lock_cmp1_mode0;
332 uint32_t com_lock_cmp2_mode0;
333 uint32_t com_lock_cmp3_mode0;
334 uint32_t com_core_clk_en;
335 uint32_t com_coreclk_div;
336 uint32_t com_restrim_ctrl;
337 uint32_t com_vco_tune_ctrl;
338 uint32_t tx_l0_tx_drv_lvl;
339 uint32_t tx_l0_tx_emp_post1_lvl;
340 uint32_t tx_l1_tx_drv_lvl;
341 uint32_t tx_l1_tx_emp_post1_lvl;
342 uint32_t tx_l2_tx_drv_lvl;
343 uint32_t tx_l2_tx_emp_post1_lvl;
344 uint32_t tx_l3_tx_drv_lvl;
345 uint32_t tx_l3_tx_emp_post1_lvl;
346 uint32_t tx_l0_vmode_ctrl1;
347 uint32_t tx_l0_vmode_ctrl2;
348 uint32_t tx_l1_vmode_ctrl1;
349 uint32_t tx_l1_vmode_ctrl2;
350 uint32_t tx_l2_vmode_ctrl1;
351 uint32_t tx_l2_vmode_ctrl2;
352 uint32_t tx_l3_vmode_ctrl1;
353 uint32_t tx_l3_vmode_ctrl2;
354 uint32_t tx_l0_res_code_lane_tx;
355 uint32_t tx_l1_res_code_lane_tx;
356 uint32_t tx_l2_res_code_lane_tx;
357 uint32_t tx_l3_res_code_lane_tx;
358 uint32_t phy_mode;
359};
360
361void hdmi_phy_reset(void)
362{
363 uint32_t phy_reset_polarity = 0x0;
364 uint32_t pll_reset_polarity = 0x0;
365 uint32_t val;
366
367 val = readl(HDMI_PHY_CTRL);
368
369 phy_reset_polarity = val >> 3 & 0x1;
370 pll_reset_polarity = val >> 1 & 0x1;
371
372 if (phy_reset_polarity == 0)
373 writel(val | SW_RESET, HDMI_PHY_CTRL);
374 else
375 writel(val & (~SW_RESET), HDMI_PHY_CTRL);
376
377 if (pll_reset_polarity == 0)
378 writel(val | SW_RESET_PLL, HDMI_PHY_CTRL);
379 else
380 writel(val & (~SW_RESET_PLL), HDMI_PHY_CTRL);
381
382 if (phy_reset_polarity == 0)
383 writel(val & (~SW_RESET), HDMI_PHY_CTRL);
384 else
385 writel(val | SW_RESET, HDMI_PHY_CTRL);
386
387 if (pll_reset_polarity == 0)
388 writel(val & (~SW_RESET_PLL), HDMI_PHY_CTRL);
389 else
390 writel(val | SW_RESET_PLL, HDMI_PHY_CTRL);
391
392 udelay(100);
393}
394
395static int get_pll_settings(uint32_t tmds_clk_rate,
396 struct hdmi_8996_phy_pll_reg_cfg *cfg)
397{
398 switch (tmds_clk_rate) {
399 case HDMI_CLK_RATE_148_MHZ:
400 cfg->tx_l0_lane_mode = 0x43;
401 cfg->tx_l2_lane_mode = 0x43;
402 cfg->tx_l0_tx_band = 0x04;
403 cfg->tx_l1_tx_band = 0x04;
404 cfg->tx_l2_tx_band = 0x04;
405 cfg->tx_l3_tx_band = 0x04;
406 cfg->com_svs_mode_clk_sel = 0x2;
407 cfg->com_hsclk_sel = 0x21;
408 cfg->com_pll_cctrl_mode0 = 0x28;
409 cfg->com_pll_rctrl_mode0 = 0x16;
410 cfg->com_cp_ctrl_mode0 = 0xb;
411 cfg->com_dec_start_mode0 = 0x74;
412 cfg->com_div_frac_start1_mode0 = 0x0;
413 cfg->com_div_frac_start2_mode0 = 0x40;
414 cfg->com_div_frac_start3_mode0 = 0x0;
415 cfg->com_integloop_gain0_mode0 = 0x0;
416 cfg->com_integloop_gain1_mode0 = 0x1;
417 cfg->com_lock_cmp_en = 0x0;
418 cfg->com_lock_cmp1_mode0 = 0xef;
419 cfg->com_lock_cmp2_mode0 = 0x1e;
420 cfg->com_lock_cmp3_mode0 = 0x0;
421 cfg->com_core_clk_en = 0x2c;
422 cfg->com_coreclk_div = 0x5;
423 cfg->com_restrim_ctrl = 0x0;
424 cfg->com_vco_tune_ctrl = 0x0;
425 cfg->tx_l0_tx_drv_lvl = 0x25;
426 cfg->tx_l0_tx_emp_post1_lvl = 0x23;
427 cfg->tx_l1_tx_drv_lvl = 0x25;
428 cfg->tx_l1_tx_emp_post1_lvl = 0x23;
429 cfg->tx_l2_tx_drv_lvl = 0x25;
430 cfg->tx_l2_tx_emp_post1_lvl = 0x23;
431 cfg->tx_l3_tx_drv_lvl = 0x25;
432 cfg->tx_l3_tx_emp_post1_lvl = 0x23;
433 cfg->tx_l0_vmode_ctrl1 = 0x0;
434 cfg->tx_l0_vmode_ctrl2 = 0xd;
435 cfg->tx_l1_vmode_ctrl1 = 0x0;
436 cfg->tx_l1_vmode_ctrl2 = 0xd;
437 cfg->tx_l2_vmode_ctrl1 = 0x0;
438 cfg->tx_l2_vmode_ctrl2 = 0xd;
439 cfg->tx_l3_vmode_ctrl1 = 0x0;
440 cfg->tx_l3_vmode_ctrl2 = 0x0;
441 cfg->tx_l0_res_code_lane_tx = 0x0;
442 cfg->tx_l1_res_code_lane_tx = 0x0;
443 cfg->tx_l2_res_code_lane_tx = 0x0;
444 cfg->tx_l3_res_code_lane_tx = 0x0;
445 cfg->phy_mode = 0x0;
446 break;
447 case HDMI_CLK_RATE_74_MHZ:
448 cfg->tx_l0_lane_mode = 0x43;
449 cfg->tx_l2_lane_mode = 0x43;
450 cfg->tx_l0_tx_band = 0x04;
451 cfg->tx_l1_tx_band = 0x04;
452 cfg->tx_l2_tx_band = 0x04;
453 cfg->tx_l3_tx_band = 0x04;
454 cfg->com_svs_mode_clk_sel = 0x2;
455 cfg->com_hsclk_sel = 0x29;
456 cfg->com_pll_cctrl_mode0 = 0x28;
457 cfg->com_pll_rctrl_mode0 = 0x16;
458 cfg->com_cp_ctrl_mode0 = 0xb;
459 cfg->com_dec_start_mode0 = 0x74;
460 cfg->com_div_frac_start1_mode0 = 0x0;
461 cfg->com_div_frac_start2_mode0 = 0x40;
462 cfg->com_div_frac_start3_mode0 = 0x0;
463 cfg->com_integloop_gain0_mode0 = 0x0;
464 cfg->com_integloop_gain1_mode0 = 0x1;
465 cfg->com_lock_cmp_en = 0x0;
466 cfg->com_lock_cmp1_mode0 = 0x77;
467 cfg->com_lock_cmp2_mode0 = 0xf;
468 cfg->com_lock_cmp3_mode0 = 0x0;
469 cfg->com_core_clk_en = 0x2c;
470 cfg->com_coreclk_div = 0x5;
471 cfg->com_restrim_ctrl = 0x0;
472 cfg->com_vco_tune_ctrl = 0x0;
473 cfg->tx_l0_tx_drv_lvl = 0x20;
474 cfg->tx_l0_tx_emp_post1_lvl = 0x20;
475 cfg->tx_l1_tx_drv_lvl = 0x20;
476 cfg->tx_l1_tx_emp_post1_lvl = 0x20;
477 cfg->tx_l2_tx_drv_lvl = 0x20;
478 cfg->tx_l2_tx_emp_post1_lvl = 0x20;
479 cfg->tx_l3_tx_drv_lvl = 0x20;
480 cfg->tx_l3_tx_emp_post1_lvl = 0x20;
481 cfg->tx_l0_vmode_ctrl1 = 0x0;
482 cfg->tx_l0_vmode_ctrl2 = 0xe;
483 cfg->tx_l1_vmode_ctrl1 = 0x0;
484 cfg->tx_l1_vmode_ctrl2 = 0xe;
485 cfg->tx_l2_vmode_ctrl1 = 0x0;
486 cfg->tx_l2_vmode_ctrl2 = 0xe;
487 cfg->tx_l3_vmode_ctrl1 = 0x0;
488 cfg->tx_l3_vmode_ctrl2 = 0xe;
489 cfg->tx_l0_res_code_lane_tx = 0x0;
490 cfg->tx_l1_res_code_lane_tx = 0x0;
491 cfg->tx_l2_res_code_lane_tx = 0x0;
492 cfg->tx_l3_res_code_lane_tx = 0x0;
493 cfg->phy_mode = 0x0;
494 break;
495 case HDMI_CLK_RATE_25_MHZ:
496 cfg->tx_l0_lane_mode = 0x43;
497 cfg->tx_l2_lane_mode = 0x43;
498 cfg->tx_l0_tx_band = 0x7;
499 cfg->tx_l1_tx_band = 0x7;
500 cfg->tx_l2_tx_band = 0x7;
501 cfg->tx_l3_tx_band = 0x7;
502 cfg->com_svs_mode_clk_sel = 0x2;
503 cfg->com_hsclk_sel = 0x28;
504 cfg->com_pll_cctrl_mode0 = 0x1;
505 cfg->com_pll_rctrl_mode0 = 0x10;
506 cfg->com_cp_ctrl_mode0 = 0x23;
507 cfg->com_dec_start_mode0 = 0x69;
508 cfg->com_div_frac_start1_mode0 = 0x0;
509 cfg->com_div_frac_start2_mode0 = 0x0;
510 cfg->com_div_frac_start3_mode0 = 0x0;
511 cfg->com_integloop_gain0_mode0 = 0x10;
512 cfg->com_integloop_gain1_mode0 = 0x3;
513 cfg->com_lock_cmp_en = 0x0;
514 cfg->com_lock_cmp1_mode0 = 0xff;
515 cfg->com_lock_cmp2_mode0 = 0x29;
516 cfg->com_lock_cmp3_mode0 = 0x0;
517 cfg->com_core_clk_en = 0x2c;
518 cfg->com_coreclk_div = 0x5;
519 cfg->com_restrim_ctrl = 0x0;
520 cfg->com_vco_tune_ctrl = 0x0;
521 cfg->tx_l0_tx_drv_lvl = 0x20;
522 cfg->tx_l0_tx_emp_post1_lvl = 0x20;
523 cfg->tx_l1_tx_drv_lvl = 0x20;
524 cfg->tx_l1_tx_emp_post1_lvl = 0x20;
525 cfg->tx_l2_tx_drv_lvl = 0x20;
526 cfg->tx_l2_tx_emp_post1_lvl = 0x20;
527 cfg->tx_l3_tx_drv_lvl = 0x20;
528 cfg->tx_l3_tx_emp_post1_lvl = 0x20;
529 cfg->tx_l0_vmode_ctrl1 = 0x0;
530 cfg->tx_l0_vmode_ctrl2 = 0xe;
531 cfg->tx_l1_vmode_ctrl1 = 0x0;
532 cfg->tx_l1_vmode_ctrl2 = 0xe;
533 cfg->tx_l2_vmode_ctrl1 = 0x0;
534 cfg->tx_l2_vmode_ctrl2 = 0xe;
535 cfg->tx_l3_vmode_ctrl1 = 0x0;
536 cfg->tx_l3_vmode_ctrl2 = 0xe;
537 cfg->tx_l0_res_code_lane_tx = 0x0;
538 cfg->tx_l1_res_code_lane_tx = 0x0;
539 cfg->tx_l2_res_code_lane_tx = 0x0;
540 cfg->tx_l3_res_code_lane_tx = 0x0;
541 cfg->phy_mode = 0x0;
542 break;
Tatenda Chipeperekwabf5c4072016-02-23 18:22:42 -0800[diff] [blame]543 case HDMI_CLK_RATE_297_MHZ:
544 cfg->tx_l0_lane_mode = 0x43;
545 cfg->tx_l2_lane_mode = 0x43;
546 cfg->tx_l0_tx_band = 0x4;
547 cfg->tx_l1_tx_band = 0x4;
548 cfg->tx_l2_tx_band = 0x4;
549 cfg->tx_l3_tx_band = 0x4;
550 cfg->com_svs_mode_clk_sel = 0x1;
551 cfg->com_hsclk_sel = 0x24;
552 cfg->com_pll_cctrl_mode0 = 0x28;
553 cfg->com_pll_rctrl_mode0 = 0x16;
554 cfg->com_cp_ctrl_mode0 = 0xb;
555 cfg->com_dec_start_mode0 = 0x74;
556 cfg->com_div_frac_start1_mode0 = 0x0;
557 cfg->com_div_frac_start2_mode0 = 0x40;
558 cfg->com_div_frac_start3_mode0 = 0x0;
559 cfg->com_integloop_gain0_mode0 = 0x80;
560 cfg->com_integloop_gain1_mode0 = 0x0;
561 cfg->com_lock_cmp_en = 0x0;
562 cfg->com_lock_cmp1_mode0 = 0xdf;
563 cfg->com_lock_cmp2_mode0 = 0x3d;
564 cfg->com_lock_cmp3_mode0 = 0x0;
565 cfg->com_core_clk_en = 0x2c;
566 cfg->com_coreclk_div = 0x5;
567 cfg->com_restrim_ctrl = 0x0;
568 cfg->com_vco_tune_ctrl = 0x0;
569 cfg->tx_l0_tx_drv_lvl = 0x25;
570 cfg->tx_l0_tx_emp_post1_lvl = 0x23;
571 cfg->tx_l1_tx_drv_lvl = 0x25;
572 cfg->tx_l1_tx_emp_post1_lvl = 0x23;
573 cfg->tx_l2_tx_drv_lvl = 0x25;
574 cfg->tx_l2_tx_emp_post1_lvl = 0x23;
575 cfg->tx_l3_tx_drv_lvl = 0x25;
576 cfg->tx_l3_tx_emp_post1_lvl = 0x23;
577 cfg->tx_l0_vmode_ctrl1 = 0x0;
578 cfg->tx_l0_vmode_ctrl2 = 0xd;
579 cfg->tx_l1_vmode_ctrl1 = 0x0;
580 cfg->tx_l1_vmode_ctrl2 = 0xd;
581 cfg->tx_l2_vmode_ctrl1 = 0x0;
582 cfg->tx_l2_vmode_ctrl2 = 0xd;
583 cfg->tx_l3_vmode_ctrl1 = 0x0;
584 cfg->tx_l3_vmode_ctrl2 = 0x0;
585 cfg->tx_l0_res_code_lane_tx = 0x0;
586 cfg->tx_l1_res_code_lane_tx = 0x0;
587 cfg->tx_l2_res_code_lane_tx = 0x0;
588 cfg->tx_l3_res_code_lane_tx = 0x0;
589 cfg->phy_mode = 0x00;
590 break;
Tatenda Chipeperekwab99628c2016-03-15 09:54:37 -0700[diff] [blame]591 case HDMI_CLK_RATE_594_MHZ:
592 cfg->tx_l0_lane_mode = 0x43;
593 cfg->tx_l2_lane_mode = 0x43;
594 cfg->tx_l0_tx_band = 0x4;
595 cfg->tx_l1_tx_band = 0x4;
596 cfg->tx_l2_tx_band = 0x4;
597 cfg->tx_l3_tx_band = 0x4;
598 cfg->com_svs_mode_clk_sel = 0x1;
599 cfg->com_hsclk_sel = 0x20;
600 cfg->com_pll_cctrl_mode0 = 0x28;
601 cfg->com_pll_rctrl_mode0 = 0x16;
602 cfg->com_cp_ctrl_mode0 = 0xb;
603 cfg->com_dec_start_mode0 = 0x9a;
604 cfg->com_div_frac_start1_mode0 = 0x0;
605 cfg->com_div_frac_start2_mode0 = 0x0;
606 cfg->com_div_frac_start3_mode0 = 0xb;
607 cfg->com_integloop_gain0_mode0 = 0x80;
608 cfg->com_integloop_gain1_mode0 = 0x0;
609 cfg->com_lock_cmp_en = 0x0;
610 cfg->com_lock_cmp1_mode0 = 0xbf;
611 cfg->com_lock_cmp2_mode0 = 0x7b;
612 cfg->com_lock_cmp3_mode0 = 0x0;
613 cfg->com_core_clk_en = 0x2c;
614 cfg->com_coreclk_div = 0x5;
615 cfg->com_restrim_ctrl = 0x0;
616 cfg->com_vco_tune_ctrl = 0x0;
617 cfg->tx_l0_tx_drv_lvl = 0x25;
618 cfg->tx_l0_tx_emp_post1_lvl = 0x23;
619 cfg->tx_l1_tx_drv_lvl = 0x25;
620 cfg->tx_l1_tx_emp_post1_lvl = 0x23;
621 cfg->tx_l2_tx_drv_lvl = 0x25;
622 cfg->tx_l2_tx_emp_post1_lvl = 0x23;
623 cfg->tx_l3_tx_drv_lvl = 0x22;
624 cfg->tx_l3_tx_emp_post1_lvl = 0x27;
625 cfg->tx_l0_vmode_ctrl1 = 0x0;
626 cfg->tx_l0_vmode_ctrl2 = 0xd;
627 cfg->tx_l1_vmode_ctrl1 = 0x0;
628 cfg->tx_l1_vmode_ctrl2 = 0xd;
629 cfg->tx_l2_vmode_ctrl1 = 0x0;
630 cfg->tx_l2_vmode_ctrl2 = 0xd;
631 cfg->tx_l3_vmode_ctrl1 = 0x0;
632 cfg->tx_l3_vmode_ctrl2 = 0x0;
633 cfg->tx_l0_res_code_lane_tx = 0x0;
634 cfg->tx_l1_res_code_lane_tx = 0x0;
635 cfg->tx_l2_res_code_lane_tx = 0x0;
636 cfg->tx_l3_res_code_lane_tx = 0x0;
637 cfg->phy_mode = 0x10;
638 break;
Tatenda Chipeperekwa357f2dd2015-11-10 14:05:32 -0800[diff] [blame]639 default:
640 return ERROR;
641 }
642
643 return NO_ERROR;
644
645}
646
647uint32_t hdmi_pll_config(uint32_t tmds_clk_rate)
648{
649 struct hdmi_8996_phy_pll_reg_cfg cfg = {0};
650 int rc = NO_ERROR;
651
652 rc = get_pll_settings(tmds_clk_rate, &cfg);
653 if (rc) {
654 dprintf(CRITICAL, "%s: Unsupported clock rate %u\n", __func__, tmds_clk_rate);
655 return rc;
656 }
657
658 /* Initially shut down PHY */
659 writel(0x0, HDMI_PHY_PD_CTL);
660 udelay(500);
661
662 /* Power up sequence */
663 writel(0x04, QSERDES_COM_BG_CTRL);
664
665 writel(0x1, HDMI_PHY_PD_CTL);
666 writel(0x20, QSERDES_COM_RESETSM_CNTRL);
667 writel(0x0F, HDMI_PHY_TX0_TX1_LANE_CTL);
668 writel(0x0F, HDMI_PHY_TX2_TX3_LANE_CTL);
669 writel(0x03, HDMI_TX_L0_BASE_OFFSET +
670 QSERDES_TX_L0_CLKBUF_ENABLE);
671 writel(0x03, HDMI_TX_L1_BASE_OFFSET +
672 QSERDES_TX_L0_CLKBUF_ENABLE);
673 writel(0x03, HDMI_TX_L2_BASE_OFFSET +
674 QSERDES_TX_L0_CLKBUF_ENABLE);
675 writel(0x03, HDMI_TX_L3_BASE_OFFSET +
676 QSERDES_TX_L0_CLKBUF_ENABLE);
677
678 writel(cfg.tx_l0_lane_mode, HDMI_TX_L0_BASE_OFFSET +
679 QSERDES_TX_L0_LANE_MODE);
680 writel(cfg.tx_l2_lane_mode, HDMI_TX_L2_BASE_OFFSET +
681 QSERDES_TX_L0_LANE_MODE);
682
683 writel(cfg.tx_l0_tx_band, HDMI_TX_L0_BASE_OFFSET +
684 QSERDES_TX_L0_TX_BAND);
685 writel(cfg.tx_l1_tx_band, HDMI_TX_L1_BASE_OFFSET +
686 QSERDES_TX_L0_TX_BAND);
687 writel(cfg.tx_l2_tx_band, HDMI_TX_L2_BASE_OFFSET +
688 QSERDES_TX_L0_TX_BAND);
689 writel(cfg.tx_l3_tx_band, HDMI_TX_L3_BASE_OFFSET +
690 QSERDES_TX_L0_TX_BAND);
691
692 writel(0x03, HDMI_TX_L0_BASE_OFFSET +
693 QSERDES_TX_L0_RESET_TSYNC_EN);
694 writel(0x03, HDMI_TX_L1_BASE_OFFSET +
695 QSERDES_TX_L0_RESET_TSYNC_EN);
696 writel(0x03, HDMI_TX_L2_BASE_OFFSET +
697 QSERDES_TX_L0_RESET_TSYNC_EN);
698 writel(0x03, HDMI_TX_L3_BASE_OFFSET +
699 QSERDES_TX_L0_RESET_TSYNC_EN);
700
701 writel(0x1E, QSERDES_COM_SYSCLK_BUF_ENABLE);
702 writel(0x07, QSERDES_COM_BIAS_EN_CLKBUFLR_EN);
703 writel(0x37, QSERDES_COM_SYSCLK_EN_SEL);
704 writel(0x02, QSERDES_COM_SYS_CLK_CTRL);
705 writel(0x0E, QSERDES_COM_CLK_ENABLE1);
706
707 /* Bypass VCO calibration */
708 writel(cfg.com_svs_mode_clk_sel, QSERDES_COM_SVS_MODE_CLK_SEL);
709
710 writel(0x0F, QSERDES_COM_BG_TRIM);
711 writel(0x0F, QSERDES_COM_PLL_IVCO);
712 writel(cfg.com_vco_tune_ctrl, QSERDES_COM_VCO_TUNE_CTRL);
713
714 writel(0x06, QSERDES_COM_BG_CTRL);
715
716 writel(0x30, QSERDES_COM_CLK_SELECT);
717 writel(cfg.com_hsclk_sel, QSERDES_COM_HSCLK_SEL);
718
719 writel(cfg.com_lock_cmp_en, QSERDES_COM_LOCK_CMP_EN);
720
721 writel(cfg.com_pll_cctrl_mode0, QSERDES_COM_PLL_CCTRL_MODE0);
722 writel(cfg.com_pll_rctrl_mode0, QSERDES_COM_PLL_RCTRL_MODE0);
723 writel(cfg.com_cp_ctrl_mode0, QSERDES_COM_CP_CTRL_MODE0);
724 writel(cfg.com_dec_start_mode0, QSERDES_COM_DEC_START_MODE0);
725 writel(cfg.com_div_frac_start1_mode0, QSERDES_COM_DIV_FRAC_START1_MODE0);
726 writel(cfg.com_div_frac_start2_mode0, QSERDES_COM_DIV_FRAC_START2_MODE0);
727 writel(cfg.com_div_frac_start3_mode0, QSERDES_COM_DIV_FRAC_START3_MODE0);
728
729 writel(cfg.com_integloop_gain0_mode0, QSERDES_COM_INTEGLOOP_GAIN0_MODE0);
730 writel(cfg.com_integloop_gain1_mode0, QSERDES_COM_INTEGLOOP_GAIN1_MODE0);
731
732 writel(cfg.com_lock_cmp1_mode0, QSERDES_COM_LOCK_CMP1_MODE0);
733 writel(cfg.com_lock_cmp2_mode0, QSERDES_COM_LOCK_CMP2_MODE0);
734 writel(cfg.com_lock_cmp3_mode0, QSERDES_COM_LOCK_CMP3_MODE0);
735
736 writel(0x00, QSERDES_COM_VCO_TUNE_MAP);
737 writel(cfg.com_core_clk_en, QSERDES_COM_CORE_CLK_EN);
738 writel(cfg.com_coreclk_div, QSERDES_COM_CORECLK_DIV);
739 writel(0x02, QSERDES_COM_CMN_CONFIG);
740
741 writel(0x15, QSERDES_COM_RESCODE_DIV_NUM);
742
743 /* TX lanes setup (TX 0/1/2/3) */
744 writel(cfg.tx_l0_tx_drv_lvl, HDMI_TX_L0_BASE_OFFSET +
745 QSERDES_TX_L0_TX_DRV_LVL);
746 writel(cfg.tx_l0_tx_emp_post1_lvl, HDMI_TX_L0_BASE_OFFSET +
747 QSERDES_TX_L0_TX_EMP_POST1_LVL);
748
749 writel(cfg.tx_l1_tx_drv_lvl, HDMI_TX_L1_BASE_OFFSET +
750 QSERDES_TX_L0_TX_DRV_LVL);
751 writel(cfg.tx_l1_tx_emp_post1_lvl, HDMI_TX_L1_BASE_OFFSET +
752 QSERDES_TX_L0_TX_EMP_POST1_LVL);
753
754 writel(cfg.tx_l2_tx_drv_lvl, HDMI_TX_L2_BASE_OFFSET +
755 QSERDES_TX_L0_TX_DRV_LVL);
756 writel(cfg.tx_l2_tx_emp_post1_lvl, HDMI_TX_L2_BASE_OFFSET +
757 QSERDES_TX_L0_TX_EMP_POST1_LVL);
758
759 writel(cfg.tx_l3_tx_drv_lvl, HDMI_TX_L3_BASE_OFFSET +
760 QSERDES_TX_L0_TX_DRV_LVL);
761 writel(cfg.tx_l3_tx_emp_post1_lvl, HDMI_TX_L3_BASE_OFFSET +
762 QSERDES_TX_L0_TX_EMP_POST1_LVL);
763
764 writel(cfg.tx_l0_vmode_ctrl1, HDMI_TX_L0_BASE_OFFSET +
765 QSERDES_TX_L0_VMODE_CTRL1);
766 writel(cfg.tx_l0_vmode_ctrl2, HDMI_TX_L0_BASE_OFFSET +
767 QSERDES_TX_L0_VMODE_CTRL2);
768
769 writel(cfg.tx_l1_vmode_ctrl1, HDMI_TX_L1_BASE_OFFSET +
770 QSERDES_TX_L0_VMODE_CTRL1);
771 writel(cfg.tx_l1_vmode_ctrl2, HDMI_TX_L1_BASE_OFFSET +
772 QSERDES_TX_L0_VMODE_CTRL2);
773
774 writel(cfg.tx_l2_vmode_ctrl1, HDMI_TX_L2_BASE_OFFSET +
775 QSERDES_TX_L0_VMODE_CTRL1);
776 writel(cfg.tx_l2_vmode_ctrl2, HDMI_TX_L2_BASE_OFFSET +
777 QSERDES_TX_L0_VMODE_CTRL2);
778
779 writel(cfg.tx_l3_vmode_ctrl1, HDMI_TX_L3_BASE_OFFSET +
780 QSERDES_TX_L0_VMODE_CTRL1);
781 writel(cfg.tx_l3_vmode_ctrl2, HDMI_TX_L3_BASE_OFFSET +
782 QSERDES_TX_L0_VMODE_CTRL2);
783
784 writel(0x00, HDMI_TX_L0_BASE_OFFSET +
785 QSERDES_TX_L0_TX_DRV_LVL_OFFSET);
786 writel(0x00, HDMI_TX_L1_BASE_OFFSET +
787 QSERDES_TX_L0_TX_DRV_LVL_OFFSET);
788 writel(0x00, HDMI_TX_L2_BASE_OFFSET +
789 QSERDES_TX_L0_TX_DRV_LVL_OFFSET);
790 writel(0x00, HDMI_TX_L3_BASE_OFFSET +
791 QSERDES_TX_L0_TX_DRV_LVL_OFFSET);
792
793 writel(0x00, HDMI_TX_L0_BASE_OFFSET +
794 QSERDES_TX_L0_RES_CODE_LANE_OFFSET);
795 writel(0x00, HDMI_TX_L1_BASE_OFFSET +
796 QSERDES_TX_L0_RES_CODE_LANE_OFFSET);
797 writel(0x00, HDMI_TX_L2_BASE_OFFSET +
798 QSERDES_TX_L0_RES_CODE_LANE_OFFSET);
799 writel(0x00, HDMI_TX_L3_BASE_OFFSET +
800 QSERDES_TX_L0_RES_CODE_LANE_OFFSET);
801
802 writel(cfg.phy_mode, HDMI_PHY_MODE);
803 writel(0x1F, HDMI_PHY_PD_CTL);
804
805 writel(0x03, HDMI_TX_L0_BASE_OFFSET +
806 QSERDES_TX_L0_TRAN_DRVR_EMP_EN);
807 writel(0x03, HDMI_TX_L1_BASE_OFFSET +
808 QSERDES_TX_L0_TRAN_DRVR_EMP_EN);
809 writel(0x03, HDMI_TX_L2_BASE_OFFSET +
810 QSERDES_TX_L0_TRAN_DRVR_EMP_EN);
811 writel(0x03, HDMI_TX_L3_BASE_OFFSET +
812 QSERDES_TX_L0_TRAN_DRVR_EMP_EN);
813
814 writel(0x40, HDMI_TX_L0_BASE_OFFSET +
815 QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN);
816 writel(0x40, HDMI_TX_L1_BASE_OFFSET +
817 QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN);
818 writel(0x40, HDMI_TX_L2_BASE_OFFSET +
819 QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN);
820 writel(0x40, HDMI_TX_L3_BASE_OFFSET +
821 QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN);
822
823 writel(0x0C, HDMI_TX_L0_BASE_OFFSET +
824 QSERDES_TX_L0_HP_PD_ENABLES);
825 writel(0x0C, HDMI_TX_L1_BASE_OFFSET +
826 QSERDES_TX_L0_HP_PD_ENABLES);
827 writel(0x0C, HDMI_TX_L2_BASE_OFFSET +
828 QSERDES_TX_L0_HP_PD_ENABLES);
829 writel(0x03, HDMI_TX_L3_BASE_OFFSET +
830 QSERDES_TX_L0_HP_PD_ENABLES);
831
832 return NO_ERROR;
833}
834
835int hdmi_vco_enable(void)
836{
837 uint32_t pll_locked = 0;
838 uint32_t phy_ready = 0;
839 uint32_t status = 0;
840 uint32_t num_reads = 0;
841
842 writel(0x1, HDMI_PHY_CFG);
843 udelay(100);
844
845 writel(0x19, HDMI_PHY_CFG);
846 udelay(100);
847
848 num_reads = HDMI_PLL_POLL_MAX_READS;
849 status = readl(QSERDES_COM_C_READY_STATUS);
850 while (!(status & BIT(0)) && num_reads) {
851 status = readl(QSERDES_COM_C_READY_STATUS);
852 num_reads--;
853 udelay(HDMI_PLL_POLL_TIMEOUT_US);
854 }
855
856 if ((status & BIT(0)) == 1 && num_reads) {
857 pll_locked = 1;
858 } else {
859 pll_locked = 0;
860 }
861
862 dprintf(INFO, "%s: pll_locked = %d\n", __func__, pll_locked);
863
864 writel(0x6F, HDMI_TX_L0_BASE_OFFSET +
865 QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN);
866 writel(0x6F, HDMI_TX_L1_BASE_OFFSET +
867 QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN);
868 writel(0x6F, HDMI_TX_L2_BASE_OFFSET +
869 QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN);
870 writel(0x6F, HDMI_TX_L3_BASE_OFFSET +
871 QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN);
872
873 /* Disable SSC */
874 writel(0x0, QSERDES_COM_SSC_PER1);
875 writel(0x0, QSERDES_COM_SSC_PER2);
876 writel(0x0, QSERDES_COM_SSC_STEP_SIZE1);
877 writel(0x0, QSERDES_COM_SSC_STEP_SIZE2);
878 writel(0x2, QSERDES_COM_SSC_EN_CENTER);
879
880 num_reads = HDMI_PLL_POLL_MAX_READS;
881 status = readl(HDMI_PHY_STATUS);
882 while (!(status & BIT(0)) && num_reads) {
Tatenda Chipeperekwa82638a62016-01-27 12:30:19 -0800[diff] [blame]883 status = readl(HDMI_PHY_STATUS);
Tatenda Chipeperekwa357f2dd2015-11-10 14:05:32 -0800[diff] [blame]884 num_reads--;
885 udelay(HDMI_PLL_POLL_TIMEOUT_US);
886 }
887
888 if ((status & BIT(0)) == 1 && num_reads) {
889 phy_ready = 1;
890 } else {
891 phy_ready = 0;
892 }
893
894 dprintf(INFO, "%s: phy_ready = %d\n", __func__, phy_ready);
895
896 /* Restart the retiming buffer */
897 writel(0x18, HDMI_PHY_CFG);
898 udelay(1);
899 writel(0x19, HDMI_PHY_CFG);
900
901 return NO_ERROR;
902}
903
904int hdmi_vco_disable(void)
905{
906 writel(0x0, HDMI_PHY_PD_CTL);
907 udelay(500);
908
909 return NO_ERROR;
910}