| V S Ramanjaneya Kumar T | 713be57 | 2013-08-02 11:00:10 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2013, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #ifndef _PLATFORM_FSM9900_IOMAP_H_ |
| 30 | #define _PLATFORM_FSM9900_IOMAP_H_ |
| 31 | |
| 32 | #define MSM_IOMAP_BASE 0xF9000000 |
| 33 | #define MSM_IOMAP_END 0xFEFFFFFF |
| 34 | |
| 35 | #define SDRAM_START_ADDR 0x00000000 |
| 36 | #define SDRAM_SEC_BANK_START_ADDR 0x10000000 |
| 37 | |
| V S Ramanjaneya Kumar T | c194589 | 2013-08-27 11:39:53 +0530 | [diff] [blame] | 38 | #define MSM_SHARED_BASE 0x1C100000 |
| V S Ramanjaneya Kumar T | 713be57 | 2013-08-02 11:00:10 +0530 | [diff] [blame] | 39 | |
| 40 | #define RPM_MSG_RAM_BASE 0xFC42B000 |
| 41 | #define SYSTEM_IMEM_BASE 0xFE800000 |
| 42 | #define MSM_SHARED_IMEM_BASE 0xFE805000 |
| 43 | |
| 44 | #define RESTART_REASON_ADDR (RPM_MSG_RAM_BASE + 0x65C) |
| 45 | #define RESTART_REASON_ADDR_V2 (MSM_SHARED_IMEM_BASE + 0x65C) |
| 46 | #define DLOAD_MODE_ADDR_V2 (MSM_SHARED_IMEM_BASE + 0x0) |
| 47 | #define EMERGENCY_DLOAD_MODE_ADDR_V2 (MSM_SHARED_IMEM_BASE + 0xFE0) |
| 48 | |
| 49 | #define KPSS_BASE 0xF9000000 |
| 50 | |
| 51 | #define MSM_GIC_DIST_BASE KPSS_BASE |
| 52 | #define MSM_GIC_CPU_BASE (KPSS_BASE + 0x2000) |
| 53 | #define APCS_KPSS_ACS_BASE (KPSS_BASE + 0x00008000) |
| 54 | #define APCS_APC_KPSS_PLL_BASE (KPSS_BASE + 0x0000A000) |
| 55 | #define APCS_KPSS_CFG_BASE (KPSS_BASE + 0x00010000) |
| 56 | #define APCS_KPSS_WDT_BASE (KPSS_BASE + 0x00017000) |
| 57 | #define KPSS_APCS_QTMR_AC_BASE (KPSS_BASE + 0x00020000) |
| 58 | #define KPSS_APCS_F0_QTMR_V1_BASE (KPSS_BASE + 0x00021000) |
| 59 | #define QTMR_BASE KPSS_APCS_F0_QTMR_V1_BASE |
| 60 | |
| 61 | #define PERIPH_SS_BASE 0xF9800000 |
| 62 | |
| 63 | #define MSM_SDC1_BAM_BASE (PERIPH_SS_BASE + 0x00004000) |
| 64 | #define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000) |
| 65 | #define MSM_SDC1_DML_BASE (PERIPH_SS_BASE + 0x00024800) |
| 66 | #define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900) |
| 67 | #define MSM_SDC2_BAM_BASE (PERIPH_SS_BASE + 0x00084000) |
| 68 | #define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000) |
| 69 | #define MSM_SDC2_DML_BASE (PERIPH_SS_BASE + 0x000A4800) |
| 70 | #define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900) |
| 71 | |
| 72 | /* BLSP1_UART[0:5] */ |
| 73 | #define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0011D000) |
| 74 | #define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x0011E000) |
| 75 | #define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x0011F000) |
| 76 | #define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00120000) |
| 77 | #define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00121000) |
| 78 | #define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000) |
| 79 | |
| 80 | /* BLSP2_UART[0:5] */ |
| 81 | #define BLSP2_UART0_BASE (PERIPH_SS_BASE + 0x0015D000) |
| 82 | #define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x0015E000) |
| 83 | #define BLSP2_UART2_BASE (PERIPH_SS_BASE + 0x0015F000) |
| 84 | #define BLSP2_UART3_BASE (PERIPH_SS_BASE + 0x00160000) |
| 85 | #define BLSP2_UART4_BASE (PERIPH_SS_BASE + 0x00161000) |
| 86 | #define BLSP2_UART5_BASE (PERIPH_SS_BASE + 0x00162000) |
| 87 | |
| V S Ramanjaneya Kumar T | d32b532 | 2013-08-07 19:59:55 +0530 | [diff] [blame] | 88 | #define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000) |
| 89 | |
| V S Ramanjaneya Kumar T | 713be57 | 2013-08-02 11:00:10 +0530 | [diff] [blame] | 90 | #define CLK_CTL_BASE 0xFC400000 |
| 91 | |
| 92 | #define GCC_WDOG_DEBUG (CLK_CTL_BASE + 0x00001780) |
| 93 | |
| 94 | #define USB_HS_BCR (CLK_CTL_BASE + 0x480) |
| 95 | |
| 96 | #define SPMI_BASE 0xFC4C0000 |
| 97 | #define SPMI_GENI_BASE (SPMI_BASE + 0xA000) |
| 98 | #define SPMI_PIC_BASE (SPMI_BASE + 0xB000) |
| 99 | |
| 100 | #define MSM_CE2_BAM_BASE 0xFD444000 |
| 101 | #define MSM_CE2_BASE 0xFD45A000 |
| 102 | |
| 103 | #define TLMM_BASE_ADDR 0xFD510000 |
| 104 | #define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10) |
| 105 | #define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10) |
| 106 | |
| 107 | #define MPM2_MPM_CTRL_BASE 0xFC4A1000 |
| 108 | #define MPM2_MPM_PS_HOLD 0xFC4AB000 |
| 109 | #define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000 |
| 110 | |
| 111 | /* CE 1 */ |
| 112 | #define GCC_CE1_BCR (CLK_CTL_BASE + 0x1040) |
| 113 | #define GCC_CE1_CMD_RCGR (CLK_CTL_BASE + 0x1050) |
| 114 | #define GCC_CE1_CFG_RCGR (CLK_CTL_BASE + 0x1054) |
| 115 | #define GCC_CE1_CBCR (CLK_CTL_BASE + 0x1044) |
| 116 | #define GCC_CE1_AXI_CBCR (CLK_CTL_BASE + 0x1048) |
| 117 | #define GCC_CE1_AHB_CBCR (CLK_CTL_BASE + 0x104C) |
| 118 | |
| 119 | /* CE 2 */ |
| 120 | #define GCC_CE2_BCR (CLK_CTL_BASE + 0x1080) |
| 121 | #define GCC_CE2_CMD_RCGR (CLK_CTL_BASE + 0x1090) |
| 122 | #define GCC_CE2_CFG_RCGR (CLK_CTL_BASE + 0x1094) |
| 123 | #define GCC_CE2_CBCR (CLK_CTL_BASE + 0x1084) |
| 124 | #define GCC_CE2_AXI_CBCR (CLK_CTL_BASE + 0x1088) |
| 125 | #define GCC_CE2_AHB_CBCR (CLK_CTL_BASE + 0x108C) |
| 126 | |
| 127 | /* GPLL */ |
| 128 | #define GPLL0_STATUS (CLK_CTL_BASE + 0x001C) |
| 129 | #define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480) |
| 130 | #define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484) |
| 131 | |
| 132 | /* SDCC 1 */ |
| 133 | #define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */ |
| 134 | #define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */ |
| 135 | #define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4C8) |
| 136 | #define SDCC1_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x4CC) |
| 137 | #define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x4D0) /* cmd */ |
| 138 | #define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x4D4) /* cfg */ |
| 139 | #define SDCC1_M (CLK_CTL_BASE + 0x4D8) /* m */ |
| 140 | #define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */ |
| 141 | #define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */ |
| 142 | |
| 143 | /* SDCC2 */ |
| 144 | #define SDCC2_BCR (CLK_CTL_BASE + 0x500) /* block reset */ |
| 145 | #define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x504) /* branch control */ |
| 146 | #define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x508) |
| 147 | #define SDCC2_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x50C) |
| 148 | #define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x510) /* cmd */ |
| 149 | #define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x514) /* cfg */ |
| 150 | #define SDCC2_M (CLK_CTL_BASE + 0x518) /* m */ |
| 151 | #define SDCC2_N (CLK_CTL_BASE + 0x51C) /* n */ |
| 152 | #define SDCC2_D (CLK_CTL_BASE + 0x520) /* d */ |
| 153 | |
| 154 | /* UART |
| 155 | BLSP1_UART[0:5] |
| 156 | BLSP2_UART[0:5] |
| 157 | */ |
| 158 | #define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4) |
| 159 | #define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x944) |
| 160 | |
| 161 | #define BLSP1_UART0_APPS_CBCR (CLK_CTL_BASE + 0x684) |
| 162 | #define BLSP1_UART0_APPS_CMD_RCGR (CLK_CTL_BASE + 0x68C) |
| 163 | #define BLSP1_UART0_APPS_CFG_RCGR (CLK_CTL_BASE + 0x690) |
| 164 | #define BLSP1_UART0_APPS_M (CLK_CTL_BASE + 0x694) |
| 165 | #define BLSP1_UART0_APPS_N (CLK_CTL_BASE + 0x698) |
| 166 | #define BLSP1_UART0_APPS_D (CLK_CTL_BASE + 0x69C) |
| 167 | |
| 168 | #define BLSP1_UART1_APPS_CBCR (CLK_CTL_BASE + 0x704) |
| 169 | #define BLSP1_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0x70C) |
| 170 | #define BLSP1_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0x710) |
| 171 | #define BLSP1_UART1_APPS_M (CLK_CTL_BASE + 0x714) |
| 172 | #define BLSP1_UART1_APPS_N (CLK_CTL_BASE + 0x718) |
| 173 | #define BLSP1_UART1_APPS_D (CLK_CTL_BASE + 0x71C) |
| 174 | |
| 175 | #define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x784) |
| 176 | #define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x78C) |
| 177 | #define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x790) |
| 178 | #define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x794) |
| 179 | #define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x798) |
| 180 | #define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x79C) |
| 181 | |
| 182 | #define BLSP1_UART3_APPS_CBCR (CLK_CTL_BASE + 0x804) |
| 183 | #define BLSP1_UART3_APPS_CMD_RCGR (CLK_CTL_BASE + 0x80C) |
| 184 | #define BLSP1_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0x810) |
| 185 | #define BLSP1_UART3_APPS_M (CLK_CTL_BASE + 0x814) |
| 186 | #define BLSP1_UART3_APPS_N (CLK_CTL_BASE + 0x818) |
| 187 | #define BLSP1_UART3_APPS_D (CLK_CTL_BASE + 0x81C) |
| 188 | |
| 189 | #define BLSP1_UART4_APPS_CBCR (CLK_CTL_BASE + 0x884) |
| 190 | #define BLSP1_UART4_APPS_CMD_RCGR (CLK_CTL_BASE + 0x88C) |
| 191 | #define BLSP1_UART4_APPS_CFG_RCGR (CLK_CTL_BASE + 0x890) |
| 192 | #define BLSP1_UART4_APPS_M (CLK_CTL_BASE + 0x894) |
| 193 | #define BLSP1_UART4_APPS_N (CLK_CTL_BASE + 0x898) |
| 194 | #define BLSP1_UART4_APPS_D (CLK_CTL_BASE + 0x89C) |
| 195 | |
| 196 | #define BLSP1_UART5_APPS_CBCR (CLK_CTL_BASE + 0x904) |
| 197 | #define BLSP1_UART5_APPS_CMD_RCGR (CLK_CTL_BASE + 0x90C) |
| 198 | #define BLSP1_UART5_APPS_CFG_RCGR (CLK_CTL_BASE + 0x910) |
| 199 | #define BLSP1_UART5_APPS_M (CLK_CTL_BASE + 0x914) |
| 200 | #define BLSP1_UART5_APPS_N (CLK_CTL_BASE + 0x918) |
| 201 | #define BLSP1_UART5_APPS_D (CLK_CTL_BASE + 0x91C) |
| 202 | |
| 203 | #define BLSP2_UART0_APPS_CBCR (CLK_CTL_BASE + 0x9C4) |
| 204 | #define BLSP2_UART0_APPS_CMD_RCGR (CLK_CTL_BASE + 0x9CC) |
| 205 | #define BLSP2_UART0_APPS_CFG_RCGR (CLK_CTL_BASE + 0x9D0) |
| 206 | #define BLSP2_UART0_APPS_M (CLK_CTL_BASE + 0x9D4) |
| 207 | #define BLSP2_UART0_APPS_N (CLK_CTL_BASE + 0x9D8) |
| 208 | #define BLSP2_UART0_APPS_D (CLK_CTL_BASE + 0x9DC) |
| 209 | |
| 210 | #define BLSP2_UART1_APPS_CBCR (CLK_CTL_BASE + 0xA44) |
| 211 | #define BLSP2_UART1_APPS_CMD_RCGR (CLK_CTL_BASE + 0xA4C) |
| 212 | #define BLSP2_UART1_APPS_CFG_RCGR (CLK_CTL_BASE + 0xA50) |
| 213 | #define BLSP2_UART1_APPS_M (CLK_CTL_BASE + 0xA54) |
| 214 | #define BLSP2_UART1_APPS_N (CLK_CTL_BASE + 0xA58) |
| 215 | #define BLSP2_UART1_APPS_D (CLK_CTL_BASE + 0xA5C) |
| 216 | |
| 217 | #define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0xAC4) |
| 218 | #define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0xACC) |
| 219 | #define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0xAD0) |
| 220 | #define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0xAD4) |
| 221 | #define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0xAD8) |
| 222 | #define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0xADC) |
| 223 | |
| 224 | #define BLSP2_UART3_APPS_CBCR (CLK_CTL_BASE + 0xB44) |
| 225 | #define BLSP2_UART3_APPS_CMD_RCGR (CLK_CTL_BASE + 0xB4C) |
| 226 | #define BLSP2_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0xB50) |
| 227 | #define BLSP2_UART3_APPS_M (CLK_CTL_BASE + 0xB54) |
| 228 | #define BLSP2_UART3_APPS_N (CLK_CTL_BASE + 0xB58) |
| 229 | #define BLSP2_UART3_APPS_D (CLK_CTL_BASE + 0xB5C) |
| 230 | |
| 231 | #define BLSP2_UART4_APPS_CBCR (CLK_CTL_BASE + 0xBC4) |
| 232 | #define BLSP2_UART4_APPS_CMD_RCGR (CLK_CTL_BASE + 0xBCC) |
| 233 | #define BLSP2_UART4_APPS_CFG_RCGR (CLK_CTL_BASE + 0xBD0) |
| 234 | #define BLSP2_UART4_APPS_M (CLK_CTL_BASE + 0xBD4) |
| 235 | #define BLSP2_UART4_APPS_N (CLK_CTL_BASE + 0xBD8) |
| 236 | #define BLSP2_UART4_APPS_D (CLK_CTL_BASE + 0xBDC) |
| 237 | |
| 238 | #define BLSP2_UART5_APPS_CBCR (CLK_CTL_BASE + 0xC44) |
| 239 | #define BLSP2_UART5_APPS_CMD_RCGR (CLK_CTL_BASE + 0xC4C) |
| 240 | #define BLSP2_UART5_APPS_CFG_RCGR (CLK_CTL_BASE + 0xC50) |
| 241 | #define BLSP2_UART5_APPS_M (CLK_CTL_BASE + 0xC54) |
| 242 | #define BLSP2_UART5_APPS_N (CLK_CTL_BASE + 0xC58) |
| 243 | #define BLSP2_UART5_APPS_D (CLK_CTL_BASE + 0xC5C) |
| 244 | |
| 245 | /* USB */ |
| 246 | #define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484) |
| 247 | #define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x488) |
| 248 | #define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490) |
| 249 | #define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494) |
| 250 | |
| 251 | /* I2C */ |
| 252 | #define BLSP2_QUP5_I2C_APPS_CBCR (CLK_CTL_BASE + 0xB88) |
| 253 | |
| 254 | #define BLSP_QUP_BASE(blsp_id, qup_id) ((blsp_id == 1) ? \ |
| 255 | (PERIPH_SS_BASE + 0x00123000 \ |
| 256 | + (qup_id * 0x1000)) :\ |
| 257 | (PERIPH_SS_BASE + 0x00163000 + \ |
| 258 | (qup_id * 0x1000))) |
| 259 | |
| 260 | /* DRV strength for sdcc */ |
| 261 | #define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002044) |
| 262 | |
| 263 | /* SDHCI */ |
| 264 | #define SDCC_MCI_HC_MODE (0x00000078) |
| 265 | #define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC) |
| 266 | #define SDCC_HC_PWRCTL_MASK_REG (0x000000E0) |
| 267 | #define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4) |
| 268 | #define SDCC_HC_PWRCTL_CTL_REG (0x000000E8) |
| 269 | #endif |