Jeevan Shriram | 89b72f4 | 2015-01-07 16:33:25 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #ifndef _PLATFORM_MSM8916_IOMAP_H_ |
| 30 | #define _PLATFORM_MSM8916_IOMAP_H_ |
| 31 | |
Aparna Mallavarapu | 6b9ee0c | 2014-04-17 13:58:43 +0530 | [diff] [blame] | 32 | #define MSM_IOMAP_BASE 0x00000000 |
| 33 | #define MSM_IOMAP_END 0x08000000 |
| 34 | #define A53_SS_BASE 0x0B000000 |
| 35 | #define A53_SS_END 0x0B200000 |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 36 | |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 37 | #define SYSTEM_IMEM_BASE 0x08600000 |
| 38 | #define MSM_SHARED_IMEM_BASE 0x08600000 |
| 39 | |
| 40 | #define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C) |
| 41 | #define BS_INFO_OFFSET (0x6B0) |
| 42 | #define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET) |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 43 | #define SDRAM_START_ADDR 0x80000000 |
| 44 | |
Aparna Mallavarapu | 961294c | 2014-05-04 19:04:38 +0530 | [diff] [blame] | 45 | #define MSM_SHARED_BASE 0x86300000 |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 46 | #define APPS_SS_BASE 0x0B000000 |
| 47 | |
Aparna Mallavarapu | 324cfbd | 2014-08-12 12:03:48 +0530 | [diff] [blame] | 48 | #define DDR_START get_ddr_start() |
| 49 | #define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000 |
| 50 | #define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000 |
| 51 | #define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2000000 |
| 52 | #define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x1E00000 |
| 53 | |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 54 | #define MSM_GIC_DIST_BASE APPS_SS_BASE |
| 55 | #define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000) |
| 56 | #define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000) |
| 57 | #define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000) |
| 58 | #define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE |
| 59 | |
| 60 | #define PERIPH_SS_BASE 0x07800000 |
| 61 | |
| 62 | #define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000) |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 63 | #define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900) |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 64 | #define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x00064000) |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 65 | #define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900) |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 66 | |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 67 | /* SDHCI */ |
| 68 | #define SDCC_MCI_HC_MODE (0x00000078) |
| 69 | #define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC) |
| 70 | #define SDCC_HC_PWRCTL_MASK_REG (0x000000E0) |
| 71 | #define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4) |
| 72 | #define SDCC_HC_PWRCTL_CTL_REG (0x000000E8) |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 73 | #define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000) |
| 74 | #define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000) |
| 75 | #define MSM_USB_BASE (PERIPH_SS_BASE + 0x000D9000) |
| 76 | |
| 77 | #define CLK_CTL_BASE 0x1800000 |
| 78 | |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 79 | #define SPMI_BASE 0x02000000 |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 80 | #define SPMI_GENI_BASE (SPMI_BASE + 0xA000) |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 81 | #define SPMI_PIC_BASE (SPMI_BASE + 0x01800000) |
Aparna Mallavarapu | 261b06b | 2014-03-28 16:48:23 +0530 | [diff] [blame] | 82 | #define PMIC_ARB_CORE 0x200F000 |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 83 | |
Aparna Mallavarapu | 9d41cd9 | 2014-01-29 21:01:11 +0530 | [diff] [blame] | 84 | #define TLMM_BASE_ADDR 0x1000000 |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 85 | #define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000) |
| 86 | #define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x00000004 + (x)*0x1000) |
vijay kumar | 0c4157f | 2015-03-25 15:53:23 +0530 | [diff] [blame] | 87 | #define GPIO_OUT_SET_ADDR(x) (TLMM_BASE_ADDR + 0x200040 + (x/32)*0x04) |
| 88 | #define GPIO_OUT_CLR_ADDR(x) (TLMM_BASE_ADDR + 0x200020 + (x/32)*0x04) |
| 89 | #define GPIO_OUT_VAL(x) (1 << (x - (x/32)*32)) |
| 90 | #define GPIO_OUT_OE_SET_ADDR(x) (TLMM_BASE_ADDR + 0x2000C0 + (x/32)*0x04) |
| 91 | #define GPIO_OUT_OE_VAL(x) (1 << (x - (x/32)*32)) |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 92 | |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 93 | #define MPM2_MPM_CTRL_BASE 0x004A0000 |
Maria Yu | c6d79d7 | 2014-03-21 10:44:03 +0800 | [diff] [blame] | 94 | #define MPM2_MPM_PS_HOLD 0x004AB000 |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 95 | #define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000 |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 96 | |
Aparna Mallavarapu | 2e89967 | 2014-04-22 15:12:05 +0530 | [diff] [blame] | 97 | /* CRYPTO ENGINE */ |
| 98 | #define MSM_CE1_BASE 0x073A000 |
| 99 | #define MSM_CE1_BAM_BASE 0x0704000 |
| 100 | #define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000) |
| 101 | #define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004) |
| 102 | #define GCC_CRYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008) |
| 103 | #define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C) |
| 104 | #define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020) |
| 105 | #define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024) |
Aparna Mallavarapu | 3f24f3b | 2014-05-15 11:50:37 +0530 | [diff] [blame] | 106 | |
| 107 | /* I2C */ |
| 108 | #define BLSP_QUP_BASE(blsp_id, qup_id) (PERIPH_SS_BASE + 0xB5000 + 0x1000 * qup_id) |
| 109 | #define GCC_BLSP1_QUP2_APPS_CBCR (CLK_CTL_BASE + 0x3010) |
| 110 | #define GCC_BLSP1_QUP2_CFG_RCGR (CLK_CTL_BASE + 0x3018) |
| 111 | #define GCC_BLSP1_QUP2_CMD_RCGR (CLK_CTL_BASE + 0x3014) |
| 112 | |
vijay kumar | 0251c7d | 2015-04-06 19:16:06 +0530 | [diff] [blame] | 113 | #define GCC_BLSP1_QUP4_APPS_CBCR (CLK_CTL_BASE + 0x5020) |
| 114 | #define GCC_BLSP1_QUP4_CFG_RCGR (CLK_CTL_BASE + 0x5004) |
| 115 | #define GCC_BLSP1_QUP4_CMD_RCGR (CLK_CTL_BASE + 0x5000) |
| 116 | |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 117 | /* GPLL */ |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 118 | #define GPLL0_STATUS (CLK_CTL_BASE + 0x2101C) |
Unnati Gandhi | a0bea4c | 2014-06-12 11:09:44 +0530 | [diff] [blame] | 119 | #define GPLL1_STATUS (CLK_CTL_BASE + 0x2001C) |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 120 | #define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000) |
| 121 | #define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004) |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 122 | |
| 123 | /* SDCC */ |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 124 | #define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000) |
| 125 | #define SDCC1_BCR (CLK_CTL_BASE + 0x42000) /* block reset*/ |
| 126 | #define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x42018) /* branch ontrol */ |
| 127 | #define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4201C) |
| 128 | #define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x42004) /* cmd */ |
| 129 | #define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x42008) /* cfg */ |
| 130 | #define SDCC1_M (CLK_CTL_BASE + 0x4200C) /* m */ |
| 131 | #define SDCC1_N (CLK_CTL_BASE + 0x42010) /* n */ |
| 132 | #define SDCC1_D (CLK_CTL_BASE + 0x42014) /* d */ |
| 133 | |
| 134 | #define SDCC2_BCR (CLK_CTL_BASE + 0x43000) /* block reset */ |
| 135 | #define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x43018) /* branch control */ |
| 136 | #define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x4301C) |
| 137 | #define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x43004) /* cmd */ |
| 138 | #define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x43008) /* cfg */ |
| 139 | #define SDCC2_M (CLK_CTL_BASE + 0x4300C) /* m */ |
| 140 | #define SDCC2_N (CLK_CTL_BASE + 0x43010) /* n */ |
| 141 | #define SDCC2_D (CLK_CTL_BASE + 0x43014) /* d */ |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 142 | |
| 143 | /* UART */ |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 144 | #define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008) |
| 145 | #define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C) |
| 146 | #define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034) |
| 147 | #define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038) |
| 148 | #define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x303C) |
| 149 | #define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x3040) |
| 150 | #define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x3044) |
| 151 | |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 152 | |
| 153 | /* USB */ |
Aparna Mallavarapu | 70e5df5 | 2014-02-27 22:51:29 -0800 | [diff] [blame] | 154 | #define USB_HS_BCR (CLK_CTL_BASE + 0x41000) |
| 155 | #define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x41004) |
| 156 | #define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008) |
| 157 | #define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010) |
| 158 | #define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014) |
Padmanabhan Komanduru | 02edbcc | 2014-03-26 18:51:02 +0530 | [diff] [blame] | 159 | |
| 160 | /* MDSS */ |
| 161 | #define MIPI_DSI_BASE (0x1A98000) |
| 162 | #define MIPI_DSI0_BASE MIPI_DSI_BASE |
Vineet Bajaj | e022da6 | 2014-07-24 19:13:34 +0530 | [diff] [blame] | 163 | #define MIPI_DSI1_BASE (0x1AA0000) |
Padmanabhan Komanduru | 0e9a09b | 2014-03-25 19:53:01 +0530 | [diff] [blame] | 164 | #define DSI0_PHY_BASE (0x1A98500) |
Vineet Bajaj | e022da6 | 2014-07-24 19:13:34 +0530 | [diff] [blame] | 165 | #define DSI1_PHY_BASE (0x1AA0500) |
Padmanabhan Komanduru | 0e9a09b | 2014-03-25 19:53:01 +0530 | [diff] [blame] | 166 | #define DSI0_PLL_BASE (0x1A98300) |
| 167 | #define DSI1_PLL_BASE DSI0_PLL_BASE |
Jeevan Shriram | 89b72f4 | 2015-01-07 16:33:25 -0800 | [diff] [blame] | 168 | #define DSI0_REGULATOR_BASE (0x1A98780) |
| 169 | #define DSI1_REGULATOR_BASE DSI0_REGULATOR_BASE |
Padmanabhan Komanduru | 02edbcc | 2014-03-26 18:51:02 +0530 | [diff] [blame] | 170 | #define MDP_BASE (0x1A00000) |
| 171 | #define REG_MDP(off) (MDP_BASE + (off)) |
Padmanabhan Komanduru | 02edbcc | 2014-03-26 18:51:02 +0530 | [diff] [blame] | 172 | #define MDP_HW_REV REG_MDP(0x1000) |
Unnati Gandhi | bd9dbea | 2014-07-17 14:30:29 +0530 | [diff] [blame] | 173 | #define MDP_INTR_EN REG_MDP(0x1010) |
| 174 | #define MDP_INTR_CLEAR REG_MDP(0x1018) |
| 175 | #define MDP_HIST_INTR_EN REG_MDP(0x101C) |
Jayant Shekhar | 299e14b | 2014-05-22 11:26:24 +0530 | [diff] [blame] | 176 | #define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000) |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 177 | #define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000) |
Padmanabhan Komanduru | 02edbcc | 2014-03-26 18:51:02 +0530 | [diff] [blame] | 178 | #define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000) |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 179 | #define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000) |
Jayant Shekhar | 299e14b | 2014-05-22 11:26:24 +0530 | [diff] [blame] | 180 | #define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000) |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 181 | #define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000) |
Padmanabhan Komanduru | 02edbcc | 2014-03-26 18:51:02 +0530 | [diff] [blame] | 182 | #define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000) |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 183 | #define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000) |
Padmanabhan Komanduru | 02edbcc | 2014-03-26 18:51:02 +0530 | [diff] [blame] | 184 | #define MDP_DISP_INTF_SEL REG_MDP(0x1004) |
| 185 | #define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0) |
| 186 | #define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC) |
| 187 | #define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8) |
| 188 | #define MDP_CTL_0_BASE REG_MDP(0x2000) |
| 189 | #define MDP_CTL_1_BASE REG_MDP(0x2200) |
| 190 | #define MDP_CLK_CTRL0 REG_MDP(0x012AC) |
| 191 | #define MDP_CLK_CTRL1 REG_MDP(0x012B4) |
| 192 | #define MDP_CLK_CTRL2 REG_MDP(0x012BC) |
| 193 | #define MDP_CLK_CTRL3 REG_MDP(0x013A8) |
| 194 | #define MDP_CLK_CTRL4 REG_MDP(0x013B0) |
| 195 | #define MDP_CLK_CTRL5 REG_MDP(0x013B8) |
| 196 | |
Vineet Bajaj | e022da6 | 2014-07-24 19:13:34 +0530 | [diff] [blame] | 197 | #define MDP_INTF_0_BASE REG_MDP(0x11F00) |
| 198 | #define MDP_INTF_1_BASE REG_MDP(0x12700) |
| 199 | #define MDP_INTF_2_BASE REG_MDP(0x12F00) |
| 200 | |
| 201 | #define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12f4) |
| 202 | #define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8) |
| 203 | #define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0) |
| 204 | |
| 205 | #define MDP_REG_PPB0_CNTL REG_MDP(0x1420) |
| 206 | #define MDP_REG_PPB0_CONFIG REG_MDP(0x1424) |
| 207 | |
Padmanabhan Komanduru | 02edbcc | 2014-03-26 18:51:02 +0530 | [diff] [blame] | 208 | #define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080) |
| 209 | #define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130) |
| 210 | |
| 211 | #define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0) |
| 212 | |
| 213 | #define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004) |
| 214 | #define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8) |
| 215 | #define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xc80F0) |
| 216 | #define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xc8124) |
| 217 | #define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xc8160) |
| 218 | #define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xc8164) |
| 219 | #define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xc8178) |
| 220 | #define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xc817C) |
| 221 | #define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xc80B0) |
| 222 | #define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xc80B4) |
| 223 | #define VBIF_VBIF_IN_RD_LIM_CONF2 REG_MDP(0xc80B8) |
| 224 | #define VBIF_VBIF_IN_RD_LIM_CONF3 REG_MDP(0xc80BC) |
| 225 | #define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xc80C0) |
| 226 | #define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xc80C4) |
| 227 | #define VBIF_VBIF_IN_WR_LIM_CONF2 REG_MDP(0xc80C8) |
| 228 | #define VBIF_VBIF_IN_WR_LIM_CONF3 REG_MDP(0xc80CC) |
| 229 | #define VBIF_VBIF_ABIT_SHORT REG_MDP(0xc8070) |
| 230 | #define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0xc8074) |
| 231 | #define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0xc80A8) |
| 232 | |
vijay kumar | 98f455d | 2014-10-22 17:59:30 +0530 | [diff] [blame] | 233 | #define MDSS_MDP_REG_PP_FBC_MODE 0x034 |
| 234 | #define MDSS_MDP_REG_PP_FBC_BUDGET_CTL 0x038 |
| 235 | #define MDSS_MDP_REG_PP_FBC_LOSSY_MODE 0x03C |
| 236 | |
Padmanabhan Komanduru | 02edbcc | 2014-03-26 18:51:02 +0530 | [diff] [blame] | 237 | #define SOFT_RESET 0x118 |
| 238 | #define CLK_CTRL 0x11C |
| 239 | #define TRIG_CTRL 0x084 |
| 240 | #define CTRL 0x004 |
| 241 | #define COMMAND_MODE_DMA_CTRL 0x03C |
| 242 | #define COMMAND_MODE_MDP_CTRL 0x040 |
| 243 | #define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044 |
| 244 | #define COMMAND_MODE_MDP_STREAM0_CTRL 0x058 |
| 245 | #define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C |
| 246 | #define COMMAND_MODE_MDP_STREAM1_CTRL 0x060 |
| 247 | #define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064 |
| 248 | #define ERR_INT_MASK0 0x10C |
| 249 | |
Ray Zhang | d1cd085 | 2015-01-20 15:31:33 +0800 | [diff] [blame] | 250 | #define LANE_CTL 0x0AC |
Padmanabhan Komanduru | 02edbcc | 2014-03-26 18:51:02 +0530 | [diff] [blame] | 251 | #define LANE_SWAP_CTL 0x0B0 |
| 252 | #define TIMING_CTL 0x0C4 |
| 253 | |
| 254 | #define VIDEO_MODE_ACTIVE_H 0x024 |
| 255 | #define VIDEO_MODE_ACTIVE_V 0x028 |
| 256 | #define VIDEO_MODE_TOTAL 0x02C |
| 257 | #define VIDEO_MODE_HSYNC 0x030 |
| 258 | #define VIDEO_MODE_VSYNC 0x034 |
| 259 | #define VIDEO_MODE_VSYNC_VPOS 0x038 |
| 260 | |
| 261 | #define DMA_CMD_OFFSET 0x048 |
| 262 | #define DMA_CMD_LENGTH 0x04C |
| 263 | |
| 264 | #define INT_CTRL 0x110 |
| 265 | #define CMD_MODE_DMA_SW_TRIGGER 0x090 |
| 266 | |
| 267 | #define EOT_PACKET_CTRL 0x0CC |
| 268 | #define MISR_CMD_CTRL 0x0A0 |
| 269 | #define MISR_VIDEO_CTRL 0x0A4 |
| 270 | #define VIDEO_MODE_CTRL 0x010 |
| 271 | #define HS_TIMER_CTRL 0x0BC |
| 272 | |
Aparna Mallavarapu | de688ea | 2014-05-12 17:26:11 +0530 | [diff] [blame] | 273 | #define TCSR_TZ_WONCE 0x193D000 |
Aparna Mallavarapu | ec8b7cf | 2014-12-11 12:14:54 +0530 | [diff] [blame] | 274 | #define TCSR_BOOT_MISC_DETECT 0x193D100 |
Aparna Mallavarapu | 9e01437 | 2013-10-19 15:04:58 +0530 | [diff] [blame] | 275 | #endif |