Blame - platform/msm_shared/hdmi_pll_20nm.c - kernel/lk

Casey Piper

68b7e94

2015-03-20 15:56:16 -0700

[diff] [blame]

1

2

*

3

* Redistribution and use in source and binary forms, with or without

4

* modification, are permitted provided that the following conditions

5

* are met:

6

* * Redistributions of source code must retain the above copyright

7

* notice, this list of conditions and the following disclaimer.

8

* * Redistributions in binary form must reproduce the above copyright

9

* notice, this list of conditions and the following disclaimer in

10

* the documentation and/or other materials provided with the

11

* distribution.

12

* * Neither the name of The Linux Foundation nor the names of its

13

* contributors may be used to endorse or promote products derived

14

* from this software without specific prior written permission.

15

*

16

* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

17

* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

18

* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

19

* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

20

* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

21

* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

22

* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS

23

* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED

24

* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

25

* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT

26

* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF

* SUCH DAMAGE.

*/

#include <debug.h>

#include <err.h>

#include <reg.h>

#include <smem.h>

#include <bits.h>

#include <msm_panel.h>

36

#include <platform/timer.h>

37

#include <platform/iomap.h>

38

39

40

#define HDMI_PHY_CMD_SIZE 68

41

#define HDMI_PHY_CLK_SIZE 97

42

43

#define HDMI_PHY_BASE 0xFD9A9200

44

#define HDMI_PLL_BASE 0xFD9A8600

45

46

/* hdmi phy registers */

47

enum {

48

CALC_QSERDES_COM_SYSCLK_EN_SEL_TXBAND = 0,

49

CALC_QSERDES_COM_DIV_REF1,

50

CALC_QSERDES_COM_DIV_REF2,

51

CALC_QSERDES_COM_KVCO_COUNT1,

52

CALC_QSERDES_COM_KVCO_COUNT2,

53

CALC_QSERDES_COM_KVCO_CAL_CNTRL,

54

CALC_QSERDES_COM_KVCO_CODE,

55

CALC_QSERDES_COM_VREF_CFG3,

56

CALC_QSERDES_COM_VREF_CFG4,

57

CALC_QSERDES_COM_VREF_CFG5,

58

CALC_QSERDES_COM_PLL_IP_SETI,

59

CALC_QSERDES_COM_PLL_CP_SETI,

60

CALC_QSERDES_COM_PLL_IP_SETP,

61

CALC_QSERDES_COM_PLL_CP_SETP,

62

CALC_QSERDES_COM_PLL_CRCTRL,

63

CALC_QSERDES_COM_DIV_FRAC_START1,

64

CALC_QSERDES_COM_DIV_FRAC_START2,

65

CALC_QSERDES_COM_DIV_FRAC_START3,

66

CALC_QSERDES_COM_DEC_START1,

67

CALC_QSERDES_COM_DEC_START2,

68

CALC_QSERDES_COM_PLLLOCK_CMP1,

69

CALC_QSERDES_COM_PLLLOCK_CMP2,

70

CALC_QSERDES_COM_PLLLOCK_CMP3,

71

CALC_QSERDES_COM_PLLLOCK_CMP_EN,

72

CALC_QSERDES_COM_RESETSM_CNTRL,

CALC_HDMI_PHY_MODE,

CALC_MAX

};

/* Set to 1 for auto KVCO cal; set to 0 for fixed value */

78

#define HDMI_PHY_AUTO_KVCO_CAL 1

79

80

/* PLL REGISTERS */

81

#define QSERDES_COM_SYS_CLK_CTRL (0x000)

82

#define QSERDES_COM_PLL_VCOTAIL_EN (0x004)

83

#define QSERDES_COM_CMN_MODE (0x008)

84

#define QSERDES_COM_IE_TRIM (0x00C)

85

#define QSERDES_COM_IP_TRIM (0x010)

86

#define QSERDES_COM_PLL_CNTRL (0x014)

87

#define QSERDES_COM_PLL_PHSEL_CONTROL (0x018)

88

#define QSERDES_COM_IPTAT_TRIM_VCCA_TX_SEL (0x01C)

89

#define QSERDES_COM_PLL_PHSEL_DC (0x020)

90

#define QSERDES_COM_PLL_IP_SETI (0x024)

91

#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL (0x028)

92

#define QSERDES_COM_PLL_BKG_KVCO_CAL_EN (0x02C)

93

#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN (0x030)

94

#define QSERDES_COM_PLL_CP_SETI (0x034)

95

#define QSERDES_COM_PLL_IP_SETP (0x038)

96

#define QSERDES_COM_PLL_CP_SETP (0x03C)

97

#define QSERDES_COM_ATB_SEL1 (0x040)

98

#define QSERDES_COM_ATB_SEL2 (0x044)

99

#define QSERDES_COM_SYSCLK_EN_SEL_TXBAND (0x048)

100

#define QSERDES_COM_RESETSM_CNTRL (0x04C)

101

#define QSERDES_COM_RESETSM_CNTRL2 (0x050)

102

#define QSERDES_COM_RESETSM_CNTRL3 (0x054)

103

#define QSERDES_COM_RESETSM_PLL_CAL_COUNT1 (0x058)

104

#define QSERDES_COM_RESETSM_PLL_CAL_COUNT2 (0x05C)

105

#define QSERDES_COM_DIV_REF1 (0x060)

106

#define QSERDES_COM_DIV_REF2 (0x064)

107

#define QSERDES_COM_KVCO_COUNT1 (0x068)

108

#define QSERDES_COM_KVCO_COUNT2 (0x06C)

109

#define QSERDES_COM_KVCO_CAL_CNTRL (0x070)

110

#define QSERDES_COM_KVCO_CODE (0x074)

111

#define QSERDES_COM_VREF_CFG1 (0x078)

112

#define QSERDES_COM_VREF_CFG2 (0x07C)

113

#define QSERDES_COM_VREF_CFG3 (0x080)

114

#define QSERDES_COM_VREF_CFG4 (0x084)

115

#define QSERDES_COM_VREF_CFG5 (0x088)

116

#define QSERDES_COM_VREF_CFG6 (0x08C)

117

#define QSERDES_COM_PLLLOCK_CMP1 (0x090)

118

#define QSERDES_COM_PLLLOCK_CMP2 (0x094)

119

#define QSERDES_COM_PLLLOCK_CMP3 (0x098)

120

#define QSERDES_COM_PLLLOCK_CMP_EN (0x09C)

121

#define QSERDES_COM_BGTC (0x0A0)

122

#define QSERDES_COM_PLL_TEST_UPDN (0x0A4)

123

#define QSERDES_COM_PLL_VCO_TUNE (0x0A8)

124

#define QSERDES_COM_DEC_START1 (0x0AC)

125

#define QSERDES_COM_PLL_AMP_OS (0x0B0)

126

#define QSERDES_COM_SSC_EN_CENTER (0x0B4)

127

#define QSERDES_COM_SSC_ADJ_PER1 (0x0B8)

128

#define QSERDES_COM_SSC_ADJ_PER2 (0x0BC)

129

#define QSERDES_COM_SSC_PER1 (0x0C0)

130

#define QSERDES_COM_SSC_PER2 (0x0C4)

131

#define QSERDES_COM_SSC_STEP_SIZE1 (0x0C8)

132

#define QSERDES_COM_SSC_STEP_SIZE2 (0x0CC)

133

#define QSERDES_COM_RES_CODE_UP (0x0D0)

134

#define QSERDES_COM_RES_CODE_DN (0x0D4)

135

#define QSERDES_COM_RES_CODE_UP_OFFSET (0x0D8)

136

#define QSERDES_COM_RES_CODE_DN_OFFSET (0x0DC)

137

#define QSERDES_COM_RES_CODE_START_SEG1 (0x0E0)

138

#define QSERDES_COM_RES_CODE_START_SEG2 (0x0E4)

139

#define QSERDES_COM_RES_CODE_CAL_CSR (0x0E8)

140

#define QSERDES_COM_RES_CODE (0x0EC)

141

#define QSERDES_COM_RES_TRIM_CONTROL (0x0F0)

142

#define QSERDES_COM_RES_TRIM_CONTROL2 (0x0F4)

143

#define QSERDES_COM_RES_TRIM_EN_VCOCALDONE (0x0F8)

144

#define QSERDES_COM_FAUX_EN (0x0FC)

145

#define QSERDES_COM_DIV_FRAC_START1 (0x100)

146

#define QSERDES_COM_DIV_FRAC_START2 (0x104)

147

#define QSERDES_COM_DIV_FRAC_START3 (0x108)

148

#define QSERDES_COM_DEC_START2 (0x10C)

149

#define QSERDES_COM_PLL_RXTXEPCLK_EN (0x110)

150

#define QSERDES_COM_PLL_CRCTRL (0x114)

151

#define QSERDES_COM_PLL_CLKEPDIV (0x118)

152

#define QSERDES_COM_PLL_FREQUPDATE (0x11C)

153

#define QSERDES_COM_PLL_BKGCAL_TRIM_UP (0x120)

154

#define QSERDES_COM_PLL_BKGCAL_TRIM_DN (0x124)

155

#define QSERDES_COM_PLL_BKGCAL_TRIM_MUX (0x128)

156

#define QSERDES_COM_PLL_BKGCAL_VREF_CFG (0x12C)

157

#define QSERDES_COM_PLL_BKGCAL_DIV_REF1 (0x130)

158

#define QSERDES_COM_PLL_BKGCAL_DIV_REF2 (0x134)

159

#define QSERDES_COM_MUXADDR (0x138)

160

#define QSERDES_COM_LOW_POWER_RO_CONTROL (0x13C)

161

#define QSERDES_COM_POST_DIVIDER_CONTROL (0x140)

162

#define QSERDES_COM_HR_OCLK2_DIVIDER (0x144)

163

#define QSERDES_COM_HR_OCLK3_DIVIDER (0x148)

164

#define QSERDES_COM_PLL_VCO_HIGH (0x14C)

165

#define QSERDES_COM_RESET_SM (0x150)

166

#define QSERDES_COM_MUXVAL (0x154)

167

#define QSERDES_COM_CORE_RES_CODE_DN (0x158)

168

#define QSERDES_COM_CORE_RES_CODE_UP (0x15C)

169

#define QSERDES_COM_CORE_VCO_TUNE (0x160)

170

#define QSERDES_COM_CORE_VCO_TAIL (0x164)

171

#define QSERDES_COM_CORE_KVCO_CODE (0x168)

172

173

/* Tx Channel 0 REGISTERS */

174

#define QSERDES_TX_L0_BIST_MODE_LANENO (0x00)

175

#define QSERDES_TX_L0_CLKBUF_ENABLE (0x04)

176

#define QSERDES_TX_L0_TX_EMP_POST1_LVL (0x08)

177

#define QSERDES_TX_L0_TX_DRV_LVL (0x0C)

178

#define QSERDES_TX_L0_RESET_TSYNC_EN (0x10)

179

#define QSERDES_TX_L0_LPB_EN (0x14)

180

#define QSERDES_TX_L0_RES_CODE_UP (0x18)

181

#define QSERDES_TX_L0_RES_CODE_DN (0x1C)

182

#define QSERDES_TX_L0_PERL_LENGTH1 (0x20)

183

#define QSERDES_TX_L0_PERL_LENGTH2 (0x24)

184

#define QSERDES_TX_L0_SERDES_BYP_EN_OUT (0x28)

185

#define QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN (0x2C)

186

#define QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN (0x30)

187

#define QSERDES_TX_L0_BIST_PATTERN1 (0x34)

188

#define QSERDES_TX_L0_BIST_PATTERN2 (0x38)

189

#define QSERDES_TX_L0_BIST_PATTERN3 (0x3C)

190

#define QSERDES_TX_L0_BIST_PATTERN4 (0x40)

191

#define QSERDES_TX_L0_BIST_PATTERN5 (0x44)

192

#define QSERDES_TX_L0_BIST_PATTERN6 (0x48)

193

#define QSERDES_TX_L0_BIST_PATTERN7 (0x4C)

194

#define QSERDES_TX_L0_BIST_PATTERN8 (0x50)

195

#define QSERDES_TX_L0_LANE_MODE (0x54)

196

#define QSERDES_TX_L0_IDAC_CAL_LANE_MODE (0x58)

197

#define QSERDES_TX_L0_IDAC_CAL_LANE_MODE_CONFIGURATION (0x5C)

198

#define QSERDES_TX_L0_ATB_SEL1 (0x60)

199

#define QSERDES_TX_L0_ATB_SEL2 (0x64)

200

#define QSERDES_TX_L0_RCV_DETECT_LVL (0x68)

201

#define QSERDES_TX_L0_PRBS_SEED1 (0x6C)

202

#define QSERDES_TX_L0_PRBS_SEED2 (0x70)

203

#define QSERDES_TX_L0_PRBS_SEED3 (0x74)

204

#define QSERDES_TX_L0_PRBS_SEED4 (0x78)

205

#define QSERDES_TX_L0_RESET_GEN (0x7C)

206

#define QSERDES_TX_L0_TRAN_DRVR_EMP_EN (0x80)

207

#define QSERDES_TX_L0_TX_INTERFACE_MODE (0x84)

208

#define QSERDES_TX_L0_PWM_CTRL (0x88)

209

#define QSERDES_TX_L0_PWM_DATA (0x8C)

210

#define QSERDES_TX_L0_PWM_ENC_DIV_CTRL (0x90)

211

#define QSERDES_TX_L0_VMODE_CTRL1 (0x94)

212

#define QSERDES_TX_L0_VMODE_CTRL2 (0x98)

213

#define QSERDES_TX_L0_VMODE_CTRL3 (0x9C)

214

#define QSERDES_TX_L0_VMODE_CTRL4 (0xA0)

215

#define QSERDES_TX_L0_VMODE_CTRL5 (0xA4)

216

#define QSERDES_TX_L0_VMODE_CTRL6 (0xA8)

217

#define QSERDES_TX_L0_VMODE_CTRL7 (0xAC)

218

#define QSERDES_TX_L0_TX_ALOG_INTF_OBSV_CNTL (0xB0)

219

#define QSERDES_TX_L0_BIST_STATUS (0xB4)

220

#define QSERDES_TX_L0_BIST_ERROR_COUNT1 (0xB8)

221

#define QSERDES_TX_L0_BIST_ERROR_COUNT2 (0xBC)

222

#define QSERDES_TX_L0_TX_ALOG_INTF_OBSV (0xC0)

223

#define QSERDES_TX_L0_PWM_DEC_STATUS (0xC4)

224

225

/* Tx Channel 1 REGISTERS */

226

#define QSERDES_TX_L1_BIST_MODE_LANENO (0x00)

227

#define QSERDES_TX_L1_CLKBUF_ENABLE (0x04)

228

#define QSERDES_TX_L1_TX_EMP_POST1_LVL (0x08)

229

#define QSERDES_TX_L1_TX_DRV_LVL (0x0C)

230

#define QSERDES_TX_L1_RESET_TSYNC_EN (0x10)

231

#define QSERDES_TX_L1_LPB_EN (0x14)

232

#define QSERDES_TX_L1_RES_CODE_UP (0x18)

233

#define QSERDES_TX_L1_RES_CODE_DN (0x1C)

234

#define QSERDES_TX_L1_PERL_LENGTH1 (0x20)

235

#define QSERDES_TX_L1_PERL_LENGTH2 (0x24)

236

#define QSERDES_TX_L1_SERDES_BYP_EN_OUT (0x28)

237

#define QSERDES_TX_L1_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN (0x2C)

238

#define QSERDES_TX_L1_PARRATE_REC_DETECT_IDLE_EN (0x30)

239

#define QSERDES_TX_L1_BIST_PATTERN1 (0x34)

240

#define QSERDES_TX_L1_BIST_PATTERN2 (0x38)

241

#define QSERDES_TX_L1_BIST_PATTERN3 (0x3C)

242

#define QSERDES_TX_L1_BIST_PATTERN4 (0x40)

243

#define QSERDES_TX_L1_BIST_PATTERN5 (0x44)

244

#define QSERDES_TX_L1_BIST_PATTERN6 (0x48)

245

#define QSERDES_TX_L1_BIST_PATTERN7 (0x4C)

246

#define QSERDES_TX_L1_BIST_PATTERN8 (0x50)

247

#define QSERDES_TX_L1_LANE_MODE (0x54)

248

#define QSERDES_TX_L1_IDAC_CAL_LANE_MODE (0x58)

249

#define QSERDES_TX_L1_IDAC_CAL_LANE_MODE_CONFIGURATION (0x5C)

250

#define QSERDES_TX_L1_ATB_SEL1 (0x60)

251

#define QSERDES_TX_L1_ATB_SEL2 (0x64)

252

#define QSERDES_TX_L1_RCV_DETECT_LVL (0x68)

253

#define QSERDES_TX_L1_PRBS_SEED1 (0x6C)

254

#define QSERDES_TX_L1_PRBS_SEED2 (0x70)

255

#define QSERDES_TX_L1_PRBS_SEED3 (0x74)

256

#define QSERDES_TX_L1_PRBS_SEED4 (0x78)

257

#define QSERDES_TX_L1_RESET_GEN (0x7C)

258

#define QSERDES_TX_L1_TRAN_DRVR_EMP_EN (0x80)

259

#define QSERDES_TX_L1_TX_INTERFACE_MODE (0x84)

260

#define QSERDES_TX_L1_PWM_CTRL (0x88)

261

#define QSERDES_TX_L1_PWM_DATA (0x8C)

262

#define QSERDES_TX_L1_PWM_ENC_DIV_CTRL (0x90)

263

#define QSERDES_TX_L1_VMODE_CTRL1 (0x94)

264

#define QSERDES_TX_L1_VMODE_CTRL2 (0x98)

265

#define QSERDES_TX_L1_VMODE_CTRL3 (0x9C)

266

#define QSERDES_TX_L1_VMODE_CTRL4 (0xA0)

267

#define QSERDES_TX_L1_VMODE_CTRL5 (0xA4)

268

#define QSERDES_TX_L1_VMODE_CTRL6 (0xA8)

269

#define QSERDES_TX_L1_VMODE_CTRL7 (0xAC)

270

#define QSERDES_TX_L1_TX_ALOG_INTF_OBSV_CNTL (0xB0)

271

#define QSERDES_TX_L1_BIST_STATUS (0xB4)

272

#define QSERDES_TX_L1_BIST_ERROR_COUNT1 (0xB8)

273

#define QSERDES_TX_L1_BIST_ERROR_COUNT2 (0xBC)

274

#define QSERDES_TX_L1_TX_ALOG_INTF_OBSV (0xC0)

275

#define QSERDES_TX_L1_PWM_DEC_STATUS (0xC4)

276

277

/* Tx Channel 2 REGISERS */

278

#define QSERDES_TX_L2_BIST_MODE_LANENO (0x00)

279

#define QSERDES_TX_L2_CLKBUF_ENABLE (0x04)

280

#define QSERDES_TX_L2_TX_EMP_POST1_LVL (0x08)

281

#define QSERDES_TX_L2_TX_DRV_LVL (0x0C)

282

#define QSERDES_TX_L2_RESET_TSYNC_EN (0x10)

283

#define QSERDES_TX_L2_LPB_EN (0x14)

284

#define QSERDES_TX_L2_RES_CODE_UP (0x18)

285

#define QSERDES_TX_L2_RES_CODE_DN (0x1C)

286

#define QSERDES_TX_L2_PERL_LENGTH1 (0x20)

287

#define QSERDES_TX_L2_PERL_LENGTH2 (0x24)

288

#define QSERDES_TX_L2_SERDES_BYP_EN_OUT (0x28)

289

#define QSERDES_TX_L2_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN (0x2C)

290

#define QSERDES_TX_L2_PARRATE_REC_DETECT_IDLE_EN (0x30)

291

#define QSERDES_TX_L2_BIST_PATTERN1 (0x34)

292

#define QSERDES_TX_L2_BIST_PATTERN2 (0x38)

293

#define QSERDES_TX_L2_BIST_PATTERN3 (0x3C)

294

#define QSERDES_TX_L2_BIST_PATTERN4 (0x40)

295

#define QSERDES_TX_L2_BIST_PATTERN5 (0x44)

296

#define QSERDES_TX_L2_BIST_PATTERN6 (0x48)

297

#define QSERDES_TX_L2_BIST_PATTERN7 (0x4C)

298

#define QSERDES_TX_L2_BIST_PATTERN8 (0x50)

299

#define QSERDES_TX_L2_LANE_MODE (0x54)

300

#define QSERDES_TX_L2_IDAC_CAL_LANE_MODE (0x58)

301

#define QSERDES_TX_L2_IDAC_CAL_LANE_MODE_CONFIGURATION (0x5C)

302

#define QSERDES_TX_L2_ATB_SEL1 (0x60)

303

#define QSERDES_TX_L2_ATB_SEL2 (0x64)

304

#define QSERDES_TX_L2_RCV_DETECT_LVL (0x68)

305

#define QSERDES_TX_L2_PRBS_SEED1 (0x6C)

306

#define QSERDES_TX_L2_PRBS_SEED2 (0x70)

307

#define QSERDES_TX_L2_PRBS_SEED3 (0x74)

308

#define QSERDES_TX_L2_PRBS_SEED4 (0x78)

309

#define QSERDES_TX_L2_RESET_GEN (0x7C)

310

#define QSERDES_TX_L2_TRAN_DRVR_EMP_EN (0x80)

311

#define QSERDES_TX_L2_TX_INTERFACE_MODE (0x84)

312

#define QSERDES_TX_L2_PWM_CTRL (0x88)

313

#define QSERDES_TX_L2_PWM_DATA (0x8C)

314

#define QSERDES_TX_L2_PWM_ENC_DIV_CTRL (0x90)

315

#define QSERDES_TX_L2_VMODE_CTRL1 (0x94)

316

#define QSERDES_TX_L2_VMODE_CTRL2 (0x98)

317

#define QSERDES_TX_L2_VMODE_CTRL3 (0x9C)

318

#define QSERDES_TX_L2_VMODE_CTRL4 (0xA0)

319

#define QSERDES_TX_L2_VMODE_CTRL5 (0xA4)

320

#define QSERDES_TX_L2_VMODE_CTRL6 (0xA8)

321

#define QSERDES_TX_L2_VMODE_CTRL7 (0xAC)

322

#define QSERDES_TX_L2_TX_ALOG_INTF_OBSV_CNTL (0xB0)

323

#define QSERDES_TX_L2_BIST_STATUS (0xB4)

324

#define QSERDES_TX_L2_BIST_ERROR_COUNT1 (0xB8)

325

#define QSERDES_TX_L2_BIST_ERROR_COUNT2 (0xBC)

326

#define QSERDES_TX_L2_TX_ALOG_INTF_OBSV (0xC0)

327

#define QSERDES_TX_L2_PWM_DEC_STATUS (0xC4)

328

329

/* Tx Channel 3 REGISERS */

330

#define QSERDES_TX_L3_BIST_MODE_LANENO (0x00)

331

#define QSERDES_TX_L3_CLKBUF_ENABLE (0x04)

332

#define QSERDES_TX_L3_TX_EMP_POST1_LVL (0x08)

333

#define QSERDES_TX_L3_TX_DRV_LVL (0x0C)

334

#define QSERDES_TX_L3_RESET_TSYNC_EN (0x10)

335

#define QSERDES_TX_L3_LPB_EN (0x14)

336

#define QSERDES_TX_L3_RES_CODE_UP (0x18)

337

#define QSERDES_TX_L3_RES_CODE_DN (0x1C)

338

#define QSERDES_TX_L3_PERL_LENGTH1 (0x20)

339

#define QSERDES_TX_L3_PERL_LENGTH2 (0x24)

340

#define QSERDES_TX_L3_SERDES_BYP_EN_OUT (0x28)

341

#define QSERDES_TX_L3_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN (0x2C)

342

#define QSERDES_TX_L3_PARRATE_REC_DETECT_IDLE_EN (0x30)

343

#define QSERDES_TX_L3_BIST_PATTERN1 (0x34)

344

#define QSERDES_TX_L3_BIST_PATTERN2 (0x38)

345

#define QSERDES_TX_L3_BIST_PATTERN3 (0x3C)

346

#define QSERDES_TX_L3_BIST_PATTERN4 (0x40)

347

#define QSERDES_TX_L3_BIST_PATTERN5 (0x44)

348

#define QSERDES_TX_L3_BIST_PATTERN6 (0x48)

349

#define QSERDES_TX_L3_BIST_PATTERN7 (0x4C)

350

#define QSERDES_TX_L3_BIST_PATTERN8 (0x50)

351

#define QSERDES_TX_L3_LANE_MODE (0x54)

352

#define QSERDES_TX_L3_IDAC_CAL_LANE_MODE (0x58)

353

#define QSERDES_TX_L3_IDAC_CAL_LANE_MODE_CONFIGURATION (0x5C)

354

#define QSERDES_TX_L3_ATB_SEL1 (0x60)

355

#define QSERDES_TX_L3_ATB_SEL2 (0x64)

356

#define QSERDES_TX_L3_RCV_DETECT_LVL (0x68)

357

#define QSERDES_TX_L3_PRBS_SEED1 (0x6C)

358

#define QSERDES_TX_L3_PRBS_SEED2 (0x70)

359

#define QSERDES_TX_L3_PRBS_SEED3 (0x74)

360

#define QSERDES_TX_L3_PRBS_SEED4 (0x78)

361

#define QSERDES_TX_L3_RESET_GEN (0x7C)

362

#define QSERDES_TX_L3_TRAN_DRVR_EMP_EN (0x80)

363

#define QSERDES_TX_L3_TX_INTERFACE_MODE (0x84)

364

#define QSERDES_TX_L3_PWM_CTRL (0x88)

365

#define QSERDES_TX_L3_PWM_DATA (0x8C)

366

#define QSERDES_TX_L3_PWM_ENC_DIV_CTRL (0x90)

367

#define QSERDES_TX_L3_VMODE_CTRL1 (0x94)

368

#define QSERDES_TX_L3_VMODE_CTRL2 (0x98)

369

#define QSERDES_TX_L3_VMODE_CTRL3 (0x9C)

370

#define QSERDES_TX_L3_VMODE_CTRL4 (0xA0)

371

#define QSERDES_TX_L3_VMODE_CTRL5 (0xA4)

372

#define QSERDES_TX_L3_VMODE_CTRL6 (0xA8)

373

#define QSERDES_TX_L3_VMODE_CTRL7 (0xAC)

374

#define QSERDES_TX_L3_TX_ALOG_INTF_OBSV_CNTL (0xB0)

375

#define QSERDES_TX_L3_BIST_STATUS (0xB4)

376

#define QSERDES_TX_L3_BIST_ERROR_COUNT1 (0xB8)

377

#define QSERDES_TX_L3_BIST_ERROR_COUNT2 (0xBC)

378

#define QSERDES_TX_L3_TX_ALOG_INTF_OBSV (0xC0)

379

#define QSERDES_TX_L3_PWM_DEC_STATUS (0xC4)

380

381

/* HDMI PHY REGISTERS */

382

#define HDMI_PHY_CFG (0x00)

383

#define HDMI_PHY_PD_CTL (0x04)

384

#define HDMI_PHY_MODE (0x08)

385

#define HDMI_PHY_MISR_CLEAR (0x0C)

386

#define HDMI_PHY_TX0_TX1_BIST_CFG0 (0x10)

387

#define HDMI_PHY_TX0_TX1_BIST_CFG1 (0x14)

388

#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE0 (0x18)

389

#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE1 (0x1C)

390

#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE2 (0x20)

391

#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE3 (0x24)

392

#define HDMI_PHY_TX0_TX1_PRBS_POLY_BYTE0 (0x28)

393

#define HDMI_PHY_TX0_TX1_PRBS_POLY_BYTE1 (0x2C)

394

#define HDMI_PHY_TX0_TX1_PRBS_POLY_BYTE2 (0x30)

395

#define HDMI_PHY_TX0_TX1_PRBS_POLY_BYTE3 (0x34)

396

#define HDMI_PHY_TX2_TX3_BIST_CFG0 (0x38)

397

#define HDMI_PHY_TX2_TX3_BIST_CFG1 (0x3C)

398

#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE0 (0x40)

399

#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE1 (0x44)

400

#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE2 (0x48)

401

#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE3 (0x4C)

402

#define HDMI_PHY_TX2_TX3_PRBS_POLY_BYTE0 (0x50)

403

#define HDMI_PHY_TX2_TX3_PRBS_POLY_BYTE1 (0x54)

404

#define HDMI_PHY_TX2_TX3_PRBS_POLY_BYTE2 (0x58)

405

#define HDMI_PHY_TX2_TX3_PRBS_POLY_BYTE3 (0x5C)

406

#define HDMI_PHY_DEBUG_BUS_SEL (0x60)

407

#define HDMI_PHY_TXCAL_CFG0 (0x64)

408

#define HDMI_PHY_TXCAL_CFG1 (0x68)

409

#define HDMI_PHY_TX0_TX1_BIST_STATUS0 (0x6C)

410

#define HDMI_PHY_TX0_TX1_BIST_STATUS1 (0x70)

411

#define HDMI_PHY_TX0_TX1_BIST_STATUS2 (0x74)

412

#define HDMI_PHY_TX2_TX3_BIST_STATUS0 (0x78)

413

#define HDMI_PHY_TX2_TX3_BIST_STATUS1 (0x7C)

414

#define HDMI_PHY_TX2_TX3_BIST_STATUS2 (0x80)

415

#define HDMI_PHY_PRE_MISR_STATUS0 (0x84)

416

#define HDMI_PHY_PRE_MISR_STATUS1 (0x88)

417

#define HDMI_PHY_PRE_MISR_STATUS2 (0x8C)

418

#define HDMI_PHY_PRE_MISR_STATUS3 (0x90)

419

#define HDMI_PHY_POST_MISR_STATUS0 (0x94)

420

#define HDMI_PHY_POST_MISR_STATUS1 (0x98)

421

#define HDMI_PHY_POST_MISR_STATUS2 (0x9C)

422

#define HDMI_PHY_POST_MISR_STATUS3 (0xA0)

423

#define HDMI_PHY_STATUS (0xA4)

424

#define HDMI_PHY_MISC3_STATUS (0xA8)

425

#define HDMI_PHY_DEBUG_BUS0 (0xAC)

426

#define HDMI_PHY_DEBUG_BUS1 (0xB0)

427

#define HDMI_PHY_DEBUG_BUS2 (0xB4)

428

#define HDMI_PHY_DEBUG_BUS3 (0xB8)

429

#define HDMI_PHY_REVISION_ID0 (0xBC)

430

#define HDMI_PHY_REVISION_ID1 (0xC0)

431

#define HDMI_PHY_REVISION_ID2 (0xC4)

432

#define HDMI_PHY_REVISION_ID3 (0xC8)

433

434

#define HDMI_PLL_POLL_MAX_READS 2500

435

#define HDMI_PLL_POLL_TIMEOUT_US 50

436

437

static uint32_t clk_tbl[HDMI_PHY_CLK_SIZE] = {

438

297000000, 268500000, 148500000, 74250000, 27000000, 27027000,

439

25200000, 108108000, 54054000, 25175000, 31500000, 33750000,

440

35500000, 36000000, 40000000, 49500000, 50000000, 56250000,

441

65000000, 68250000, 71000000, 72000000, 73250000, 75000000,

442

78750000, 79500000, 83500000, 85500000, 88750000, 94500000,

443

101000000, 102250000, 106500000, 108000000, 115500000, 117500000,

444

119000000, 121750000, 122500000, 135000000, 136750000, 140250000,

445

146250000, 148250000, 25175000, 31469000, 33784000, 37762000,

446

37800000, 40500000, 40541000, 44900000, 73515000, 74176000,

447

91894000, 92720000, 92813000, 110272000, 111264000, 111375000,

448

118681000, 118800000, 140250000, 148352000, 154000000, 156000000,

449

157000000, 157500000, 162000000, 175500000, 178022000, 178200000,

450

179500000, 182750000, 185440000, 185625000, 187000000, 187250000,

451

189000000, 193250000, 202500000, 204750000, 208000000, 214750000,

452

218250000, 222527000, 222750000, 229500000, 234000000, 245250000,

453

245500000, 261000000, 268250000, 281250000, 288000000, 296703000,

340000000,

};

/* one to one mapping with clk_tbl */

458

static uint32_t clk_settings[CALC_MAX][HDMI_PHY_CLK_SIZE] = {

459

{ /* CALC_QSERDES_COM_SYSCLK_EN_SEL_TXBAND */

460

0x4A, 0x4A, 0x5A, 0x6A, 0x7A, 0x7A, 0x7A, 0x5A, 0x6A, 0x7A,

461

0x7A, 0x7A, 0x7A, 0x7A, 0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x6A,

462

0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x5A, 0x5A, 0x5A, 0x5A,

463

0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A,

464

0x5A, 0x5A, 0x5A, 0x5A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x6A,

465

0x6A, 0x6A, 0x6A, 0x6A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A,

466

0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x4A, 0x4A,

467

0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A,

468

0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A,

469

0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A

470

},

471

{ /* CALC_QSERDES_COM_DIV_REF1 */

472

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

473

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

474

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

475

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

476

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

477

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

478

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

479

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

480

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

481

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

482

},

483

{ /* CALC_QSERDES_COM_DIV_REF2 */

484

0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,

485

0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,

486

0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,

487

0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,

488

0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,

489

0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,

490

0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,

491

0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,

492

0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,

493

0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00

494

},

495

{ /* CALC_QSERDES_COM_KVCO_COUNT1 */

496

0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,

497

0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,

498

0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,

499

0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,

500

0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,

501

0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,

502

0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,

503

0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,

504

0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,

505

0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x00

506

},

507

{ /* CALC_QSERDES_COM_KVCO_COUNT2 */

508

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

509

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

510

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

511

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

512

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

513

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

514

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

515

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

516

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

517

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

518

},

519

{ /* CALC_QSERDES_COM_KVCO_CAL_CNTRL */

520

0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,

521

0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,

522

0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,

523

0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,

524

0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,

525

0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,

526

0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,

527

0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,

528

0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,

529

0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00

530

},

531

{ /* CALC_QSERDES_COM_KVCO_CODE */

532

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

533

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

534

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

535

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

536

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

537

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

538

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

539

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

540

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

541

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F

542

},

543

{ /* CALC_QSERDES_COM_VREF_CFG3 */

544

0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,

545

0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,

546

0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,

547

0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,

548

0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,

549

0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,

550

0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,

551

0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,

552

0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,

553

0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00

554

},

555

{ /* CALC_QSERDES_COM_VREF_CFG4 */

556

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

557

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

558

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

559

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

560

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

561

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

562

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

563

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

564

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

565

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

566

},

567

{ /* CALC_QSERDES_COM_VREF_CFG5 */

568

0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,

569

0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,

570

0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,

571

0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,

572

0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,

573

0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,

574

0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,

575

0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,

576

0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,

577

0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10

578

},

579

{ /* CALC_QSERDES_COM_PLL_IP_SETI */

580

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

581

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

582

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

583

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

584

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

585

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

586

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

587

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

588

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

589

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03

590

},

591

{ /* CALC_QSERDES_COM_PLL_CP_SETI */

592

0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,

593

0x3F, 0x3F, 0x2F, 0x2F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,

594

0x2F, 0x2F, 0x2F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,

595

0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,

596

0x3F, 0x2F, 0x2F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,

597

0x3F, 0x3F, 0x2F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,

598

0x3F, 0x3F, 0x2F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,

599

0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,

600

0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,

601

0x3F, 0x3F, 0x3F, 0x2F, 0x2F, 0x3F, 0x3F

602

},

603

{ /* CALC_QSERDES_COM_PLL_IP_SETP */

604

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

605

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

606

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

607

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

608

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

609

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

610

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

611

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

612

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,

613

0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03

614

},

615

{ /* CALC_QSERDES_COM_PLL_CP_SETP */

616

0x17, 0x1F, 0x17, 0x17, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,

617

0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,

618

0x1F, 0x1F, 0x1F, 0x17, 0x17, 0x17, 0x1F, 0x1F, 0x1F, 0x1F,

619

0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,

620

0x1F, 0x1F, 0x1F, 0x17, 0x1F, 0x1F, 0x1F, 0x17, 0x17, 0x1F,

621

0x1F, 0x1F, 0x1F, 0x17, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,

622

0x1F, 0x1F, 0x1F, 0x17, 0x17, 0x17, 0x17, 0x17, 0x1F, 0x1F,

623

0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,

624

0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,

625

0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x17, 0x17

626

},

627

{ /* CALC_QSERDES_COM_PLL_CRCTRL */

628

0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,

629

0xBB, 0xBB, 0xBB, 0xBB, 0x77, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,

630

0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,

631

0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,

632

0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,

633

0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,

634

0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,

635

0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,

636

0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,

637

0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB

638

},

639

{ /* CALC_QSERDES_COM_DIV_FRAC_START1 */

640

0x80, 0x80, 0x80, 0x80, 0x80, 0xE6, 0x80, 0xE6, 0xE6, 0xAB,

641

0x80, 0x80, 0xD5, 0x80, 0xAB, 0x80, 0xD5, 0x80, 0xD5, 0x80,

642

0xD5, 0x80, 0xD5, 0x80, 0x80, 0x80, 0xD5, 0x80, 0xD5, 0x80,

643

0xAB, 0xD5, 0x80, 0x80, 0x80, 0xAB, 0xAB, 0xD5, 0xD5, 0x80,

644

0xD5, 0x80, 0x80, 0xAB, 0xAB, 0xF7, 0xA2, 0xBC, 0x80, 0x80,

645

0xEF, 0xD5, 0x80, 0xC4, 0x89, 0xAB, 0x91, 0xEF, 0xB3, 0x80,

646

0xA2, 0x80, 0x80, 0xC4, 0xD5, 0x80, 0xD5, 0x80, 0x80, 0x80,

647

0xA2, 0x80, 0xAB, 0xD5, 0xAB, 0x80, 0xAB, 0xD5, 0x80, 0xD5,

648

0x80, 0x80, 0xAB, 0xAB, 0x80, 0xA2, 0x80, 0x80, 0x80, 0x80,

649

0xAB, 0x80, 0xD5, 0x80, 0x80, 0xB3, 0xAB

650

},

651

{ /* CALC_QSERDES_COM_DIV_FRAC_START2 */

652

0x80, 0x80, 0x80, 0x80, 0x80, 0xCC, 0x80, 0xCC, 0xCC, 0xD5,

653

0x80, 0x80, 0xAA, 0x80, 0xD5, 0x80, 0xAA, 0x80, 0xAA, 0x80,

654

0xAA, 0x80, 0xAA, 0x80, 0x80, 0x80, 0xAA, 0x80, 0xAA, 0x80,

655

0xD5, 0xAA, 0x80, 0x80, 0x80, 0xD5, 0xD5, 0xAA, 0xAA, 0x80,

656

0xAA, 0x80, 0x80, 0xD5, 0xD5, 0xEE, 0xC4, 0xF7, 0x80, 0x80,

657

0xDD, 0xAA, 0x80, 0x88, 0x91, 0xD5, 0xE2, 0xDD, 0xE6, 0xC0,

658

0x84, 0x80, 0x80, 0x88, 0xAA, 0x80, 0xAA, 0x80, 0x80, 0x80,

659

0x84, 0x80, 0xD5, 0xEA, 0xD5, 0xE0, 0xD5, 0xEA, 0x80, 0xEA,

660

0x80, 0xC0, 0xD5, 0x95, 0xC0, 0xE4, 0xC0, 0x80, 0x80, 0xC0,

661

0xD5, 0x80, 0xEA, 0xC0, 0x80, 0x86, 0xD5

662

},

663

{ /* CALC_QSERDES_COM_DIV_FRAC_START3 */

664

0x56, 0x7B, 0x56, 0x56, 0x50, 0x53, 0x60, 0x53, 0x53, 0x5C,

665

0x68, 0x54, 0x7D, 0x40, 0x6A, 0x64, 0x45, 0x66, 0x6D, 0x46,

666

0x7D, 0x40, 0x53, 0x48, 0x42, 0x74, 0x5F, 0x62, 0x4E, 0x4E,

667

0x66, 0x50, 0x5E, 0x50, 0x4A, 0x4C, 0x7E, 0x5A, 0x73, 0x54,

668

0x4E, 0x43, 0x4B, 0x4D, 0x5C, 0x63, 0x58, 0x6A, 0x70, 0x4C,

669

0x4E, 0x71, 0x65, 0x51, 0x77, 0x52, 0x55, 0x5B, 0x7C, 0x40,

670

0x74, 0x78, 0x43, 0x51, 0x4D, 0x50, 0x71, 0x42, 0x4C, 0x6D,

671

0x57, 0x5A, 0x6F, 0x65, 0x52, 0x55, 0x6C, 0x70, 0x4E, 0x54,

672

0x6F, 0x54, 0x4A, 0x7B, 0x75, 0x7C, 0x40, 0x71, 0x7C, 0x77,

673

0x7B, 0x7E, 0x76, 0x4F, 0x40, 0x51, 0x62

674

},

675

{ /* CALC_QSERDES_COM_DEC_START1 */

676

0xCD, 0xC5, 0xCD, 0xCD, 0xB8, 0xB8, 0xB4, 0xB8, 0xB8, 0xB4,

677

0xC1, 0xC6, 0xC9, 0xCB, 0xA9, 0xB3, 0xB4, 0xBA, 0xC3, 0xC7,

678

0xC9, 0xCB, 0xCC, 0xCE, 0xD2, 0xD2, 0xAB, 0xAC, 0xAE, 0xB1,

679

0xB4, 0xB5, 0xB7, 0xB8, 0xBC, 0xBD, 0xBD, 0xBF, 0xBF, 0xC6,

680

0xC7, 0xC9, 0xCC, 0xCD, 0xB4, 0xC1, 0xC6, 0xCE, 0xCE, 0xAA,

681

0xAA, 0xAE, 0xCC, 0xCD, 0xAF, 0xB0, 0xB0, 0xB9, 0xB9, 0xBA,

682

0xBD, 0xBD, 0xC9, 0xCD, 0xD0, 0xD1, 0xD1, 0xD2, 0xAA, 0xAD,

683

0xAE, 0xAE, 0xAE, 0xAF, 0xB0, 0xB0, 0xB0, 0xB0, 0xB1, 0xB2,

684

0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBF,

685

0xBF, 0xC3, 0xC5, 0xC9, 0xCB, 0xCD, 0xD8

686

},

687

{ /*CALC_QSERDES_COM_DEC_START2 */

688

0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,

689

0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,

690

0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,

691

0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,

692

0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,

693

0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,

694

0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,

695

0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,

696

0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,

697

0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02

698

},

699

{ /* CALC_QSERDES_COM_PLLLOCK_CMP1 */

700

0xDF, 0xEF, 0xDF, 0xDF, 0xFF, 0x0B, 0xFF, 0x0B, 0x0B, 0xF4,

701

0x7F, 0x3F, 0x2A, 0xFF, 0x54, 0x3F, 0xAA, 0xDF, 0x2A, 0xDF,

702

0x2A, 0xFF, 0x0A, 0x7F, 0x9F, 0x3F, 0xCA, 0x9F, 0xFA, 0x5F,

703

0x14, 0x9A, 0x5F, 0xFF, 0x1F, 0xF4, 0x94, 0xBA, 0x0A, 0x3F,

704

0xFA, 0x6F, 0xEF, 0xC4, 0xF4, 0x72, 0x4E, 0xEF, 0xFF, 0xBF,

705

0xC8, 0x6A, 0x42, 0xCF, 0x49, 0xA1, 0xAB, 0xF1, 0x5B, 0x67,

706

0x72, 0x7F, 0x6F, 0xCF, 0x2A, 0xFF, 0x6A, 0x9F, 0xBF, 0x8F,

707

0x16, 0x1F, 0x64, 0x12, 0xA1, 0xAB, 0xF4, 0x02, 0x5F, 0x42,

708

0x2F, 0xA7, 0x54, 0xBC, 0x77, 0x5B, 0x67, 0xCF, 0xBF, 0x17,

709

0x24, 0x5F, 0xE2, 0x97, 0xFF, 0xCF, 0xD4

710

},

711

{ /* CALC_QSERDES_COM_PLLLOCK_CMP2 */

712

0x3D, 0x37, 0x3D, 0x3D, 0x2C, 0x2D, 0x29, 0x2D, 0x2D, 0x29,

713

0x34, 0x38, 0x3B, 0x3B, 0x21, 0x29, 0x29, 0x2E, 0x36, 0x38,

714

0x3B, 0x3B, 0x3D, 0x3E, 0x41, 0x42, 0x22, 0x23, 0x24, 0x27,

715

0x2A, 0x2A, 0x2C, 0x2C, 0x30, 0x30, 0x31, 0x32, 0x33, 0x38,

716

0x38, 0x3A, 0x3C, 0x3D, 0x29, 0x34, 0x38, 0x3E, 0x3E, 0x21,

717

0x21, 0x25, 0x3D, 0x3D, 0x26, 0x26, 0x26, 0x2D, 0x2E, 0x2E,

718

0x31, 0x31, 0x3A, 0x3D, 0x40, 0x40, 0x41, 0x41, 0x21, 0x24,

719

0x25, 0x25, 0x25, 0x26, 0x26, 0x26, 0x26, 0x27, 0x27, 0x28,

720

0x2A, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2E, 0x2F, 0x30, 0x33,

721

0x33, 0x36, 0x37, 0x3A, 0x3B, 0x3D, 0x46

722

},

723

{ /* CALC_QSERDES_COM_PLLLOCK_CMP3 */

724

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

725

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

726

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

727

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

728

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

729

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

730

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

731

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

732

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

733

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

734

},

735

{ /* CALC_QSERDES_COM_PLLLOCK_CMP_EN */

736

0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,

737

0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,

738

0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,

739

0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,

740

0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,

741

0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,

742

0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,

743

0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,

744

0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,

745

0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11

746

},

747

{ /* CALC_QSERDES_COM_RESETSM_CNTRL */

748

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

749

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

750

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

751

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

752

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

753

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

754

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

755

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

756

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

757

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80

758

},

759

{ /* CALC_HDMI_PHY_MODE */

760

0x00, 0x00, 0x01, 0x02, 0x03, 0x03, 0x03, 0x01, 0x02, 0x03,

761

0x03, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,

762

0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x01,

763

0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,

764

0x01, 0x01, 0x01, 0x01, 0x03, 0x03, 0x03, 0x03, 0x03, 0x02,

765

0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,

766

0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00,

767

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

768

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

769

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

}

};

#define SW_RESET BIT(2)

774

#define SW_RESET_PLL BIT(0)

775

776

void hdmi_phy_reset(void)

777

{

778

uint32_t phy_reset_polarity = 0x0;

779

uint32_t pll_reset_polarity = 0x0;

780

uint32_t val;

781

782

val = readl(HDMI_PHY_CTRL);

783

784

phy_reset_polarity = val >> 3 & 0x1;

785

pll_reset_polarity = val >> 1 & 0x1;

786

787

if (phy_reset_polarity == 0)

788

writel(val | SW_RESET, HDMI_PHY_CTRL);

789

else

790

writel(val & (~SW_RESET), HDMI_PHY_CTRL);

791

792

if (pll_reset_polarity == 0)

793

writel(val | SW_RESET_PLL, HDMI_PHY_CTRL);

794

else

795

writel(val & (~SW_RESET_PLL), HDMI_PHY_CTRL);

796

797

if (phy_reset_polarity == 0)

798

writel(val & (~SW_RESET), HDMI_PHY_CTRL);

799

else

800

writel(val | SW_RESET, HDMI_PHY_CTRL);

801

802

if (pll_reset_polarity == 0)

803

writel(val & (~SW_RESET_PLL), HDMI_PHY_CTRL);

804

else

805

writel(val | SW_RESET_PLL, HDMI_PHY_CTRL);

806

}

807

808

static uint32_t hdmi_poll_status(void)

809

{

810

uint32_t ready_poll;

811

uint32_t time_out_loop;

812

uint32_t time_out_max = HDMI_PLL_POLL_MAX_READS;

813

814

/* Poll for C_READY and PHY READY */

815

dprintf(SPEW, "%s: Waiting for PHY Ready\n", __func__);

time_out_loop = 0;

do {

if (time_out_loop)

udelay(HDMI_PLL_POLL_TIMEOUT_US);

820

821

ready_poll = readl(HDMI_PLL_BASE + QSERDES_COM_RESET_SM);

822

time_out_loop++;

823

} while (!(ready_poll & BIT(6)) &&

824

(time_out_loop < time_out_max));

825

826

if (time_out_loop >= time_out_max) {

827

dprintf(CRITICAL, "%s: C READY TIMEOUT\n", __func__);

828

return ERROR;

829

} else {

830

dprintf(SPEW, "%s: C READY\n", __func__);

831

}

832

833

/* Poll for PHY READY */

834

dprintf(SPEW, "%s: Waiting for PHY Ready\n", __func__);

835

time_out_loop = 0;

836

do {

837

udelay(HDMI_PLL_POLL_TIMEOUT_US);

838

839

ready_poll = readl(HDMI_PHY_BASE + HDMI_PHY_STATUS);

840

time_out_loop++;

841

} while (!(ready_poll & BIT(0)) && (time_out_loop < time_out_max));

842

843

if (time_out_loop >= time_out_max) {

844

dprintf(CRITICAL, "%s: PHY READY TIMEOUT\n", __func__);

return ERROR;

} else {

udelay(100);

dprintf(SPEW, "%s: HDMI PHY READY\n", __func__);

}

return NO_ERROR;

}

Casey Piper

2015-03-26 16:12:10 -0700

[diff] [blame]

854

uint32_t hdmi_pll_config(uint32_t tmds_clk_rate)

Casey Piper

68b7e94

2015-03-20 15:56:16 -0700

[diff] [blame]

855

{

Casey Piper

68b7e94

2015-03-20 15:56:16 -0700

[diff] [blame]

856

uint32_t clk_index;

857

858

/* Find clock target for reset sequence */

859

for (clk_index = 0; clk_index < HDMI_PHY_CLK_SIZE; clk_index++) {

860

if ((clk_tbl[clk_index] >= (tmds_clk_rate - 2000)) &&

861

(clk_tbl[clk_index] <= (tmds_clk_rate + 2000))) {

862

dprintf(SPEW, "%s: found clk %d\n", __func__,

tmds_clk_rate);

break;

}

}

if (clk_index >= HDMI_PHY_CLK_SIZE) {

869

dprintf(CRITICAL, "%s: pixel clock %d not valid\n",

870

__func__, tmds_clk_rate);

return ERROR;

}

/* Initially shut down PHY */

875

dprintf(SPEW, "%s: Disabling PHY\n", __func__);

876

writel(0x0, HDMI_PHY_BASE + HDMI_PHY_PD_CTL);

877

udelay(100);

878

879

/* power-up and recommended common block settings */

880

writel(0x1F, HDMI_PHY_BASE + HDMI_PHY_PD_CTL);

881

writel(0x01, HDMI_PHY_BASE + HDMI_PHY_CFG);

882

udelay(100);

883

884

writel(0x07, HDMI_PHY_BASE + HDMI_PHY_CFG);

885

udelay(100);

886

887

writel(0x05, HDMI_PHY_BASE + HDMI_PHY_CFG);

888

udelay(100);

889

890

writel(0x42, HDMI_PLL_BASE + QSERDES_COM_SYS_CLK_CTRL);

891

writel(0x03, HDMI_PLL_BASE + QSERDES_COM_PLL_VCOTAIL_EN);

892

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_CMN_MODE);

893

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_IE_TRIM);

894

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_IP_TRIM);

895

writel(0x01, HDMI_PLL_BASE + QSERDES_COM_PLL_CNTRL);

896

writel(0x04, HDMI_PLL_BASE + QSERDES_COM_PLL_PHSEL_CONTROL);

897

writel(tmds_clk_rate > 148500000 ? 0x80 : 0xC0,

898

HDMI_PLL_BASE + QSERDES_COM_IPTAT_TRIM_VCCA_TX_SEL);

899

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_PLL_PHSEL_DC);

900

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_CORE_CLK_IN_SYNC_SEL);

901

902

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_PLL_BKG_KVCO_CAL_EN);

903

904

writel(0x0F, HDMI_PLL_BASE + QSERDES_COM_BIAS_EN_CLKBUFLR_EN);

905

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_ATB_SEL1);

906

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_ATB_SEL2);

907

908

writel(clk_settings[CALC_QSERDES_COM_SYSCLK_EN_SEL_TXBAND][clk_index],

909

HDMI_PLL_BASE + QSERDES_COM_SYSCLK_EN_SEL_TXBAND);

910

911

writel(0x30, HDMI_PLL_BASE + QSERDES_COM_KVCO_CODE);

912

writel(0x0F, HDMI_PLL_BASE + QSERDES_COM_BGTC);

913

914

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_PLL_TEST_UPDN);

915

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_PLL_VCO_TUNE);

916

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_PLL_AMP_OS);

917

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_SSC_EN_CENTER);

918

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_RES_CODE_UP);

919

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_RES_CODE_DN);

920

921

writel(0x77, HDMI_PLL_BASE + QSERDES_COM_RES_CODE_CAL_CSR);

922

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_RES_TRIM_EN_VCOCALDONE);

923

writel(0x00, HDMI_PLL_BASE + QSERDES_COM_FAUX_EN);

924

writel(0x0E, HDMI_PLL_BASE + QSERDES_COM_PLL_RXTXEPCLK_EN);

925

926

/* PLL loop bandwidth */

927

writel(0x01, HDMI_PLL_BASE + QSERDES_COM_PLL_IP_SETI);

928

writel(0x3F, HDMI_PLL_BASE + QSERDES_COM_PLL_CP_SETI);

929

writel(0x06, HDMI_PLL_BASE + QSERDES_COM_PLL_IP_SETP);

930

writel(0x1F, HDMI_PLL_BASE + QSERDES_COM_PLL_CP_SETP);

931

writel(0xBB, HDMI_PLL_BASE + QSERDES_COM_PLL_CRCTRL);

932

933

/* PLL calibration */

934

writel(clk_settings[CALC_QSERDES_COM_DIV_FRAC_START1][clk_index],

935

HDMI_PLL_BASE + QSERDES_COM_DIV_FRAC_START1);

936

writel(clk_settings[CALC_QSERDES_COM_DIV_FRAC_START2][clk_index],

937

HDMI_PLL_BASE + QSERDES_COM_DIV_FRAC_START2);

938

writel(clk_settings[CALC_QSERDES_COM_DIV_FRAC_START3][clk_index],

939

HDMI_PLL_BASE + QSERDES_COM_DIV_FRAC_START3);

940

writel(clk_settings[CALC_QSERDES_COM_DEC_START1][clk_index],

941

HDMI_PLL_BASE + QSERDES_COM_DEC_START1);

942

writel(clk_settings[CALC_QSERDES_COM_DEC_START2][clk_index],

943

HDMI_PLL_BASE + QSERDES_COM_DEC_START2);

944

writel(clk_settings[CALC_QSERDES_COM_PLLLOCK_CMP1][clk_index],

945

HDMI_PLL_BASE + QSERDES_COM_PLLLOCK_CMP1);

946

writel(clk_settings[CALC_QSERDES_COM_PLLLOCK_CMP2][clk_index],

947

HDMI_PLL_BASE + QSERDES_COM_PLLLOCK_CMP2);

948

writel(clk_settings[CALC_QSERDES_COM_PLLLOCK_CMP3][clk_index],

949

HDMI_PLL_BASE + QSERDES_COM_PLLLOCK_CMP3);

950

writel(0x01, HDMI_PLL_BASE + QSERDES_COM_PLLLOCK_CMP_EN);

951

952

/* Resistor calibration linear search */

953

writel(0x60, HDMI_PLL_BASE + QSERDES_COM_RES_CODE_START_SEG1);

954

writel(0x60, HDMI_PLL_BASE + QSERDES_COM_RES_CODE_START_SEG2);

955

writel(0x01, HDMI_PLL_BASE + QSERDES_COM_RES_TRIM_CONTROL);

956

957

/* Reset state machine control */

958

writel(0x80, HDMI_PLL_BASE + QSERDES_COM_RESETSM_CNTRL);

959

writel(0x07, HDMI_PLL_BASE + QSERDES_COM_RESETSM_CNTRL2);

960

udelay(100);

961

962

/* TX lanes (transceivers) power-up sequence */

963

writel(clk_settings[CALC_HDMI_PHY_MODE][clk_index],

964

HDMI_PHY_BASE + HDMI_PHY_MODE);

965

966

writel(0x03, HDMI_PLL_BASE + 0x400 + QSERDES_TX_L0_CLKBUF_ENABLE);

967

writel(0x03, HDMI_PLL_BASE + 0x600 + QSERDES_TX_L1_CLKBUF_ENABLE);

968

writel(0x03, HDMI_PLL_BASE + 0x800 + QSERDES_TX_L2_CLKBUF_ENABLE);

969

writel(0x03, HDMI_PLL_BASE + 0xA00 + QSERDES_TX_L3_CLKBUF_ENABLE);

970

971

writel(0x03, HDMI_PLL_BASE + 0x400 + QSERDES_TX_L0_TRAN_DRVR_EMP_EN);

972

writel(0x03, HDMI_PLL_BASE + 0x600 + QSERDES_TX_L1_TRAN_DRVR_EMP_EN);

973

writel(0x03, HDMI_PLL_BASE + 0x800 + QSERDES_TX_L2_TRAN_DRVR_EMP_EN);

974

writel(0x03, HDMI_PLL_BASE + 0xA00 + QSERDES_TX_L3_TRAN_DRVR_EMP_EN);

975

976

writel(0x6F, HDMI_PLL_BASE + 0x400 +

977

QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN);

978

writel(0x6F, HDMI_PLL_BASE + 0x600 +

979

QSERDES_TX_L1_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN);

980

writel(0x6F, HDMI_PLL_BASE + 0x800 +

981

QSERDES_TX_L2_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN);

982

writel(0x6F, HDMI_PLL_BASE + 0xA00 +

983

QSERDES_TX_L3_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN);

984

985

writel(tmds_clk_rate >= 74000000 ? 0x2F : 0x21,

986

HDMI_PLL_BASE + 0x400 + QSERDES_TX_L0_TX_EMP_POST1_LVL);

987

writel(tmds_clk_rate >= 74000000 ? 0xAF : 0xA1,

988

HDMI_PHY_BASE + HDMI_PHY_TXCAL_CFG0);

989

990

writel(tmds_clk_rate >= 74000000 ? 0x0C : 0x04,

991

HDMI_PLL_BASE + 0x400 + QSERDES_TX_L0_VMODE_CTRL1);

992

writel(tmds_clk_rate >= 74000000 ? 0x0D : 0x05,

993

HDMI_PLL_BASE + 0x800 + QSERDES_TX_L2_VMODE_CTRL1);

994

writel(tmds_clk_rate >= 74000000 ? 0x1F : 0x11,

995

HDMI_PLL_BASE + 0x400 + QSERDES_TX_L0_TX_DRV_LVL);

996

writel(tmds_clk_rate >= 74000000 ? 0x1F : 0x11,

997

HDMI_PLL_BASE + 0x800 + QSERDES_TX_L2_TX_DRV_LVL);

998

writel(0x80, HDMI_PLL_BASE + 0x400 + QSERDES_TX_L0_VMODE_CTRL2);

999

writel(0x00, HDMI_PLL_BASE + 0x800 + QSERDES_TX_L2_VMODE_CTRL2);

1000

writel(tmds_clk_rate >= 74000000 ? 0x01 : 0x02,

1001

HDMI_PLL_BASE + 0x400 + QSERDES_TX_L0_VMODE_CTRL3);

1002

writel(tmds_clk_rate >= 74000000 ? 0x00 : 0x02,

1003

HDMI_PLL_BASE + 0x800 + QSERDES_TX_L2_VMODE_CTRL3);

1004

writel(tmds_clk_rate >= 74000000 ? 0x00 : 0xA0,

1005

HDMI_PLL_BASE + 0x400 + QSERDES_TX_L0_VMODE_CTRL5);

1006

writel(tmds_clk_rate >= 74000000 ? 0x00 : 0xA0,

1007

HDMI_PLL_BASE + 0x800 + QSERDES_TX_L2_VMODE_CTRL5);

1008

writel(0x00, HDMI_PLL_BASE + 0x400 + QSERDES_TX_L0_VMODE_CTRL6);

1009

writel(0x00, HDMI_PLL_BASE + 0x800 + QSERDES_TX_L2_VMODE_CTRL6);

1010

1011

writel(0x40, HDMI_PLL_BASE + 0x400 +

1012

QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN);

1013

writel(0x00, HDMI_PLL_BASE + 0x400 +

1014

QSERDES_TX_L0_TX_INTERFACE_MODE);

1015

writel(0x40, HDMI_PLL_BASE + 0x600 +

1016

QSERDES_TX_L1_PARRATE_REC_DETECT_IDLE_EN);

1017

writel(0x00, HDMI_PLL_BASE + 0x600 +

1018

QSERDES_TX_L1_TX_INTERFACE_MODE);

1019

writel(0x40, HDMI_PLL_BASE + 0x800 +

1020

QSERDES_TX_L2_PARRATE_REC_DETECT_IDLE_EN);

1021

writel(0x00, HDMI_PLL_BASE + 0x800 +

1022

QSERDES_TX_L2_TX_INTERFACE_MODE);

1023

writel(0x40, HDMI_PLL_BASE + 0xA00 +

1024

QSERDES_TX_L3_PARRATE_REC_DETECT_IDLE_EN);

1025

writel(0x00, HDMI_PLL_BASE + 0xA00 +

1026

QSERDES_TX_L3_TX_INTERFACE_MODE);

return NO_ERROR;

}

int hdmi_vco_enable(void)

{

int rc;

writel(0x01, HDMI_PHY_BASE + HDMI_PHY_CFG);

1036

udelay(100);

1037

1038

writel(0x03, HDMI_PHY_BASE + HDMI_PHY_CFG);

1039

udelay(100);

1040

1041

writel(0x09, HDMI_PHY_BASE + HDMI_PHY_CFG);

1042

udelay(100);

1043

1044

rc = hdmi_poll_status();

1045

1046

writel(0x08, HDMI_PHY_BASE + HDMI_PHY_CFG);

1047

udelay(100);

1048

1049

writel(0x09, HDMI_PHY_BASE + HDMI_PHY_CFG);

udelay(100);

return rc;

}

void hdmi_vco_disable(void)

1056

{

1057

writel(0x0, HDMI_PHY_BASE + HDMI_PHY_PD_CTL);

1058

udelay(100);

1059

}