Channagoud Kadabi | dd7cb38 | 2015-03-23 23:30:25 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in the |
| 10 | * documentation and/or other materials provided with the distribution. |
| 11 | * * Neither the name of The Linux Foundation nor |
| 12 | * the names of its contributors may be used to endorse or promote |
| 13 | * products derived from this software without specific prior written |
| 14 | * permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 19 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 20 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 21 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 22 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 23 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 25 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 26 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #ifndef CLK_APLHA_PLL |
| 30 | #define CLK_APLHA_PLL |
| 31 | |
| 32 | #include <platform/iomap.h> |
| 33 | #include <platform/clock.h> |
| 34 | |
| 35 | #define L_REG(pll) (pll->base + pll->offset + 0x4) |
| 36 | #define A_REG(pll) (pll->base + pll->offset + 0x8) |
| 37 | #define A_REG_U(pll) (pll->base + pll->offset + 0xC) |
| 38 | #define ACTIVE_REG(pll) (pll->base + pll->offset + 0x0) |
| 39 | #define VOTE_REG(pll) (pll->base + pll->fsm_reg_offset) |
| 40 | #define VCO_REG(pll) (pll->base + pll->offset + 0x10) |
| 41 | #define OUTPUT_REG(pll) (pll->base + pll->offset + 0x10) |
| 42 | #define USER_CTL_LO_REG(pll) (pll->base + pll->offset + 0x10) |
| 43 | #define MODE_REG(pll) (pll->base + pll->offset + 0x0) |
| 44 | #define LOCK_REG(pll) (pll->base + pll->offset + 0x0) |
| 45 | #define ALPHA_EN_REG(pll) (pll->base + pll->offset + 0x10) |
| 46 | |
| 47 | #define PLL_VOTE_FSM_ENA BIT(20) |
| 48 | #define PLL_VOTE_FSM_RESET BIT(21) |
| 49 | #define PLL_BIAS_COUNT_START 14 |
| 50 | #define PLL_BIAS_COUNT_END 19 |
| 51 | #define PLL_BIAS_COUNT 0x6 |
| 52 | #define PLL_LOCK_COUNT_START 8 |
| 53 | #define PLL_LOCK_COUNT_END 13 |
| 54 | |
| 55 | #define VCO(a, b, c) { \ |
| 56 | .vco_val = a,\ |
| 57 | .min_freq = b,\ |
| 58 | .max_freq = c,\ |
| 59 | } |
| 60 | |
| 61 | struct alpha_pll_vco_tbl { |
| 62 | uint32_t vco_val; |
| 63 | unsigned long min_freq; |
| 64 | unsigned long max_freq; |
| 65 | }; |
| 66 | |
| 67 | struct alpha_pll_masks { |
| 68 | uint32_t lock_mask; /* lock_det bit */ |
| 69 | uint32_t active_mask; /* active_flag in FSM mode */ |
| 70 | uint32_t update_mask; /* update bit for dynamic update */ |
| 71 | uint32_t vco_mask; /* vco_sel bits */ |
| 72 | uint32_t vco_shift; |
| 73 | uint32_t alpha_en_mask; /* alpha_en bit */ |
| 74 | uint32_t output_mask; /* pllout_* bits */ |
| 75 | uint32_t post_div_mask; |
| 76 | }; |
| 77 | |
| 78 | struct alpha_pll_clk { |
| 79 | struct alpha_pll_masks *masks; |
| 80 | uint32_t offset; |
| 81 | uint32_t base; |
| 82 | struct alpha_pll_vco_tbl *vco_tbl; |
| 83 | uint32_t vco_num; |
| 84 | /* if fsm_en_mask is set, config PLL to FSM mode */ |
| 85 | uint32_t fsm_reg_offset; |
| 86 | uint32_t fsm_en_mask; |
| 87 | uint32_t enable_config; /* bitmask of outputs to be enabled */ |
| 88 | uint32_t post_div_config; /* masked post divider setting */ |
| 89 | bool inited; |
| 90 | struct clk *parent; |
| 91 | struct clk c; |
| 92 | }; |
| 93 | |
| 94 | void alpha_pll_disable(struct clk *c); |
| 95 | int alpha_pll_enable(struct clk *c); |
| 96 | |
| 97 | #endif |