Duy Truong | f3ac7b3 | 2013-02-13 01:07:28 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012, The Linux Foundation. All rights reserved. |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Duy Truong | f3ac7b3 | 2013-02-13 01:07:28 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include <stdint.h> |
| 31 | #include <msm_panel.h> |
| 32 | #include <mipi_dsi.h> |
| 33 | #include <sys/types.h> |
| 34 | #include <err.h> |
| 35 | #include <reg.h> |
| 36 | #include <debug.h> |
| 37 | #include <platform/iomap.h> |
| 38 | #include <mdp4.h> |
| 39 | #include <clock.h> |
| 40 | |
| 41 | #include "mipi_tc358764_dsi2lvds.h" |
| 42 | |
| 43 | int mipi_chimei_video_wxga_early_config(void *pdata) |
| 44 | { |
| 45 | uint32_t tmp; |
| 46 | uint32_t reg = DSI_LANE_CTRL; |
| 47 | struct msm_panel_info *pinfo = (struct msm_panel_info *)pdata; |
| 48 | |
| 49 | /* Force DSI-clock ON */ |
| 50 | tmp = readl_relaxed(reg); |
| 51 | tmp |= (1<<28); |
| 52 | writel_relaxed(tmp, reg); |
| 53 | |
| 54 | mipi_d2l_dsi_init_sequence(pinfo); |
| 55 | } |
| 56 | |
| 57 | int mipi_chimei_video_wxga_config(void *pdata) |
| 58 | { |
| 59 | int ret = NO_ERROR; |
| 60 | struct lcdc_panel_info *lcdc = NULL; |
| 61 | struct msm_panel_info *pinfo = (struct msm_panel_info *)pdata; |
| 62 | unsigned char lane_en = 0x0F; /* 4 Lanes */ |
| 63 | unsigned long low_pwr_stop_mode = 0; |
| 64 | unsigned char eof_bllp_pwr = 0; |
| 65 | unsigned char interleav = 0; |
| 66 | |
| 67 | if (pinfo == NULL) |
| 68 | return ERR_INVALID_ARGS; |
| 69 | |
| 70 | lcdc = &(pinfo->lcdc); |
| 71 | if (lcdc == NULL) |
| 72 | return ERR_INVALID_ARGS; |
| 73 | |
| 74 | ret = mipi_dsi_video_mode_config((pinfo->xres + lcdc->xres_pad), |
| 75 | (pinfo->yres + lcdc->yres_pad), |
| 76 | (pinfo->xres), |
| 77 | (pinfo->yres), |
| 78 | (lcdc->h_front_porch), |
| 79 | (lcdc->h_back_porch + lcdc->h_pulse_width), |
| 80 | (lcdc->v_front_porch), |
| 81 | (lcdc->v_back_porch + lcdc->v_pulse_width), |
| 82 | (lcdc->h_pulse_width), |
| 83 | (lcdc->v_pulse_width), |
| 84 | pinfo->mipi.dst_format, |
| 85 | pinfo->mipi.traffic_mode, |
| 86 | lane_en, |
| 87 | low_pwr_stop_mode, |
| 88 | eof_bllp_pwr, |
| 89 | interleav); |
| 90 | |
| 91 | return ret; |
| 92 | } |
| 93 | |
| 94 | int mipi_chimei_video_wxga_on(void) |
| 95 | { |
| 96 | int ret = 0; |
| 97 | |
| 98 | return ret; |
| 99 | } |
| 100 | |
| 101 | int mipi_chimei_video_wxga_off(void) |
| 102 | { |
| 103 | int ret = 0; |
| 104 | |
| 105 | return ret; |
| 106 | } |
| 107 | |
| 108 | static struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db = { |
| 109 | /* DSIPHY_REGULATOR_CTRL */ |
| 110 | .regulator = {0x03, 0x0a, 0x04, 0x00, 0x20}, /* common 8960 */ |
| 111 | /* DSIPHY_CTRL */ |
| 112 | .ctrl = {0x5f, 0x00, 0x00, 0x10}, /* common 8960 */ |
| 113 | /* DSIPHY_STRENGTH_CTRL */ |
| 114 | .strength = {0xff, 0x00, 0x06, 0x00}, /* common 8960 */ |
| 115 | /* DSIPHY_TIMING_CTRL */ |
| 116 | .timing = { 0xB6, 0x8D, 0x1E, /* panel specific */ |
| 117 | 0, /* DSIPHY_TIMING_CTRL_3 = 0 */ |
| 118 | 0x21, 0x95, 0x21, 0x8F, 0x21, 0x03, 0x04}, /* panel specific */ |
| 119 | /* DSIPHY_PLL_CTRL */ |
| 120 | .pll = { 0x01, /* common 8960 */ |
| 121 | /* VCO */ |
| 122 | 0xD8, 0x01, 0x1A, /* panel specific */ |
| 123 | 0x00, 0x50, 0x48, 0x63, |
| 124 | 0x71, 0x0F, 0x03, /* Clocks dividers */ |
| 125 | 0x00, 0x14, 0x03, 0x00, 0x02, /* common 8960 */ |
| 126 | 0x00, 0x20, 0x00, 0x01 }, /* common 8960 */ |
| 127 | }; |
| 128 | |
| 129 | void mipi_chimei_video_wxga_init(struct msm_panel_info *pinfo) |
| 130 | { |
| 131 | if (!pinfo) |
| 132 | return; |
| 133 | |
| 134 | dprintf(INFO, "mipi-dsi chimei wxga (1366x768) driver ver 1.0.\n"); |
| 135 | |
| 136 | /* Landscape */ |
| 137 | pinfo->xres = 1366; |
| 138 | pinfo->yres = 768; |
| 139 | pinfo->type = MIPI_VIDEO_PANEL; |
| 140 | pinfo->wait_cycle = 0; |
| 141 | pinfo->bpp = 24; /* RGB888 = 24 bits-per-pixel */ |
| 142 | |
| 143 | /* bitclk */ |
| 144 | pinfo->clk_rate = 473400000; /* 473.4 MHZ Calculated */ |
| 145 | |
| 146 | /* |
| 147 | * this panel is operated by DE, |
| 148 | * vsycn and hsync are ignored |
| 149 | */ |
| 150 | |
| 151 | pinfo->lcdc.h_front_porch = 96+2;/* thfp */ |
| 152 | pinfo->lcdc.h_back_porch = 88; /* thb */ |
| 153 | pinfo->lcdc.h_pulse_width = 40; /* thpw */ |
| 154 | |
| 155 | pinfo->lcdc.v_front_porch = 15; /* tvfp */ |
| 156 | pinfo->lcdc.v_back_porch = 23; /* tvb */ |
| 157 | pinfo->lcdc.v_pulse_width = 20; /* tvpw */ |
| 158 | |
| 159 | pinfo->lcdc.border_clr = 0; /* black */ |
| 160 | pinfo->lcdc.underflow_clr = 0xff; /* blue */ |
| 161 | |
| 162 | pinfo->lcdc.hsync_skew = 0; |
| 163 | |
| 164 | /* mipi - general */ |
| 165 | pinfo->mipi.vc = 0; /* virtual channel */ |
| 166 | pinfo->mipi.rgb_swap = DSI_RGB_SWAP_RGB; |
| 167 | pinfo->mipi.tx_eot_append = true; |
| 168 | pinfo->mipi.t_clk_post = 34; /* Calculated */ |
| 169 | pinfo->mipi.t_clk_pre = 64; /* Calculated */ |
| 170 | |
| 171 | pinfo->mipi.dsi_phy_db = &dsi_video_mode_phy_db; |
| 172 | |
| 173 | /* Four lanes are recomended for 1366x768 at 60 frames per second */ |
| 174 | pinfo->mipi.frame_rate = 60; /* 60 frames per second */ |
| 175 | pinfo->mipi.data_lane0 = true; |
| 176 | pinfo->mipi.data_lane1 = true; |
| 177 | pinfo->mipi.data_lane2 = true; |
| 178 | pinfo->mipi.data_lane3 = true; |
| 179 | |
| 180 | pinfo->mipi.mode = DSI_VIDEO_MODE; |
| 181 | /* |
| 182 | * Note: The CMI panel input is RGB888, |
| 183 | * thus the DSI-to-LVDS bridge output is RGB888. |
| 184 | * This parameter selects the DSI-Core output to the bridge. |
| 185 | */ |
| 186 | pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888; |
| 187 | |
| 188 | /* mipi - video mode */ |
| 189 | pinfo->mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT; |
| 190 | pinfo->mipi.pulse_mode_hsa_he = false; /* sync mode */ |
| 191 | |
| 192 | pinfo->mipi.hfp_power_stop = false; |
| 193 | pinfo->mipi.hbp_power_stop = false; |
| 194 | pinfo->mipi.hsa_power_stop = false; |
| 195 | pinfo->mipi.eof_bllp_power_stop = false; |
| 196 | pinfo->mipi.bllp_power_stop = false; |
| 197 | |
| 198 | /* mipi - command mode */ |
| 199 | pinfo->mipi.te_sel = 1; /* TE from vsycn gpio */ |
| 200 | pinfo->mipi.interleave_max = 1; |
| 201 | /* The bridge supports only Generic Read/Write commands */ |
| 202 | pinfo->mipi.insert_dcs_cmd = false; |
| 203 | pinfo->mipi.wr_mem_continue = 0; |
| 204 | pinfo->mipi.wr_mem_start = 0; |
| 205 | pinfo->mipi.stream = false; /* dma_p */ |
| 206 | pinfo->mipi.mdp_trigger = DSI_CMD_TRIGGER_NONE; |
| 207 | pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW; |
| 208 | /* |
| 209 | * toshiba d2l chip does not need max_pkt_szie dcs cmd |
| 210 | * client reply len is directly configure through |
| 211 | * RDPKTLN register (0x0404) |
| 212 | */ |
| 213 | pinfo->mipi.no_max_pkt_size = 1; |
| 214 | pinfo->mipi.force_clk_lane_hs = 1; |
| 215 | |
| 216 | pinfo->mipi.num_of_lanes = 4; |
| 217 | pinfo->mipi.panel_cmds = NULL; /* use in mipi_dsi_panel_initialize() */ |
| 218 | pinfo->mipi.num_of_panel_cmds = 0; |
| 219 | |
| 220 | |
| 221 | /* Provide config/on/off callbacks */ |
| 222 | pinfo->on = mipi_chimei_video_wxga_on; |
| 223 | pinfo->off = mipi_chimei_video_wxga_off; |
| 224 | pinfo->config = mipi_chimei_video_wxga_config; |
| 225 | pinfo->early_config = mipi_chimei_video_wxga_early_config; |
| 226 | |
| 227 | return; |
| 228 | } |