Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 1 | /* |
sundarajan srinivasan | aa1992d | 2013-03-28 18:03:23 -0700 | [diff] [blame] | 2 | * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in the |
| 10 | * documentation and/or other materials provided with the distribution. |
| 11 | * * Neither the name of Linux Foundation nor |
| 12 | * the names of its contributors may be used to endorse or promote |
| 13 | * products derived from this software without specific prior written |
| 14 | * permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 19 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 20 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 21 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 22 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 23 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 25 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 26 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
| 42 | |
| 43 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 44 | |
| 45 | |
| 46 | /* Clock Operations */ |
| 47 | static struct clk_ops clk_ops_branch = |
| 48 | { |
| 49 | .enable = clock_lib2_branch_clk_enable, |
| 50 | .disable = clock_lib2_branch_clk_disable, |
| 51 | .set_rate = clock_lib2_branch_set_rate, |
| 52 | }; |
| 53 | |
| 54 | static struct clk_ops clk_ops_rcg_mnd = |
| 55 | { |
| 56 | .enable = clock_lib2_rcg_enable, |
| 57 | .set_rate = clock_lib2_rcg_set_rate, |
| 58 | }; |
| 59 | |
| 60 | static struct clk_ops clk_ops_rcg = |
| 61 | { |
| 62 | .enable = clock_lib2_rcg_enable, |
| 63 | .set_rate = clock_lib2_rcg_set_rate, |
| 64 | }; |
| 65 | |
| 66 | static struct clk_ops clk_ops_cxo = |
| 67 | { |
| 68 | .enable = cxo_clk_enable, |
| 69 | .disable = cxo_clk_disable, |
| 70 | }; |
| 71 | |
| 72 | static struct clk_ops clk_ops_pll_vote = |
| 73 | { |
| 74 | .enable = pll_vote_clk_enable, |
| 75 | .disable = pll_vote_clk_disable, |
| 76 | .auto_off = pll_vote_clk_disable, |
| 77 | .is_enabled = pll_vote_clk_is_enabled, |
| 78 | }; |
| 79 | |
Deepa Dinamani | dca5c66 | 2012-12-03 14:13:07 -0800 | [diff] [blame] | 80 | static struct clk_ops clk_ops_vote = |
| 81 | { |
| 82 | .enable = clock_lib2_vote_clk_enable, |
| 83 | .disable = clock_lib2_vote_clk_disable, |
| 84 | }; |
Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 85 | |
| 86 | /* Clock Sources */ |
| 87 | static struct fixed_clk cxo_clk_src = |
| 88 | { |
| 89 | .c = { |
| 90 | .rate = 19200000, |
| 91 | .dbg_name = "cxo_clk_src", |
| 92 | .ops = &clk_ops_cxo, |
| 93 | }, |
| 94 | }; |
| 95 | |
| 96 | static struct pll_vote_clk gpll0_clk_src = |
| 97 | { |
| 98 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 99 | .en_mask = BIT(0), |
| 100 | .status_reg = (void *) GPLL0_STATUS, |
| 101 | .status_mask = BIT(17), |
| 102 | .parent = &cxo_clk_src.c, |
| 103 | |
| 104 | .c = { |
| 105 | .rate = 600000000, |
| 106 | .dbg_name = "gpll0_clk_src", |
| 107 | .ops = &clk_ops_pll_vote, |
| 108 | }, |
| 109 | }; |
| 110 | |
| 111 | /* UART Clocks */ |
Deepa Dinamani | dca5c66 | 2012-12-03 14:13:07 -0800 | [diff] [blame] | 112 | |
| 113 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 114 | .cbcr_reg = BLSP1_AHB_CBCR, |
| 115 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 116 | .en_mask = BIT(17), |
| 117 | |
| 118 | .c = { |
| 119 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 120 | .ops = &clk_ops_vote, |
| 121 | }, |
| 122 | }; |
| 123 | |
Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 124 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = |
| 125 | { |
| 126 | F( 3686400, gpll0, 1, 96, 15625), |
| 127 | F( 7372800, gpll0, 1, 192, 15625), |
| 128 | F(14745600, gpll0, 1, 384, 15625), |
| 129 | F(16000000, gpll0, 5, 2, 15), |
| 130 | F(19200000, cxo, 1, 0, 0), |
| 131 | F(24000000, gpll0, 5, 1, 5), |
| 132 | F(32000000, gpll0, 1, 4, 75), |
| 133 | F(40000000, gpll0, 15, 0, 0), |
| 134 | F(46400000, gpll0, 1, 29, 375), |
| 135 | F(48000000, gpll0, 12.5, 0, 0), |
| 136 | F(51200000, gpll0, 1, 32, 375), |
| 137 | F(56000000, gpll0, 1, 7, 75), |
| 138 | F(58982400, gpll0, 1, 1536, 15625), |
| 139 | F(60000000, gpll0, 10, 0, 0), |
| 140 | F_END |
| 141 | }; |
| 142 | |
| 143 | static struct rcg_clk blsp1_uart1_apps_clk_src = |
| 144 | { |
| 145 | .cmd_reg = (uint32_t *) BLSP1_UART1_APPS_CMD_RCGR, |
| 146 | .cfg_reg = (uint32_t *) BLSP1_UART1_APPS_CFG_RCGR, |
| 147 | .m_reg = (uint32_t *) BLSP1_UART1_APPS_M, |
| 148 | .n_reg = (uint32_t *) BLSP1_UART1_APPS_N, |
| 149 | .d_reg = (uint32_t *) BLSP1_UART1_APPS_D, |
| 150 | |
| 151 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 152 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 153 | .current_freq = &rcg_dummy_freq, |
| 154 | |
| 155 | .c = { |
| 156 | .dbg_name = "blsp1_uart1_apps_clk", |
| 157 | .ops = &clk_ops_rcg_mnd, |
| 158 | }, |
| 159 | }; |
| 160 | |
Deepa Dinamani | dca5c66 | 2012-12-03 14:13:07 -0800 | [diff] [blame] | 161 | static struct rcg_clk blsp1_uart2_apps_clk_src = |
| 162 | { |
| 163 | .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR, |
| 164 | .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR, |
| 165 | .m_reg = (uint32_t *) BLSP1_UART2_APPS_M, |
| 166 | .n_reg = (uint32_t *) BLSP1_UART2_APPS_N, |
| 167 | .d_reg = (uint32_t *) BLSP1_UART2_APPS_D, |
| 168 | |
| 169 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 170 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 171 | .current_freq = &rcg_dummy_freq, |
| 172 | |
| 173 | .c = { |
| 174 | .dbg_name = "blsp1_uart2_apps_clk", |
| 175 | .ops = &clk_ops_rcg_mnd, |
| 176 | }, |
| 177 | }; |
| 178 | |
Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 179 | static struct rcg_clk blsp1_uart3_apps_clk_src = |
| 180 | { |
| 181 | .cmd_reg = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR, |
| 182 | .cfg_reg = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR, |
| 183 | .m_reg = (uint32_t *) BLSP1_UART3_APPS_M, |
| 184 | .n_reg = (uint32_t *) BLSP1_UART3_APPS_N, |
| 185 | .d_reg = (uint32_t *) BLSP1_UART3_APPS_D, |
| 186 | |
| 187 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 188 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 189 | .current_freq = &rcg_dummy_freq, |
| 190 | |
| 191 | .c = { |
| 192 | .dbg_name = "blsp1_uart3_apps_clk", |
| 193 | .ops = &clk_ops_rcg_mnd, |
| 194 | }, |
| 195 | }; |
| 196 | |
| 197 | static struct branch_clk gcc_blsp1_uart1_apps_clk = |
| 198 | { |
| 199 | .cbcr_reg = (uint32_t *) BLSP1_UART1_APPS_CBCR, |
| 200 | .parent = &blsp1_uart1_apps_clk_src.c, |
| 201 | |
| 202 | .c = { |
| 203 | .dbg_name = "gcc_blsp1_uart1_apps_clk", |
| 204 | .ops = &clk_ops_branch, |
| 205 | }, |
| 206 | }; |
| 207 | |
Deepa Dinamani | dca5c66 | 2012-12-03 14:13:07 -0800 | [diff] [blame] | 208 | static struct branch_clk gcc_blsp1_uart2_apps_clk = |
| 209 | { |
| 210 | .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR, |
| 211 | .parent = &blsp1_uart2_apps_clk_src.c, |
| 212 | |
| 213 | .c = { |
| 214 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 215 | .ops = &clk_ops_branch, |
| 216 | }, |
| 217 | }; |
| 218 | |
Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 219 | static struct branch_clk gcc_blsp1_uart3_apps_clk = |
| 220 | { |
| 221 | .cbcr_reg = (uint32_t *) BLSP1_UART3_APPS_CBCR, |
| 222 | .parent = &blsp1_uart3_apps_clk_src.c, |
| 223 | |
| 224 | .c = { |
| 225 | .dbg_name = "gcc_blsp1_uart3_apps_clk", |
| 226 | .ops = &clk_ops_branch, |
| 227 | }, |
| 228 | }; |
| 229 | |
| 230 | /* USB Clocks */ |
| 231 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = |
| 232 | { |
| 233 | F(75000000, gpll0, 8, 0, 0), |
| 234 | F_END |
| 235 | }; |
| 236 | |
| 237 | static struct rcg_clk usb_hs_system_clk_src = |
| 238 | { |
| 239 | .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR, |
| 240 | .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR, |
| 241 | |
| 242 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 243 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 244 | .current_freq = &rcg_dummy_freq, |
| 245 | |
| 246 | .c = { |
| 247 | .dbg_name = "usb_hs_system_clk", |
| 248 | .ops = &clk_ops_rcg, |
| 249 | }, |
| 250 | }; |
| 251 | |
| 252 | static struct branch_clk gcc_usb_hs_system_clk = |
| 253 | { |
| 254 | .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR, |
| 255 | .parent = &usb_hs_system_clk_src.c, |
| 256 | |
| 257 | .c = { |
| 258 | .dbg_name = "gcc_usb_hs_system_clk", |
| 259 | .ops = &clk_ops_branch, |
| 260 | }, |
| 261 | }; |
| 262 | |
| 263 | static struct branch_clk gcc_usb_hs_ahb_clk = |
| 264 | { |
| 265 | .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR, |
| 266 | .has_sibling = 1, |
| 267 | |
| 268 | .c = { |
| 269 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 270 | .ops = &clk_ops_branch, |
| 271 | }, |
| 272 | }; |
| 273 | |
Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 274 | /* Clock lookup table */ |
| 275 | static struct clk_lookup mdm_9625_clocks[] = |
| 276 | { |
Deepa Dinamani | dca5c66 | 2012-12-03 14:13:07 -0800 | [diff] [blame] | 277 | CLK_LOOKUP("uart_iface_clk", gcc_blsp1_ahb_clk.c), |
Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 278 | CLK_LOOKUP("uart1_core_clk", gcc_blsp1_uart1_apps_clk.c), |
Deepa Dinamani | dca5c66 | 2012-12-03 14:13:07 -0800 | [diff] [blame] | 279 | CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c), |
Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 280 | CLK_LOOKUP("uart3_core_clk", gcc_blsp1_uart3_apps_clk.c), |
| 281 | |
| 282 | CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c), |
| 283 | CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c), |
| 284 | |
Amol Jadi | b726c3b | 2012-09-13 13:51:23 -0700 | [diff] [blame] | 285 | }; |
| 286 | |
| 287 | |
| 288 | void platform_clock_init(void) |
| 289 | { |
| 290 | clk_init(mdm_9625_clocks, ARRAY_SIZE(mdm_9625_clocks)); |
| 291 | } |