Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved. |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Duy Truong | f3ac7b3 | 2013-02-13 01:07:28 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | #include <hdmi.h> |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 30 | #include <msm_panel.h> |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 31 | #include <platform/timer.h> |
| 32 | #include <platform/clock.h> |
| 33 | #include <platform/iomap.h> |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 34 | |
| 35 | #define MDP4_OVERLAYPROC1_BASE 0x18000 |
| 36 | #define MDP4_RGB_BASE 0x40000 |
| 37 | #define MDP4_RGB_OFF 0x10000 |
| 38 | |
| 39 | struct hdmi_disp_mode_timing_type hdmi_timing_default = { |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 40 | .height = 1080, |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 41 | .hsync_porch_fp = 88, |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 42 | .hsync_width = 44, |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 43 | .hsync_porch_bp = 148, |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 44 | .width = 1920, |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 45 | .vsync_porch_fp = 4, |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 46 | .vsync_width = 5, |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 47 | .vsync_porch_bp = 36, |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 48 | .bpp = 24, |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 49 | }; |
| 50 | |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 51 | static uint8_t hdmi_msm_avi_iframe_lut[][16] = { |
| 52 | /* 480p60 480i60 576p50 576i50 720p60 720p50 1080p60 1080i60 1080p50 |
| 53 | 1080i50 1080p24 1080p30 1080p25 640x480p 480p60_16_9 576p50_4_3 */ |
| 54 | {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, |
| 55 | 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10}, /*00*/ |
| 56 | {0x18, 0x18, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, |
| 57 | 0x28, 0x28, 0x28, 0x28, 0x18, 0x28, 0x18}, /*01*/ |
| 58 | {0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, |
| 59 | 0x04, 0x04, 0x04, 0x04, 0x88, 0x00, 0x04}, /*02*/ |
| 60 | {0x02, 0x06, 0x11, 0x15, 0x04, 0x13, 0x10, 0x05, 0x1F, |
| 61 | 0x14, 0x20, 0x22, 0x21, 0x01, 0x03, 0x11}, /*03*/ |
| 62 | {0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 63 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*04*/ |
| 64 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 65 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*05*/ |
| 66 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 67 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*06*/ |
| 68 | {0xE1, 0xE1, 0x41, 0x41, 0xD1, 0xd1, 0x39, 0x39, 0x39, |
| 69 | 0x39, 0x39, 0x39, 0x39, 0xe1, 0xE1, 0x41}, /*07*/ |
| 70 | {0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x04, 0x04, 0x04, |
| 71 | 0x04, 0x04, 0x04, 0x04, 0x01, 0x01, 0x02}, /*08*/ |
| 72 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 73 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*09*/ |
| 74 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 75 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*10*/ |
| 76 | {0xD1, 0xD1, 0xD1, 0xD1, 0x01, 0x01, 0x81, 0x81, 0x81, |
| 77 | 0x81, 0x81, 0x81, 0x81, 0x81, 0xD1, 0xD1}, /*11*/ |
| 78 | {0x02, 0x02, 0x02, 0x02, 0x05, 0x05, 0x07, 0x07, 0x07, |
| 79 | 0x07, 0x07, 0x07, 0x07, 0x02, 0x02, 0x02} /*12*/ |
| 80 | }; |
| 81 | |
| 82 | void hdmi_msm_set_mode(int on) |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 83 | { |
| 84 | uint32_t val = 0; |
| 85 | if (on) { |
| 86 | val |= 0x00000003; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 87 | writel(val, HDMI_CTRL); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 88 | } else { |
| 89 | val &= ~0x00000002; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 90 | writel(val, HDMI_CTRL); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 91 | } |
| 92 | } |
| 93 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 94 | struct hdmi_disp_mode_timing_type *hdmi_common_init_panel_info() |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 95 | { |
| 96 | return &hdmi_timing_default; |
| 97 | } |
| 98 | |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 99 | void hdmi_set_fb_addr(void *addr) |
| 100 | { |
| 101 | hdmi_timing_default.base = addr; |
| 102 | } |
| 103 | |
| 104 | void hdmi_msm_panel_init(struct msm_panel_info *pinfo) |
| 105 | { |
| 106 | if (!pinfo) |
| 107 | return; |
| 108 | |
| 109 | pinfo->xres = hdmi_timing_default.width; |
| 110 | pinfo->yres = hdmi_timing_default.height; |
| 111 | pinfo->bpp = hdmi_timing_default.bpp; |
| 112 | pinfo->type = HDMI_PANEL; |
| 113 | |
| 114 | pinfo->hdmi.h_back_porch = hdmi_timing_default.hsync_porch_bp; |
| 115 | pinfo->hdmi.h_front_porch = hdmi_timing_default.hsync_porch_fp; |
| 116 | pinfo->hdmi.h_pulse_width = hdmi_timing_default.hsync_width; |
| 117 | pinfo->hdmi.v_back_porch = hdmi_timing_default.vsync_porch_bp; |
| 118 | pinfo->hdmi.v_front_porch = hdmi_timing_default.vsync_porch_fp; |
| 119 | pinfo->hdmi.v_pulse_width = hdmi_timing_default.vsync_width; |
| 120 | } |
| 121 | |
| 122 | void hdmi_frame_ctrl_reg() |
| 123 | { |
| 124 | uint32_t hdmi_frame_ctrl; |
| 125 | |
| 126 | hdmi_frame_ctrl = ((0 << 31) & 0x80000000); |
| 127 | hdmi_frame_ctrl |= ((0 << 29) & 0x20000000); |
| 128 | hdmi_frame_ctrl |= ((0 << 28) & 0x10000000); |
| 129 | writel(hdmi_frame_ctrl, HDMI_FRAME_CTRL); |
| 130 | } |
| 131 | |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 132 | void hdmi_video_setup() |
| 133 | { |
| 134 | uint32_t hsync_total = 0; |
| 135 | uint32_t vsync_total = 0; |
| 136 | uint32_t hsync_start = 0; |
| 137 | uint32_t hsync_end = 0; |
| 138 | uint32_t vsync_start = 0; |
| 139 | uint32_t vsync_end = 0; |
| 140 | uint32_t hvsync_total = 0; |
| 141 | uint32_t hsync_active = 0; |
| 142 | uint32_t vsync_active = 0; |
| 143 | uint32_t hdmi_frame_ctrl = 0; |
| 144 | uint32_t val; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 145 | struct hdmi_disp_mode_timing_type *hdmi_timing = |
| 146 | hdmi_common_init_panel_info(); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 147 | |
| 148 | hsync_total = hdmi_timing->width + hdmi_timing->hsync_porch_fp |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 149 | + hdmi_timing->hsync_porch_bp + hdmi_timing->hsync_width - 1; |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 150 | vsync_total = hdmi_timing->height + hdmi_timing->vsync_porch_fp |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 151 | + hdmi_timing->vsync_porch_bp + hdmi_timing->vsync_width - 1; |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 152 | |
| 153 | hvsync_total = (vsync_total << 16) & 0x0FFF0000; |
| 154 | hvsync_total |= (hsync_total << 0) & 0x00000FFF; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 155 | writel(hvsync_total, HDMI_TOTAL); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 156 | |
| 157 | hsync_start = hdmi_timing->hsync_porch_bp + hdmi_timing->hsync_width; |
| 158 | hsync_end = (hsync_total + 1) - hdmi_timing->hsync_porch_fp; |
| 159 | hsync_active = (hsync_end << 16) & 0x0FFF0000; |
| 160 | hsync_active |= (hsync_start << 0) & 0x00000FFF; |
| 161 | writel(hsync_active, HDMI_ACTIVE_HSYNC); |
| 162 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 163 | vsync_start = |
| 164 | hdmi_timing->vsync_porch_bp + hdmi_timing->vsync_width - 1; |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 165 | vsync_end = vsync_total - hdmi_timing->vsync_porch_fp; |
| 166 | vsync_active = (vsync_end << 16) & 0x0FFF0000; |
| 167 | vsync_active |= (vsync_start << 0) & 0x00000FFF; |
| 168 | writel(vsync_active, HDMI_ACTIVE_VSYNC); |
| 169 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 170 | writel(0, HDMI_VSYNC_TOTAL_F2); |
| 171 | writel(0, HDMI_VSYNC_ACTIVE_F2); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 172 | hdmi_frame_ctrl_reg(); |
| 173 | } |
| 174 | |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 175 | void hdmi_msm_avi_info_frame(void) |
| 176 | { |
| 177 | /* two header + length + 13 data */ |
| 178 | uint8_t aviInfoFrame[16]; |
| 179 | uint8_t checksum; |
| 180 | uint32_t sum; |
| 181 | uint32_t regVal; |
| 182 | uint8_t i; |
| 183 | uint8_t mode = 6; //HDMI_VFRMT_1920x1080p60_16_9 |
| 184 | |
| 185 | /* InfoFrame Type = 82 */ |
| 186 | aviInfoFrame[0] = 0x82; |
| 187 | /* Version = 2 */ |
| 188 | aviInfoFrame[1] = 2; |
| 189 | /* Length of AVI InfoFrame = 13 */ |
| 190 | aviInfoFrame[2] = 13; |
| 191 | |
| 192 | /* Data Byte 01: 0 Y1 Y0 A0 B1 B0 S1 S0 */ |
| 193 | aviInfoFrame[3] = hdmi_msm_avi_iframe_lut[0][mode]; |
| 194 | |
| 195 | /* Setting underscan bit */ |
| 196 | aviInfoFrame[3] |= 0x02; |
| 197 | |
| 198 | /* Data Byte 02: C1 C0 M1 M0 R3 R2 R1 R0 */ |
| 199 | aviInfoFrame[4] = hdmi_msm_avi_iframe_lut[1][mode]; |
| 200 | /* Data Byte 03: ITC EC2 EC1 EC0 Q1 Q0 SC1 SC0 */ |
| 201 | aviInfoFrame[5] = hdmi_msm_avi_iframe_lut[2][mode]; |
| 202 | /* Data Byte 04: 0 VIC6 VIC5 VIC4 VIC3 VIC2 VIC1 VIC0 */ |
| 203 | aviInfoFrame[6] = hdmi_msm_avi_iframe_lut[3][mode]; |
| 204 | /* Data Byte 05: 0 0 0 0 PR3 PR2 PR1 PR0 */ |
| 205 | aviInfoFrame[7] = hdmi_msm_avi_iframe_lut[4][mode]; |
| 206 | /* Data Byte 06: LSB Line No of End of Top Bar */ |
| 207 | aviInfoFrame[8] = hdmi_msm_avi_iframe_lut[5][mode]; |
| 208 | /* Data Byte 07: MSB Line No of End of Top Bar */ |
| 209 | aviInfoFrame[9] = hdmi_msm_avi_iframe_lut[6][mode]; |
| 210 | /* Data Byte 08: LSB Line No of Start of Bottom Bar */ |
| 211 | aviInfoFrame[10] = hdmi_msm_avi_iframe_lut[7][mode]; |
| 212 | /* Data Byte 09: MSB Line No of Start of Bottom Bar */ |
| 213 | aviInfoFrame[11] = hdmi_msm_avi_iframe_lut[8][mode]; |
| 214 | /* Data Byte 10: LSB Pixel Number of End of Left Bar */ |
| 215 | aviInfoFrame[12] = hdmi_msm_avi_iframe_lut[9][mode]; |
| 216 | /* Data Byte 11: MSB Pixel Number of End of Left Bar */ |
| 217 | aviInfoFrame[13] = hdmi_msm_avi_iframe_lut[10][mode]; |
| 218 | /* Data Byte 12: LSB Pixel Number of Start of Right Bar */ |
| 219 | aviInfoFrame[14] = hdmi_msm_avi_iframe_lut[11][mode]; |
| 220 | /* Data Byte 13: MSB Pixel Number of Start of Right Bar */ |
| 221 | aviInfoFrame[15] = hdmi_msm_avi_iframe_lut[12][mode]; |
| 222 | |
| 223 | sum = 0; |
| 224 | for (i = 0; i < 16; i++) |
| 225 | sum += aviInfoFrame[i]; |
| 226 | sum &= 0xFF; |
| 227 | sum = 256 - sum; |
| 228 | checksum = (uint8_t) sum; |
| 229 | |
| 230 | regVal = aviInfoFrame[5]; |
| 231 | regVal = regVal << 8 | aviInfoFrame[4]; |
| 232 | regVal = regVal << 8 | aviInfoFrame[3]; |
| 233 | regVal = regVal << 8 | checksum; |
| 234 | writel(regVal, MSM_HDMI_BASE + 0x006C); |
| 235 | |
| 236 | regVal = aviInfoFrame[9]; |
| 237 | regVal = regVal << 8 | aviInfoFrame[8]; |
| 238 | regVal = regVal << 8 | aviInfoFrame[7]; |
| 239 | regVal = regVal << 8 | aviInfoFrame[6]; |
| 240 | writel(regVal, MSM_HDMI_BASE + 0x0070); |
| 241 | |
| 242 | regVal = aviInfoFrame[13]; |
| 243 | regVal = regVal << 8 | aviInfoFrame[12]; |
| 244 | regVal = regVal << 8 | aviInfoFrame[11]; |
| 245 | regVal = regVal << 8 | aviInfoFrame[10]; |
| 246 | writel(regVal, MSM_HDMI_BASE + 0x0074); |
| 247 | |
| 248 | regVal = aviInfoFrame[1]; |
| 249 | regVal = regVal << 16 | aviInfoFrame[15]; |
| 250 | regVal = regVal << 8 | aviInfoFrame[14]; |
| 251 | writel(regVal, MSM_HDMI_BASE + 0x0078); |
| 252 | |
| 253 | /* INFOFRAME_CTRL0[0x002C] */ |
| 254 | /* 0x3 for AVI InfFrame enable (every frame) */ |
| 255 | writel(readl(0x002C) | 0x00000003L, MSM_HDMI_BASE + 0x002C); |
| 256 | } |
| 257 | |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 258 | void hdmi_app_clk_init(int on) |
| 259 | { |
| 260 | uint32_t val = 0; |
| 261 | if (on) { |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 262 | /* Enable hdmi apps clock */ |
| 263 | val = readl(MISC_CC2_REG); |
| 264 | val = BIT(11); |
| 265 | writel(val, MISC_CC2_REG); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 266 | udelay(10); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 267 | |
| 268 | /* Enable hdmi master clock */ |
| 269 | val = readl(MMSS_AHB_EN_REG); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 270 | val |= BIT(14); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 271 | writel(val, MMSS_AHB_EN_REG); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 272 | udelay(10); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 273 | |
| 274 | /* Enable hdmi slave clock */ |
| 275 | val = readl(MMSS_AHB_EN_REG); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 276 | val |= BIT(4); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 277 | writel(val, MMSS_AHB_EN_REG); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 278 | udelay(10); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 279 | } else { |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 280 | // Disable clocks |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 281 | val = readl(MISC_CC2_REG); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 282 | val &= ~(BIT(11)); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 283 | writel(val, MISC_CC2_REG); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 284 | udelay(10); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 285 | val = readl(MMSS_AHB_EN_REG); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 286 | val &= ~(BIT(14)); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 287 | writel(val, MMSS_AHB_EN_REG); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 288 | udelay(10); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 289 | val = readl(MMSS_AHB_EN_REG); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 290 | val &= ~(BIT(4)); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 291 | writel(val, MMSS_AHB_EN_REG); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 292 | udelay(10); |
| 293 | } |
| 294 | } |
| 295 | |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 296 | int hdmi_msm_turn_on(void) |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 297 | { |
| 298 | uint32_t hotplug_control; |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 299 | |
| 300 | hdmi_msm_set_mode(0); |
| 301 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 302 | hdmi_msm_reset_core(); // Reset the core |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 303 | hdmi_msm_init_phy(); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 304 | |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 305 | // Enable USEC REF timer |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 306 | writel(0x0001001B, HDMI_USEC_REFTIMER); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 307 | |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 308 | // Write 1 to HDMI_CTRL to enable HDMI |
| 309 | hdmi_msm_set_mode(1); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 310 | |
| 311 | // Video setup for HDMI |
| 312 | hdmi_video_setup(); |
| 313 | |
| 314 | // AVI info setup |
| 315 | hdmi_msm_avi_info_frame(); |
| 316 | |
| 317 | return 0; |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 318 | } |
| 319 | |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 320 | int hdmi_dtv_init() |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 321 | { |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 322 | uint32_t hsync_period; |
| 323 | uint32_t hsync_ctrl; |
| 324 | uint32_t hsync_start_x; |
| 325 | uint32_t hsync_end_x; |
| 326 | uint32_t display_hctl; |
| 327 | uint32_t vsync_period; |
| 328 | uint32_t display_v_start; |
| 329 | uint32_t display_v_end; |
| 330 | uint32_t hsync_polarity; |
| 331 | uint32_t vsync_polarity; |
| 332 | uint32_t data_en_polarity; |
| 333 | uint32_t ctrl_polarity; |
| 334 | uint32_t dtv_border_clr = 0; |
| 335 | uint32_t dtv_underflow_clr = 0; |
| 336 | uint32_t active_v_start = 0; |
| 337 | uint32_t active_v_end = 0; |
| 338 | uint32_t dtv_hsync_skew = 0; |
| 339 | uint32_t intf, stage, snum, mask, data; |
| 340 | unsigned char *rgb_base; |
| 341 | unsigned char *overlay_base; |
| 342 | uint32_t val; |
| 343 | |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 344 | struct hdmi_disp_mode_timing_type *timing = |
| 345 | hdmi_common_init_panel_info(); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 346 | |
| 347 | // MDP E config |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 348 | writel((unsigned)timing->base, MDP_BASE + 0xb0008); //FB Address |
| 349 | writel(((timing->height << 16) | timing->width), MDP_BASE + 0xb0004); |
| 350 | writel((timing->width * timing->bpp / 8), MDP_BASE + 0xb000c); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 351 | writel(0, MDP_BASE + 0xb0010); |
| 352 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 353 | writel(DMA_PACK_PATTERN_RGB | DMA_DSTC0G_8BITS | DMA_DSTC1B_8BITS | |
| 354 | DMA_DSTC2R_8BITS, MDP_BASE + 0xb0000); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 355 | writel(0xff0000, MDP_BASE + 0xb0070); |
| 356 | writel(0xff0000, MDP_BASE + 0xb0074); |
| 357 | writel(0xff0000, MDP_BASE + 0xb0078); |
| 358 | |
| 359 | // overlay rgb setup RGB2 |
| 360 | rgb_base = MDP_BASE + MDP4_RGB_BASE; |
| 361 | rgb_base += (MDP4_RGB_OFF * 1); |
| 362 | writel(((timing->height << 16) | timing->width), rgb_base + 0x0000); |
| 363 | writel(0x0, rgb_base + 0x0004); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 364 | writel(((timing->height << 16) | timing->width), rgb_base + 0x0008); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 365 | writel(0x0, rgb_base + 0x000c); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 366 | writel(timing->base, rgb_base + 0x0010); //FB address |
| 367 | writel((timing->width * timing->bpp / 8), rgb_base + 0x0040); |
| 368 | writel(0x2443F, rgb_base + 0x0050); //format |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 369 | writel(0x20001, rgb_base + 0x0054); //pattern |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 370 | writel(0x0, rgb_base + 0x0058); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 371 | writel(0x20000000, rgb_base + 0x005c); //phaseX |
| 372 | writel(0x20000000, rgb_base + 0x0060); // phaseY |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 373 | |
| 374 | // mdp4 mixer setup MDP4_MIXER1 |
| 375 | data = readl(MDP_BASE + 0x10100); |
| 376 | stage = 9; |
| 377 | snum = 12; |
| 378 | mask = 0x0f; |
| 379 | mask <<= snum; |
| 380 | stage <<= snum; |
| 381 | data &= ~mask; |
| 382 | data |= stage; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 383 | writel(data, MDP_BASE + 0x10100); // Overlay CFG conf |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 384 | data = readl(MDP_BASE + 0x10100); |
| 385 | |
| 386 | // Overlay cfg |
| 387 | overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE; |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 388 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 389 | writel(0x0, MDP_BASE + 0x0038); //EXternal interface select |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 390 | |
| 391 | data = ((timing->height << 16) | timing->width); |
| 392 | writel(data, overlay_base + 0x0008); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 393 | writel(timing->base, overlay_base + 0x000c); |
| 394 | writel((timing->width * timing->bpp / 8), overlay_base + 0x0010); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 395 | writel(0x10, overlay_base + 0x104); |
| 396 | writel(0x10, overlay_base + 0x124); |
| 397 | writel(0x10, overlay_base + 0x144); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 398 | writel(0x01, overlay_base + 0x0004); /* directout */ |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 399 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 400 | hsync_period = |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 401 | timing->hsync_width + timing->hsync_porch_bp + timing->width + |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 402 | timing->hsync_porch_fp; |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 403 | hsync_ctrl = (hsync_period << 16) | timing->hsync_width; |
| 404 | hsync_start_x = timing->hsync_width + timing->hsync_porch_bp; |
| 405 | hsync_end_x = hsync_period - timing->hsync_porch_fp - 1; |
| 406 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 407 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 408 | vsync_period = |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 409 | (timing->vsync_width + timing->vsync_porch_bp + timing->height + |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 410 | timing->vsync_porch_fp) * hsync_period; |
| 411 | display_v_start = |
| 412 | (timing->vsync_width + timing->vsync_porch_bp) * hsync_period; |
| 413 | display_v_end = |
| 414 | vsync_period - (timing->vsync_porch_bp * hsync_period) - 1; |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 415 | |
| 416 | dtv_underflow_clr |= 0x80000000; |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 417 | hsync_polarity = 0; |
| 418 | vsync_polarity = 0; |
| 419 | data_en_polarity = 0; |
| 420 | ctrl_polarity = |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 421 | (data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 422 | |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 423 | writel(hsync_ctrl, MDP_BASE + DTV_BASE + 0x4); |
| 424 | writel(vsync_period, MDP_BASE + DTV_BASE + 0x8); |
| 425 | writel(timing->vsync_width * hsync_period, |
| 426 | MDP_BASE + DTV_BASE + 0xc); |
| 427 | writel(display_hctl, MDP_BASE + DTV_BASE + 0x18); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 428 | writel(display_v_start, MDP_BASE + DTV_BASE + 0x1c); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 429 | writel(0x25a197, MDP_BASE + DTV_BASE + 0x20); |
| 430 | writel(dtv_border_clr, MDP_BASE + DTV_BASE + 0x40); |
| 431 | writel(0x8fffffff, MDP_BASE + DTV_BASE + 0x44); |
| 432 | writel(dtv_hsync_skew, MDP_BASE + DTV_BASE + 0x48); |
| 433 | writel(ctrl_polarity, MDP_BASE + DTV_BASE + 0x50); |
| 434 | writel(0x0, MDP_BASE + DTV_BASE + 0x2c); |
| 435 | writel(active_v_start, MDP_BASE + DTV_BASE + 0x30); |
| 436 | writel(active_v_end, MDP_BASE + DTV_BASE + 0x38); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 437 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 438 | /* Enable DTV block */ |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 439 | writel(0x01, MDP_BASE + DTV_BASE); |
| 440 | |
| 441 | /* Flush mixer/pipes configurations */ |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 442 | val = BIT(1); |
| 443 | val |= BIT(5); |
| 444 | writel(val, MDP_BASE + 0x18000); |
Ajay Singh Parmar | 7c1cd52 | 2013-02-13 20:33:49 +0530 | [diff] [blame] | 445 | |
| 446 | return 0; |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 447 | } |
| 448 | |
| 449 | void hdmi_display_shutdown() |
| 450 | { |
| 451 | writel(0x0, MDP_BASE + DTV_BASE); |
| 452 | writel(0x8, MDP_BASE + 0x0038); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 453 | writel(0x0, MDP_BASE + 0x10100); |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 454 | } |