Deepa Dinamani | 554b062 | 2013-05-16 15:00:30 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2013, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
| 42 | #define cxo_mm_source_val 0 |
| 43 | #define mmpll0_mm_source_val 1 |
| 44 | #define mmpll1_mm_source_val 2 |
| 45 | #define mmpll3_mm_source_val 3 |
| 46 | #define gpll0_mm_source_val 5 |
| 47 | |
| 48 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 49 | |
| 50 | |
| 51 | /* Clock Operations */ |
| 52 | static struct clk_ops clk_ops_branch = |
| 53 | { |
| 54 | .enable = clock_lib2_branch_clk_enable, |
| 55 | .disable = clock_lib2_branch_clk_disable, |
| 56 | .set_rate = clock_lib2_branch_set_rate, |
| 57 | }; |
| 58 | |
| 59 | static struct clk_ops clk_ops_rcg_mnd = |
| 60 | { |
| 61 | .enable = clock_lib2_rcg_enable, |
| 62 | .set_rate = clock_lib2_rcg_set_rate, |
| 63 | }; |
| 64 | |
| 65 | static struct clk_ops clk_ops_rcg = |
| 66 | { |
| 67 | .enable = clock_lib2_rcg_enable, |
| 68 | .set_rate = clock_lib2_rcg_set_rate, |
| 69 | }; |
| 70 | |
| 71 | static struct clk_ops clk_ops_cxo = |
| 72 | { |
| 73 | .enable = cxo_clk_enable, |
| 74 | .disable = cxo_clk_disable, |
| 75 | }; |
| 76 | |
| 77 | static struct clk_ops clk_ops_pll_vote = |
| 78 | { |
| 79 | .enable = pll_vote_clk_enable, |
| 80 | .disable = pll_vote_clk_disable, |
| 81 | .auto_off = pll_vote_clk_disable, |
| 82 | .is_enabled = pll_vote_clk_is_enabled, |
| 83 | }; |
| 84 | |
| 85 | static struct clk_ops clk_ops_vote = |
| 86 | { |
| 87 | .enable = clock_lib2_vote_clk_enable, |
| 88 | .disable = clock_lib2_vote_clk_disable, |
| 89 | }; |
| 90 | |
| 91 | /* Clock Sources */ |
| 92 | static struct fixed_clk cxo_clk_src = |
| 93 | { |
| 94 | .c = { |
| 95 | .rate = 19200000, |
| 96 | .dbg_name = "cxo_clk_src", |
| 97 | .ops = &clk_ops_cxo, |
| 98 | }, |
| 99 | }; |
| 100 | |
Sundarajan Srinivasan | 09374ed | 2013-06-18 13:29:32 -0700 | [diff] [blame] | 101 | static struct pll_vote_clk gpll0_clk_src = |
| 102 | { |
| 103 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 104 | .en_mask = BIT(0), |
| 105 | .status_reg = (void *) GPLL0_STATUS, |
| 106 | .status_mask = BIT(17), |
| 107 | .parent = &cxo_clk_src.c, |
| 108 | |
| 109 | .c = { |
| 110 | .rate = 600000000, |
| 111 | .dbg_name = "gpll0_clk_src", |
| 112 | .ops = &clk_ops_pll_vote, |
| 113 | }, |
| 114 | }; |
| 115 | |
| 116 | /* UART Clocks */ |
| 117 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = |
| 118 | { |
| 119 | F( 3686400, gpll0, 1, 96, 15625), |
| 120 | F( 7372800, gpll0, 1, 192, 15625), |
| 121 | F(14745600, gpll0, 1, 384, 15625), |
| 122 | F(16000000, gpll0, 5, 2, 15), |
| 123 | F(19200000, cxo, 1, 0, 0), |
| 124 | F(24000000, gpll0, 5, 1, 5), |
| 125 | F(32000000, gpll0, 1, 4, 75), |
| 126 | F(40000000, gpll0, 15, 0, 0), |
| 127 | F(46400000, gpll0, 1, 29, 375), |
| 128 | F(48000000, gpll0, 12.5, 0, 0), |
| 129 | F(51200000, gpll0, 1, 32, 375), |
| 130 | F(56000000, gpll0, 1, 7, 75), |
| 131 | F(58982400, gpll0, 1, 1536, 15625), |
| 132 | F(60000000, gpll0, 10, 0, 0), |
| 133 | F_END |
| 134 | }; |
| 135 | |
| 136 | static struct rcg_clk blsp1_uart2_apps_clk_src = |
| 137 | { |
| 138 | .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR, |
| 139 | .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR, |
| 140 | .m_reg = (uint32_t *) BLSP1_UART2_APPS_M, |
| 141 | .n_reg = (uint32_t *) BLSP1_UART2_APPS_N, |
| 142 | .d_reg = (uint32_t *) BLSP1_UART2_APPS_D, |
| 143 | |
| 144 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 145 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 146 | .current_freq = &rcg_dummy_freq, |
| 147 | |
| 148 | .c = { |
| 149 | .dbg_name = "blsp1_uart2_apps_clk", |
| 150 | .ops = &clk_ops_rcg_mnd, |
| 151 | }, |
| 152 | }; |
| 153 | |
| 154 | static struct branch_clk gcc_blsp1_uart2_apps_clk = |
| 155 | { |
| 156 | .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR, |
| 157 | .parent = &blsp1_uart2_apps_clk_src.c, |
| 158 | |
| 159 | .c = { |
| 160 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 161 | .ops = &clk_ops_branch, |
| 162 | }, |
| 163 | }; |
| 164 | |
| 165 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 166 | .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR, |
| 167 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 168 | .en_mask = BIT(17), |
| 169 | |
| 170 | .c = { |
| 171 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 172 | .ops = &clk_ops_vote, |
| 173 | }, |
| 174 | }; |
| 175 | |
| 176 | static struct vote_clk gcc_blsp2_ahb_clk = { |
| 177 | .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR, |
| 178 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 179 | .en_mask = BIT(15), |
| 180 | |
| 181 | .c = { |
| 182 | .dbg_name = "gcc_blsp2_ahb_clk", |
| 183 | .ops = &clk_ops_vote, |
| 184 | }, |
| 185 | }; |
| 186 | |
| 187 | /* USB Clocks */ |
| 188 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = |
| 189 | { |
| 190 | F(75000000, gpll0, 8, 0, 0), |
| 191 | F_END |
| 192 | }; |
| 193 | |
| 194 | static struct rcg_clk usb_hs_system_clk_src = |
| 195 | { |
| 196 | .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR, |
| 197 | .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR, |
| 198 | |
| 199 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 200 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 201 | .current_freq = &rcg_dummy_freq, |
| 202 | |
| 203 | .c = { |
| 204 | .dbg_name = "usb_hs_system_clk", |
| 205 | .ops = &clk_ops_rcg, |
| 206 | }, |
| 207 | }; |
| 208 | |
| 209 | static struct branch_clk gcc_usb_hs_system_clk = |
| 210 | { |
| 211 | .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR, |
| 212 | .parent = &usb_hs_system_clk_src.c, |
| 213 | |
| 214 | .c = { |
| 215 | .dbg_name = "gcc_usb_hs_system_clk", |
| 216 | .ops = &clk_ops_branch, |
| 217 | }, |
| 218 | }; |
| 219 | |
| 220 | static struct branch_clk gcc_usb_hs_ahb_clk = |
| 221 | { |
| 222 | .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR, |
| 223 | .has_sibling = 1, |
| 224 | |
| 225 | .c = { |
| 226 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 227 | .ops = &clk_ops_branch, |
| 228 | }, |
| 229 | }; |
| 230 | |
| 231 | /* SDCC Clocks */ |
| 232 | static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] = |
| 233 | { |
| 234 | F( 144000, cxo, 16, 3, 25), |
| 235 | F( 400000, cxo, 12, 1, 4), |
| 236 | F( 20000000, gpll0, 15, 1, 2), |
| 237 | F( 25000000, gpll0, 12, 1, 2), |
| 238 | F( 50000000, gpll0, 12, 0, 0), |
| 239 | F(100000000, gpll0, 6, 0, 0), |
| 240 | F(200000000, gpll0, 3, 0, 0), |
| 241 | F_END |
| 242 | }; |
| 243 | |
| 244 | static struct rcg_clk sdcc1_apps_clk_src = |
| 245 | { |
| 246 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 247 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 248 | .m_reg = (uint32_t *) SDCC1_M, |
| 249 | .n_reg = (uint32_t *) SDCC1_N, |
| 250 | .d_reg = (uint32_t *) SDCC1_D, |
| 251 | |
| 252 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 253 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 254 | .current_freq = &rcg_dummy_freq, |
| 255 | |
| 256 | .c = { |
| 257 | .dbg_name = "sdc1_clk", |
| 258 | .ops = &clk_ops_rcg_mnd, |
| 259 | }, |
| 260 | }; |
| 261 | |
| 262 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 263 | { |
| 264 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 265 | .parent = &sdcc1_apps_clk_src.c, |
| 266 | |
| 267 | .c = { |
| 268 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 269 | .ops = &clk_ops_branch, |
| 270 | }, |
| 271 | }; |
| 272 | |
| 273 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 274 | { |
| 275 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 276 | .has_sibling = 1, |
| 277 | |
| 278 | .c = { |
| 279 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 280 | .ops = &clk_ops_branch, |
| 281 | }, |
| 282 | }; |
| 283 | |
Dhaval Patel | 6dee7ff | 2013-10-18 19:02:37 -0700 | [diff] [blame] | 284 | /* Display clocks */ |
| 285 | static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = { |
| 286 | F_MM(19200000, cxo, 1, 0, 0), |
| 287 | F_END |
| 288 | }; |
| 289 | |
| 290 | static struct clk_freq_tbl ftbl_mdss_esc1_1_clk[] = { |
| 291 | F_MM(19200000, cxo, 1, 0, 0), |
| 292 | F_END |
| 293 | }; |
| 294 | |
| 295 | static struct clk_freq_tbl ftbl_mmss_axi_clk[] = { |
| 296 | F_MM(19200000, cxo, 1, 0, 0), |
| 297 | F_MM(100000000, gpll0, 6, 0, 0), |
| 298 | F_END |
| 299 | }; |
| 300 | |
| 301 | static struct clk_freq_tbl ftbl_mdp_clk[] = { |
| 302 | F_MM( 75000000, gpll0, 8, 0, 0), |
| 303 | F_MM( 240000000, gpll0, 2.5, 0, 0), |
| 304 | F_END |
| 305 | }; |
| 306 | |
| 307 | static struct rcg_clk dsi_esc0_clk_src = { |
| 308 | .cmd_reg = (uint32_t *) DSI_ESC0_CMD_RCGR, |
| 309 | .cfg_reg = (uint32_t *) DSI_ESC0_CFG_RCGR, |
| 310 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 311 | .freq_tbl = ftbl_mdss_esc0_1_clk, |
| 312 | |
| 313 | .c = { |
| 314 | .dbg_name = "dsi_esc0_clk_src", |
| 315 | .ops = &clk_ops_rcg, |
| 316 | }, |
| 317 | }; |
| 318 | |
| 319 | static struct rcg_clk dsi_esc1_clk_src = { |
| 320 | .cmd_reg = (uint32_t *) DSI_ESC1_CMD_RCGR, |
| 321 | .cfg_reg = (uint32_t *) DSI_ESC1_CFG_RCGR, |
| 322 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 323 | .freq_tbl = ftbl_mdss_esc1_1_clk, |
| 324 | |
| 325 | .c = { |
| 326 | .dbg_name = "dsi_esc1_clk_src", |
| 327 | .ops = &clk_ops_rcg, |
| 328 | }, |
| 329 | }; |
| 330 | |
| 331 | static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = { |
| 332 | F_MM(19200000, cxo, 1, 0, 0), |
| 333 | F_END |
| 334 | }; |
| 335 | |
| 336 | static struct rcg_clk vsync_clk_src = { |
| 337 | .cmd_reg = (uint32_t *) VSYNC_CMD_RCGR, |
| 338 | .cfg_reg = (uint32_t *) VSYNC_CFG_RCGR, |
| 339 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 340 | .freq_tbl = ftbl_mdss_vsync_clk, |
| 341 | |
| 342 | .c = { |
| 343 | .dbg_name = "vsync_clk_src", |
| 344 | .ops = &clk_ops_rcg, |
| 345 | }, |
| 346 | }; |
| 347 | |
| 348 | static struct rcg_clk mdp_axi_clk_src = { |
| 349 | .cmd_reg = (uint32_t *) MDP_AXI_CMD_RCGR, |
| 350 | .cfg_reg = (uint32_t *) MDP_AXI_CFG_RCGR, |
| 351 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 352 | .freq_tbl = ftbl_mmss_axi_clk, |
| 353 | |
| 354 | .c = { |
| 355 | .dbg_name = "mdp_axi_clk_src", |
| 356 | .ops = &clk_ops_rcg, |
| 357 | }, |
| 358 | }; |
| 359 | |
| 360 | static struct branch_clk mdss_esc0_clk = { |
| 361 | .cbcr_reg = (uint32_t *) DSI_ESC0_CBCR, |
| 362 | .parent = &dsi_esc0_clk_src.c, |
| 363 | .has_sibling = 0, |
| 364 | |
| 365 | .c = { |
| 366 | .dbg_name = "mdss_esc0_clk", |
| 367 | .ops = &clk_ops_branch, |
| 368 | }, |
| 369 | }; |
| 370 | |
| 371 | static struct branch_clk mdss_esc1_clk = { |
| 372 | .cbcr_reg = (uint32_t *) DSI_ESC1_CBCR, |
| 373 | .parent = &dsi_esc1_clk_src.c, |
| 374 | .has_sibling = 0, |
| 375 | |
| 376 | .c = { |
| 377 | .dbg_name = "mdss_esc1_clk", |
| 378 | .ops = &clk_ops_branch, |
| 379 | }, |
| 380 | }; |
| 381 | |
| 382 | static struct branch_clk mdss_axi_clk = { |
| 383 | .cbcr_reg = (uint32_t *) MDP_AXI_CBCR, |
| 384 | .parent = &mdp_axi_clk_src.c, |
| 385 | .has_sibling = 0, |
| 386 | |
| 387 | .c = { |
| 388 | .dbg_name = "mdss_axi_clk", |
| 389 | .ops = &clk_ops_branch, |
| 390 | }, |
| 391 | }; |
| 392 | |
| 393 | static struct branch_clk mmss_mmssnoc_axi_clk = { |
| 394 | .cbcr_reg = (uint32_t *) MMSS_MMSSNOC_AXI_CBCR, |
| 395 | .parent = &mdp_axi_clk_src.c, |
| 396 | .has_sibling = 0, |
| 397 | |
| 398 | .c = { |
| 399 | .dbg_name = "mmss_mmssnoc_axi_clk", |
| 400 | .ops = &clk_ops_branch, |
| 401 | }, |
| 402 | }; |
| 403 | |
| 404 | static struct branch_clk mmss_s0_axi_clk = { |
| 405 | .cbcr_reg = (uint32_t *) MMSS_S0_AXI_CBCR, |
| 406 | .parent = &mdp_axi_clk_src.c, |
| 407 | .has_sibling = 0, |
| 408 | |
| 409 | .c = { |
| 410 | .dbg_name = "mmss_s0_axi_clk", |
| 411 | .ops = &clk_ops_branch, |
| 412 | }, |
| 413 | }; |
| 414 | |
| 415 | static struct branch_clk mdp_ahb_clk = { |
| 416 | .cbcr_reg = (uint32_t *) MDP_AHB_CBCR, |
| 417 | .has_sibling = 1, |
| 418 | |
| 419 | .c = { |
| 420 | .dbg_name = "mdp_ahb_clk", |
| 421 | .ops = &clk_ops_branch, |
| 422 | }, |
| 423 | }; |
| 424 | |
| 425 | static struct rcg_clk mdss_mdp_clk_src = { |
| 426 | .cmd_reg = (uint32_t *) MDP_CMD_RCGR, |
| 427 | .cfg_reg = (uint32_t *) MDP_CFG_RCGR, |
| 428 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 429 | .freq_tbl = ftbl_mdp_clk, |
| 430 | .current_freq = &rcg_dummy_freq, |
| 431 | |
| 432 | .c = { |
| 433 | .dbg_name = "mdss_mdp_clk_src", |
| 434 | .ops = &clk_ops_rcg, |
| 435 | }, |
| 436 | }; |
| 437 | |
| 438 | static struct branch_clk mdss_mdp_clk = { |
| 439 | .cbcr_reg = (uint32_t *) MDP_CBCR, |
| 440 | .parent = &mdss_mdp_clk_src.c, |
| 441 | .has_sibling = 1, |
| 442 | |
| 443 | .c = { |
| 444 | .dbg_name = "mdss_mdp_clk", |
| 445 | .ops = &clk_ops_branch, |
| 446 | }, |
| 447 | }; |
| 448 | |
| 449 | static struct branch_clk mdss_mdp_lut_clk = { |
| 450 | .cbcr_reg = MDP_LUT_CBCR, |
| 451 | .parent = &mdss_mdp_clk_src.c, |
| 452 | .has_sibling = 1, |
| 453 | |
| 454 | .c = { |
| 455 | .dbg_name = "mdss_mdp_lut_clk", |
| 456 | .ops = &clk_ops_branch, |
| 457 | }, |
| 458 | }; |
| 459 | |
| 460 | static struct branch_clk mdss_vsync_clk = { |
| 461 | .cbcr_reg = MDSS_VSYNC_CBCR, |
| 462 | .parent = &vsync_clk_src.c, |
| 463 | .has_sibling = 0, |
| 464 | |
| 465 | .c = { |
| 466 | .dbg_name = "mdss_vsync_clk", |
| 467 | .ops = &clk_ops_branch, |
| 468 | }, |
| 469 | }; |
| 470 | |
| 471 | |
Deepa Dinamani | 554b062 | 2013-05-16 15:00:30 -0700 | [diff] [blame] | 472 | /* Clock lookup table */ |
| 473 | static struct clk_lookup msm_clocks_8084[] = |
| 474 | { |
Sundarajan Srinivasan | 09374ed | 2013-06-18 13:29:32 -0700 | [diff] [blame] | 475 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 476 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
Deepa Dinamani | 554b062 | 2013-05-16 15:00:30 -0700 | [diff] [blame] | 477 | |
Sundarajan Srinivasan | 09374ed | 2013-06-18 13:29:32 -0700 | [diff] [blame] | 478 | CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c), |
| 479 | CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c), |
| 480 | |
| 481 | CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c), |
| 482 | CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c), |
Dhaval Patel | 6dee7ff | 2013-10-18 19:02:37 -0700 | [diff] [blame] | 483 | |
| 484 | /* mdss clocks */ |
| 485 | CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c), |
| 486 | CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c), |
| 487 | CLK_LOOKUP("mdss_esc1_clk", mdss_esc1_clk.c), |
| 488 | CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c), |
| 489 | CLK_LOOKUP("mmss_mmssnoc_axi_clk", mmss_mmssnoc_axi_clk.c), |
| 490 | CLK_LOOKUP("mmss_s0_axi_clk", mmss_s0_axi_clk.c), |
| 491 | CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c), |
| 492 | CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c), |
| 493 | CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c), |
| 494 | CLK_LOOKUP("mdss_mdp_lut_clk", mdss_mdp_lut_clk.c), |
Sundarajan Srinivasan | 09374ed | 2013-06-18 13:29:32 -0700 | [diff] [blame] | 495 | }; |
Deepa Dinamani | 554b062 | 2013-05-16 15:00:30 -0700 | [diff] [blame] | 496 | |
| 497 | void platform_clock_init(void) |
| 498 | { |
| 499 | clk_init(msm_clocks_8084, ARRAY_SIZE(msm_clocks_8084)); |
| 500 | } |