| /include/ "skeleton.dtsi" |
| |
| / { |
| compatible = "nvidia,tegra114"; |
| interrupt-parent = <&gic>; |
| |
| gic: interrupt-controller { |
| compatible = "arm,cortex-a15-gic"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x50041000 0x1000>, |
| <0x50042000 0x1000>, |
| <0x50044000 0x2000>, |
| <0x50046000 0x2000>; |
| interrupts = <1 9 0xf04>; |
| }; |
| |
| timer@60005000 { |
| compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; |
| reg = <0x60005000 0x400>; |
| interrupts = <0 0 0x04 |
| 0 1 0x04 |
| 0 41 0x04 |
| 0 42 0x04 |
| 0 121 0x04 |
| 0 122 0x04>; |
| }; |
| |
| tegra_car: clock { |
| compatible = "nvidia,tegra114-car, nvidia,tegra30-car"; |
| reg = <0x60006000 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| ahb: ahb { |
| compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; |
| reg = <0x6000c004 0x14c>; |
| }; |
| |
| gpio: gpio { |
| compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; |
| reg = <0x6000d000 0x1000>; |
| interrupts = <0 32 0x04 |
| 0 33 0x04 |
| 0 34 0x04 |
| 0 35 0x04 |
| 0 55 0x04 |
| 0 87 0x04 |
| 0 89 0x04 |
| 0 125 0x04>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| }; |
| |
| pinmux: pinmux { |
| compatible = "nvidia,tegra114-pinmux"; |
| reg = <0x70000868 0x148 /* Pad control registers */ |
| 0x70003000 0x40c>; /* Mux registers */ |
| }; |
| |
| serial@70006000 { |
| compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006000 0x40>; |
| reg-shift = <2>; |
| interrupts = <0 36 0x04>; |
| status = "disabled"; |
| }; |
| |
| serial@70006040 { |
| compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006040 0x40>; |
| reg-shift = <2>; |
| interrupts = <0 37 0x04>; |
| status = "disabled"; |
| }; |
| |
| serial@70006200 { |
| compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006200 0x100>; |
| reg-shift = <2>; |
| interrupts = <0 46 0x04>; |
| status = "disabled"; |
| }; |
| |
| serial@70006300 { |
| compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006300 0x100>; |
| reg-shift = <2>; |
| interrupts = <0 90 0x04>; |
| status = "disabled"; |
| }; |
| |
| rtc { |
| compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; |
| reg = <0x7000e000 0x100>; |
| interrupts = <0 2 0x04>; |
| }; |
| |
| pmc { |
| compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc"; |
| reg = <0x7000e400 0x400>; |
| }; |
| |
| iommu { |
| compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; |
| reg = <0x7000f010 0x02c |
| 0x7000f1f0 0x010 |
| 0x7000f228 0x074>; |
| nvidia,#asids = <4>; |
| dma-window = <0 0x40000000>; |
| nvidia,swgroups = <0x18659fe>; |
| nvidia,ahb = <&ahb>; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0>; |
| }; |
| |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <1>; |
| }; |
| |
| cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <2>; |
| }; |
| |
| cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <3>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupts = <1 13 0xf08>, |
| <1 14 0xf08>, |
| <1 11 0xf08>, |
| <1 10 0xf08>; |
| }; |
| }; |