| /* |
| * Copyright 2013 Freescale Semiconductor, Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; either version 2 of the License, or |
| * (at your option) any later version. |
| */ |
| |
| #include "skeleton.dtsi" |
| #include "vfxxx.dtsi" |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| a5_cpu: cpu@0 { |
| compatible = "arm,cortex-a5"; |
| device_type = "cpu"; |
| reg = <0x0>; |
| }; |
| }; |
| |
| soc { |
| interrupt-parent = <&intc>; |
| |
| aips-bus@40000000 { |
| |
| intc: interrupt-controller@40002000 { |
| compatible = "arm,cortex-a9-gic"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x40003000 0x1000>, |
| <0x40002100 0x100>; |
| }; |
| |
| global_timer: timer@40002200 { |
| compatible = "arm,cortex-a9-global-timer"; |
| reg = <0x40002200 0x20>; |
| interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks VF610_CLK_PLATFORM_BUS>; |
| }; |
| }; |
| }; |
| }; |
| |
| &adc0 { |
| interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &adc1 { |
| interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &can0 { |
| interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &can1 { |
| interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &dspi0 { |
| interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &edma0 { |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "edma-tx", "edma-err"; |
| }; |
| |
| &edma1 { |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "edma-tx", "edma-err"; |
| }; |
| |
| &esdhc1 { |
| interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &fec0 { |
| interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &fec1 { |
| interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &ftm { |
| interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &gpio0 { |
| interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &gpio1 { |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &gpio2 { |
| interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &gpio3 { |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &gpio4 { |
| interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &i2c0 { |
| interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &pit { |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &qspi0 { |
| interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &sai2 { |
| interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &snvsrtc { |
| interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &src { |
| interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &uart0 { |
| interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &uart1 { |
| interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &uart2 { |
| interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &uart3 { |
| interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &uart4 { |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &uart5 { |
| interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &usbdev0 { |
| interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &usbh1 { |
| interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &usbphy0 { |
| interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &usbphy1 { |
| interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &wdoga5 { |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| status = "okay"; |
| }; |