| &soc { |
| mdss_dsi0_pll: qcom,mdss_dsi0_pll { |
| compatible = "qcom,mdss_dsi_pll_14nm"; |
| label = "MDSS DSI 0 PLL"; |
| cell-index = <0>; |
| #clock-cells = <1>; |
| reg = <0x5e94400 0x588>, |
| <0x5f03000 0x8>, |
| <0x5e94200 0x100>; |
| reg-names = "pll_base", "gdsc_base", |
| "dynamic_pll_base"; |
| clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; |
| clock-names = "iface_clk"; |
| clock-rate = <0>; |
| memory-region = <&dfps_data_memory>; |
| gdsc-supply = <&mdss_core_gdsc>; |
| qcom,dsi-pll-ssc-en; |
| qcom,dsi-pll-ssc-mode = "down-spread"; |
| qcom,platform-supply-entries { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| qcom,platform-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "gdsc"; |
| qcom,supply-min-voltage = <0>; |
| qcom,supply-max-voltage = <0>; |
| qcom,supply-enable-load = <0>; |
| qcom,supply-disable-load = <0>; |
| }; |
| }; |
| }; |
| }; |