| #include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi" |
| #include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi" |
| #include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi" |
| #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" |
| #include "dsi-panel-sharp-dsc-4k-video.dtsi" |
| #include "dsi-panel-sharp-1080p-cmd.dtsi" |
| #include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" |
| #include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" |
| #include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" |
| #include "dsi-panel-nt35695b-truly-fhd-video.dtsi" |
| #include "dsi-panel-sim-cmd.dtsi" |
| #include "dsi-panel-sim-video.dtsi" |
| #include "dsi-panel-sim-dsc375-cmd.dtsi" |
| #include "dsi-panel-sim-dsc-10bit-cmd.dtsi" |
| #include "dsi-panel-sim-dualmipi-cmd.dtsi" |
| #include "dsi-panel-sim-dualmipi-video.dtsi" |
| #include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" |
| #include "dsi-panel-sim-sec-hd-cmd.dtsi" |
| #include <dt-bindings/clock/mdss-7nm-pll-clk.h> |
| |
| &tlmm { |
| display_panel_avdd_default: display_panel_avdd_default { |
| mux { |
| pins = "gpio61"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio61"; |
| drive-strength = <8>; |
| bias-disable = <0>; |
| output-high; |
| }; |
| }; |
| }; |
| |
| &soc { |
| ext_disp: qcom,msm-ext-disp { |
| compatible = "qcom,msm-ext-disp"; |
| |
| ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { |
| compatible = "qcom,msm-ext-disp-audio-codec-rx"; |
| }; |
| }; |
| |
| dsi_panel_pwr_supply: dsi_panel_pwr_supply { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,panel-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "vddio"; |
| qcom,supply-min-voltage = <1800000>; |
| qcom,supply-max-voltage = <1800000>; |
| qcom,supply-enable-load = <62000>; |
| qcom,supply-disable-load = <80>; |
| qcom,supply-post-on-sleep = <20>; |
| }; |
| |
| qcom,panel-supply-entry@1 { |
| reg = <1>; |
| qcom,supply-name = "vdd"; |
| qcom,supply-min-voltage = <3300000>; |
| qcom,supply-max-voltage = <3300000>; |
| qcom,supply-enable-load = <857000>; |
| qcom,supply-disable-load = <0>; |
| qcom,supply-post-on-sleep = <0>; |
| }; |
| }; |
| |
| dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,panel-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "vddio"; |
| qcom,supply-min-voltage = <1800000>; |
| qcom,supply-max-voltage = <1800000>; |
| qcom,supply-enable-load = <62000>; |
| qcom,supply-disable-load = <80>; |
| qcom,supply-post-on-sleep = <20>; |
| }; |
| |
| qcom,panel-supply-entry@1 { |
| reg = <1>; |
| qcom,supply-name = "avdd"; |
| qcom,supply-min-voltage = <4600000>; |
| qcom,supply-max-voltage = <6000000>; |
| qcom,supply-enable-load = <100000>; |
| qcom,supply-disable-load = <100>; |
| }; |
| }; |
| |
| display_panel_avdd: display_gpio_regulator@1 { |
| compatible = "regulator-fixed"; |
| regulator-name = "display_panel_avdd"; |
| regulator-min-microvolt = <5500000>; |
| regulator-max-microvolt = <5500000>; |
| regulator-enable-ramp-delay = <233>; |
| gpio = <&tlmm 61 0>; |
| enable-active-high; |
| regulator-boot-on; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&display_panel_avdd_default>; |
| }; |
| |
| sde_dsi: qcom,dsi-display-primary { |
| compatible = "qcom,dsi-display"; |
| label = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>, |
| <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, |
| <&mdss_dsi1_pll PCLK_MUX_1_CLK>; |
| clock-names = "src_byte_clk0", "src_pixel_clk0", |
| "src_byte_clk1", "src_pixel_clk1"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| |
| qcom,platform-te-gpio = <&tlmm 66 0>; |
| qcom,panel-te-source = <0>; |
| |
| vddio-supply = <&pm8150_l14>; |
| vdd-supply = <&pm8150a_l11>; |
| avdd-supply = <&display_panel_avdd>; |
| |
| qcom,mdp = <&mdss_mdp>; |
| qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; |
| }; |
| |
| sde_dsi1: qcom,dsi-display-secondary { |
| compatible = "qcom,dsi-display"; |
| label = "secondary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>, |
| <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, |
| <&mdss_dsi1_pll PCLK_MUX_1_CLK>; |
| clock-names = "src_byte_clk0", "src_pixel_clk0", |
| "src_byte_clk1", "src_pixel_clk1"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; |
| pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; |
| |
| qcom,platform-te-gpio = <&tlmm 67 0>; |
| qcom,panel-te-source = <1>; |
| |
| vddio-supply = <&pm8150_l14>; |
| vdd-supply = <&pm8150a_l11>; |
| avdd-supply = <&display_panel_avdd>; |
| |
| qcom,mdp = <&mdss_mdp>; |
| }; |
| |
| sde_wb: qcom,wb-display@0 { |
| compatible = "qcom,wb-display"; |
| cell-index = <0>; |
| label = "wb_display"; |
| }; |
| }; |
| |
| &sde_dp { |
| qcom,dp-usbpd-detection = <&pm8150b_pdphy>; |
| qcom,ext-disp = <&ext_disp>; |
| qcom,dp-aux-switch = <&fsa4480>; |
| |
| qcom,usbplug-cc-gpio = <&tlmm 65 0>; |
| |
| pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; |
| pinctrl-0 = <&sde_dp_usbplug_cc_active>; |
| pinctrl-1 = <&sde_dp_usbplug_cc_suspend>; |
| }; |
| |
| &mdss_mdp { |
| connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; |
| }; |
| |
| /* PHY TIMINGS REVISION W */ |
| &dsi_sw43404_amoled_cmd { |
| qcom,ulps-enabled; |
| qcom,esd-check-enabled; |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; |
| qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; |
| qcom,mdss-dsi-panel-status-value = <0x9c>; |
| qcom,mdss-dsi-panel-status-read-length = <1>; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05 |
| 05 03 02 04 00 12 15]; |
| qcom,display-topology = <2 2 1>; |
| qcom,default-topology-index = <0>; |
| qcom,partial-update-enabled = "single_roi"; |
| qcom,panel-roi-alignment = <720 180 180 180 1440 180>; |
| }; |
| }; |
| }; |
| |
| &dsi_sw43404_amoled_video { |
| qcom,esd-check-enabled; |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; |
| qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; |
| qcom,mdss-dsi-panel-status-value = <0x9c>; |
| qcom,mdss-dsi-panel-status-read-length = <1>; |
| qcom,dsi-supported-dfps-list = <60 57 55>; |
| qcom,mdss-dsi-pan-enable-dynamic-fps; |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp"; |
| qcom,mdss-dsi-min-refresh-rate = <55>; |
| qcom,mdss-dsi-max-refresh-rate = <60>; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05 |
| 05 03 02 04 00 12 15]; |
| qcom,display-topology = <2 2 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_sw43404_amoled_fhd_plus_cmd { |
| qcom,ulps-enabled; |
| qcom,esd-check-enabled; |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; |
| qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; |
| qcom,mdss-dsi-panel-status-value = <0x9c>; |
| qcom,mdss-dsi-panel-status-read-length = <1>; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04 |
| 05 02 03 04 00 11 14]; |
| qcom,display-topology = <2 2 1>; |
| qcom,default-topology-index = <0>; |
| qcom,partial-update-enabled = "single_roi"; |
| qcom,panel-roi-alignment = <540 270 270 270 1080 270>; |
| }; |
| }; |
| }; |
| |
| &dsi_sharp_4k_dsc_cmd { |
| qcom,ulps-enabled; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 |
| 08 05 02 04 00 19 18]; |
| qcom,display-topology = <2 2 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_sharp_4k_dsc_video { |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 |
| 08 05 02 04 00 19 18]; |
| qcom,display-topology = <2 2 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_sharp_1080_cmd { |
| qcom,ulps-enabled; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08 |
| 08 05 02 04 00 19 18]; |
| qcom,display-topology = <1 0 1>; |
| qcom,default-topology-index = <0>; |
| qcom,mdss-dsi-panel-clockrate = <900000000>; |
| }; |
| }; |
| }; |
| |
| &dsi_dual_nt35597_truly_cmd { |
| qcom,ulps-enabled; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 |
| 07 05 02 04 00 18 17]; |
| qcom,display-topology = <2 0 2>, |
| <1 0 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_dual_nt35597_truly_video { |
| qcom,mdss-dsi-min-refresh-rate = <53>; |
| qcom,mdss-dsi-max-refresh-rate = <60>; |
| qcom,mdss-dsi-pan-enable-dynamic-fps; |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 |
| 07 05 02 04 00 18 17]; |
| qcom,display-topology = <2 0 2>, |
| <1 0 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_nt35695b_truly_fhd_cmd { |
| qcom,ulps-enabled; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 |
| 08 08 05 02 04 00 19 17]; |
| qcom,display-topology = <1 0 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_nt35695b_truly_fhd_video { |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 |
| 08 08 05 02 04 00 19 17]; |
| qcom,display-topology = <1 0 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_sim_cmd { |
| qcom,ulps-enabled; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 |
| 07 05 02 04 00 18 17]; |
| qcom,display-topology = <1 1 1>, |
| <2 2 1>; |
| qcom,default-topology-index = <1>; |
| }; |
| |
| timing@1 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 |
| 07 05 02 04 00 18 17]; |
| qcom,display-topology = <1 1 1>, |
| <2 2 1>; |
| qcom,default-topology-index = <1>; |
| }; |
| |
| timing@2 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 |
| 07 05 02 04 00 18 17]; |
| qcom,display-topology = <1 1 1>, |
| <2 2 1>; |
| qcom,default-topology-index = <1>; |
| qcom,panel-roi-alignment = <720 40 720 40 720 40>; |
| qcom,partial-update-enabled = "single_roi"; |
| }; |
| |
| timing@3 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 |
| 07 05 02 04 00 18 17]; |
| qcom,display-topology = <1 1 1>, |
| <2 2 1>; |
| qcom,default-topology-index = <1>; |
| qcom,panel-roi-alignment = <540 40 540 40 540 40>; |
| qcom,partial-update-enabled = "single_roi"; |
| }; |
| |
| timing@4 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 |
| 07 05 02 04 00 18 17]; |
| qcom,display-topology = <1 1 1>, |
| <2 2 1>; |
| qcom,default-topology-index = <1>; |
| qcom,panel-roi-alignment = <360 40 360 40 360 40>; |
| qcom,partial-update-enabled = "single_roi"; |
| }; |
| }; |
| }; |
| |
| &dsi_sim_vid { |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 |
| 07 05 02 04 00 18 17]; |
| qcom,display-topology = <1 0 1>, |
| <2 0 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_sim_dsc_375_cmd { |
| qcom,ulps-enabled; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { /* 1080p */ |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 |
| 07 05 02 04 00 18 17]; |
| qcom,display-topology = <1 1 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| |
| timing@1 { /* qhd */ |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 |
| 08 05 02 04 00 19 18]; |
| qcom,display-topology = <1 1 1>, |
| <2 2 1>, /* dsc merge */ |
| <2 1 1>; /* 3d mux */ |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_sim_dsc_10b_cmd { |
| qcom,ulps-enabled; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { /* QHD 60fps */ |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 |
| 07 05 02 04 00 18 17]; |
| qcom,display-topology = <1 1 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| |
| timing@1 { /* 1080 60fps */ |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 |
| 08 05 02 04 00 19 18]; |
| qcom,display-topology = <1 1 1>, |
| <2 2 1>, /* dsc merge */ |
| <2 1 1>; /* 3d mux */ |
| qcom,default-topology-index = <0>; |
| }; |
| |
| timing@2 { /* QHD 90fps */ |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 |
| 07 05 02 04 00 18 17]; |
| qcom,display-topology = <1 1 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_dual_sim_cmd { |
| qcom,ulps-enabled; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 |
| 09 06 02 04 00 18 17]; |
| qcom,display-topology = <2 0 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| |
| timing@1 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 |
| 07 05 02 04 00 18 17]; |
| qcom,display-topology = <2 0 2>, |
| <1 0 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| |
| timing@2 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 |
| 08 05 02 04 00 19 18]; |
| qcom,display-topology = <2 0 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_dual_sim_vid { |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 |
| 07 05 02 04 00 18 17]; |
| qcom,display-topology = <2 0 2>, |
| <1 0 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_dual_sim_dsc_375_cmd { |
| qcom,ulps-enabled; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { /* qhd */ |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 |
| 07 05 02 04 00 18 17]; |
| qcom,display-topology = <2 2 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| |
| timing@1 { /* 4k */ |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 |
| 08 05 02 04 00 19 18]; |
| qcom,display-topology = <2 2 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| |
| timing@2 { /* 5k */ |
| qcom,mdss-dsi-panel-phy-timings = [00 46 13 14 33 30 12 |
| 14 0e 02 04 00 37 22]; |
| qcom,display-topology = <2 2 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_sim_sec_hd_cmd { |
| qcom,ulps-enabled; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 |
| 08 08 05 02 04 00 19 17]; |
| qcom,display-topology = <1 0 1>; |
| qcom,default-topology-index = <0>; |
| qcom,panel-roi-alignment = <720 40 720 40 720 40>; |
| qcom,partial-update-enabled = "single_roi"; |
| }; |
| }; |
| }; |