| #include <dt-bindings/msm/msm-bus-ids.h> |
| |
| &soc { |
| /* QUPv3_0 wrapper instance : North QUP*/ |
| qupv3_0: qcom,qupv3_0_geni_se@9c0000 { |
| compatible = "qcom,qupv3-geni-se"; |
| reg = <0x9c0000 0x2000>; |
| qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_0>; |
| qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>; |
| iommus = <&apps_smmu 0x5a3 0x0>; |
| qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; |
| qcom,iommu-dma = "fastmap"; |
| }; |
| |
| /* QUPV3_0_SE0 */ |
| i3c0: i3c-master@980000 { |
| compatible = "qcom,geni-i3c"; |
| reg = <0x980000 0x4000>, |
| <0x0EC30000 0x10000>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep", "disable"; |
| pinctrl-0 = <&qupv3_se0_i3c_active>; |
| pinctrl-1 = <&qupv3_se0_i3c_sleep>; |
| pinctrl-2 = <&qupv3_se0_i3c_disable>; |
| interrupts-extended = <&intc GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>, |
| <&pdc 31 IRQ_TYPE_LEVEL_HIGH>, |
| <&pdc 30 IRQ_TYPE_LEVEL_HIGH>; |
| |
| #address-cells = <3>; |
| #size-cells = <0>; |
| qcom,wrapper-core = <&qupv3_0>; |
| qcom,ibi-ctrl-id = <0>; |
| status = "disabled"; |
| }; |
| |
| /* QUPV3_0_SE1 */ |
| i3c1: i3c-master@984000 { |
| compatible = "qcom,geni-i3c"; |
| reg = <0x984000 0x4000>, |
| <0xEC40000 0x10000>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep", "disable"; |
| pinctrl-0 = <&qupv3_se1_i3c_active>; |
| pinctrl-1 = <&qupv3_se1_i3c_sleep>; |
| pinctrl-2 = <&qupv3_se1_i3c_disable>; |
| interrupts-extended = <&intc GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, |
| <&pdc 33 IRQ_TYPE_LEVEL_HIGH>, |
| <&pdc 32 IRQ_TYPE_LEVEL_HIGH>; |
| |
| #address-cells = <3>; |
| #size-cells = <0>; |
| qcom,wrapper-core = <&qupv3_0>; |
| qcom,ibi-ctrl-id = <1>; |
| status = "disabled"; |
| }; |
| |
| /* Debug UART Instance for RUMI platform */ |
| qupv3_se2_2uart: qcom,qup_uart@988000 { |
| compatible = "qcom,msm-geni-console"; |
| reg = <0x988000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se2_2uart_active>; |
| pinctrl-1 = <&qupv3_se2_2uart_sleep>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,wrapper-core = <&qupv3_0>; |
| qcom,change-sampling-rate; |
| status = "disabled"; |
| }; |
| |
| /* |
| * HS UART instances. HS UART usecases can be supported on these |
| * instances only. |
| */ |
| qupv3_se6_4uart: qcom,qup_uart@998000 { |
| compatible = "qcom,msm-geni-serial-hs"; |
| reg = <0x998000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "active", "sleep"; |
| pinctrl-0 = <&qupv3_se6_default_cts>, |
| <&qupv3_se6_default_rtsrx>, <&qupv3_se6_default_tx>; |
| pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>, |
| <&qupv3_se6_tx>; |
| pinctrl-2 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>, |
| <&qupv3_se6_tx>; |
| interrupts-extended = <&intc GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>, |
| <&tlmm 19 0>; |
| status = "disabled"; |
| qcom,wakeup-byte = <0xFD>; |
| qcom,wrapper-core = <&qupv3_0>; |
| }; |
| |
| /* I2C */ |
| qupv3_se0_i2c: i2c@980000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x980000 0x4000>; |
| interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| dmas = <&gpi_dma0 0 0 3 64 0>, |
| <&gpi_dma0 1 0 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se0_i2c_active>; |
| pinctrl-1 = <&qupv3_se0_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_0>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se1_i2c: i2c@984000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x984000 0x4000>; |
| interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| dmas = <&gpi_dma0 0 1 3 64 0>, |
| <&gpi_dma0 1 1 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se1_i2c_active>; |
| pinctrl-1 = <&qupv3_se1_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_0>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se2_i2c: i2c@988000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x988000 0x4000>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| dmas = <&gpi_dma0 0 2 3 64 0>, |
| <&gpi_dma0 1 2 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se2_i2c_active>; |
| pinctrl-1 = <&qupv3_se2_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_0>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se3_i2c: i2c@98c000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x98c000 0x4000>; |
| interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| dmas = <&gpi_dma0 0 3 3 64 0>, |
| <&gpi_dma0 1 3 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se3_i2c_active>; |
| pinctrl-1 = <&qupv3_se3_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_0>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se4_i2c: i2c@990000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x990000 0x4000>; |
| interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| dmas = <&gpi_dma0 0 4 3 64 0>, |
| <&gpi_dma0 1 4 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se4_i2c_active>; |
| pinctrl-1 = <&qupv3_se4_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_0>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se5_i2c: i2c@994000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x994000 0x4000>; |
| interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| dmas = <&gpi_dma0 0 5 3 64 0>, |
| <&gpi_dma0 1 5 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se5_i2c_active>; |
| pinctrl-1 = <&qupv3_se5_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_0>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se6_i2c: i2c@998000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x998000 0x4000>; |
| interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| dmas = <&gpi_dma0 0 6 3 64 0>, |
| <&gpi_dma0 1 6 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se6_i2c_active>; |
| pinctrl-1 = <&qupv3_se6_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_0>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se7_i2c: i2c@99c000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x99c000 0x4000>; |
| interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| dmas = <&gpi_dma0 0 7 3 64 0>, |
| <&gpi_dma0 1 7 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se7_i2c_active>; |
| pinctrl-1 = <&qupv3_se7_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_0>; |
| status = "disabled"; |
| }; |
| |
| /* SPI */ |
| qupv3_se0_spi: spi@980000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x980000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se0_spi_active>; |
| pinctrl-1 = <&qupv3_se0_spi_sleep>; |
| interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_0>; |
| dmas = <&gpi_dma0 0 0 1 64 0>, |
| <&gpi_dma0 1 0 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se1_spi: spi@984000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x984000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se1_spi_active>; |
| pinctrl-1 = <&qupv3_se1_spi_sleep>; |
| interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_0>; |
| dmas = <&gpi_dma0 0 1 1 64 0>, |
| <&gpi_dma0 1 1 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se2_spi: spi@988000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x988000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se2_spi_active>; |
| pinctrl-1 = <&qupv3_se2_spi_sleep>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_0>; |
| dmas = <&gpi_dma0 0 2 1 64 0>, |
| <&gpi_dma0 1 2 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se3_spi: spi@98c000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x98c000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se3_spi_active>; |
| pinctrl-1 = <&qupv3_se3_spi_sleep>; |
| interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_0>; |
| dmas = <&gpi_dma0 0 3 1 64 0>, |
| <&gpi_dma0 1 3 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se4_spi: spi@990000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x990000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se4_spi_active>; |
| pinctrl-1 = <&qupv3_se4_spi_sleep>; |
| interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_0>; |
| dmas = <&gpi_dma0 0 4 1 64 0>, |
| <&gpi_dma0 1 4 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se5_spi: spi@994000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x994000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se5_spi_active>; |
| pinctrl-1 = <&qupv3_se5_spi_sleep>; |
| interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_0>; |
| dmas = <&gpi_dma0 0 5 1 64 0>, |
| <&gpi_dma0 1 5 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se6_spi: spi@998000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x998000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se6_spi_active>; |
| pinctrl-1 = <&qupv3_se6_spi_sleep>; |
| interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_0>; |
| dmas = <&gpi_dma0 0 6 1 64 0>, |
| <&gpi_dma0 1 6 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se7_spi: spi@99c000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x99c000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se7_spi_active>; |
| pinctrl-1 = <&qupv3_se7_spi_sleep>; |
| interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_0>; |
| dmas = <&gpi_dma0 0 7 1 64 0>, |
| <&gpi_dma0 1 7 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| /* QUPv3 South_1 & South_2 Instances |
| * South_1 0 : SE 8 |
| * South_1 1 : SE 9 |
| * South_1 2 : SE 10 |
| * South_1 3 : SE 11 |
| * South_1 4 : SE 12 |
| * South_1 5 : SE 13 |
| * South_2 0 : SE 14 |
| * South_2 1 : SE 15 |
| * South_2 2 : SE 16 |
| * South_2 3 : SE 17 |
| * South_2 4 : SE 18 |
| * South_2 5 : SE 19 |
| */ |
| |
| /* QUPv3_1 wrapper instance : South_1 QUP */ |
| qupv3_1: qcom,qupv3_1_geni_se@ac0000 { |
| compatible = "qcom,qupv3-geni-se"; |
| reg = <0xac0000 0x2000>; |
| qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_1>; |
| qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>; |
| iommus = <&apps_smmu 0x43 0x0>; |
| qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; |
| qcom,iommu-dma = "fastmap"; |
| }; |
| |
| /* Debug UART Instance for CDP/MTP platform */ |
| qupv3_se12_2uart: qcom,qup_uart@a90000 { |
| compatible = "qcom,msm-geni-console"; |
| reg = <0xa90000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se12_2uart_active>; |
| pinctrl-1 = <&qupv3_se12_2uart_sleep>; |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,wrapper-core = <&qupv3_1>; |
| qcom,change-sampling-rate; |
| status = "disabled"; |
| }; |
| qupv3_se13_4uart: qcom,qup_uart@a94000 { |
| compatible = "qcom,msm-geni-serial-hs"; |
| reg = <0xa94000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| pinctrl-names = "default", "active", "sleep"; |
| pinctrl-0 = <&qupv3_se13_default_cts>, |
| <&qupv3_se13_default_rtsrx>, <&qupv3_se13_default_tx>; |
| pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>, |
| <&qupv3_se13_tx>; |
| pinctrl-2 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>, |
| <&qupv3_se13_tx>; |
| interrupts-extended = <&intc GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, |
| <&tlmm 39 0>; |
| status = "disabled"; |
| qcom,wakeup-byte = <0xFD>; |
| qcom,wrapper-core = <&qupv3_1>; |
| }; |
| |
| /* I2C */ |
| qupv3_se8_i2c: i2c@a80000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0xa80000 0x4000>; |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| dmas = <&gpi_dma1 0 0 3 64 0>, |
| <&gpi_dma1 1 0 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se8_i2c_active>; |
| pinctrl-1 = <&qupv3_se8_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_1>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se9_i2c: i2c@a84000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0xa84000 0x4000>; |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| dmas = <&gpi_dma1 0 1 3 64 0>, |
| <&gpi_dma1 1 1 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se9_i2c_active>; |
| pinctrl-1 = <&qupv3_se9_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_1>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se10_i2c: i2c@a88000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0xa88000 0x4000>; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| dmas = <&gpi_dma1 0 2 3 64 0>, |
| <&gpi_dma1 1 2 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se10_i2c_active>; |
| pinctrl-1 = <&qupv3_se10_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_1>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se11_i2c: i2c@a8c000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0xa8c000 0x4000>; |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| dmas = <&gpi_dma1 0 3 3 64 0>, |
| <&gpi_dma1 1 3 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se11_i2c_active>; |
| pinctrl-1 = <&qupv3_se11_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_1>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se12_i2c: i2c@a90000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0xa90000 0x4000>; |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| dmas = <&gpi_dma1 0 4 3 64 0>, |
| <&gpi_dma1 1 4 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se12_i2c_active>; |
| pinctrl-1 = <&qupv3_se12_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_1>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se13_i2c: i2c@a94000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0xa94000 0x4000>; |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| dmas = <&gpi_dma1 0 5 3 64 0>, |
| <&gpi_dma1 1 5 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se13_i2c_active>; |
| pinctrl-1 = <&qupv3_se13_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_1>; |
| status = "disabled"; |
| }; |
| |
| /* SPI */ |
| qupv3_se8_spi: spi@a80000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xa80000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se8_spi_active>; |
| pinctrl-1 = <&qupv3_se8_spi_active>; |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_1>; |
| dmas = <&gpi_dma1 0 0 1 64 0>, |
| <&gpi_dma1 1 0 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se9_spi: spi@a84000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xa84000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se9_spi_active>; |
| pinctrl-1 = <&qupv3_se9_spi_sleep>; |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_1>; |
| dmas = <&gpi_dma1 0 1 1 64 0>, |
| <&gpi_dma1 1 1 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se10_spi: spi@a88000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xa88000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se10_spi_active>; |
| pinctrl-1 = <&qupv3_se10_spi_sleep>; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_1>; |
| dmas = <&gpi_dma1 0 2 1 64 0>, |
| <&gpi_dma1 1 2 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se11_spi: spi@a8c000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xa8c000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se11_spi_active>; |
| pinctrl-1 = <&qupv3_se11_spi_sleep>; |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_1>; |
| dmas = <&gpi_dma1 0 3 1 64 0>, |
| <&gpi_dma1 1 3 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se12_spi: spi@a90000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xa90000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se12_spi_active>; |
| pinctrl-1 = <&qupv3_se12_spi_sleep>; |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_1>; |
| dmas = <&gpi_dma1 0 4 1 64 0>, |
| <&gpi_dma1 1 4 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se13_spi: spi@a94000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xa94000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se13_spi_active>; |
| pinctrl-1 = <&qupv3_se13_spi_sleep>; |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_1>; |
| dmas = <&gpi_dma1 0 5 1 64 0>, |
| <&gpi_dma1 1 5 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| /* QUPv3_2 wrapper instance : South_2 QUP */ |
| qupv3_2: qcom,qupv3_2_geni_se@8c0000 { |
| compatible = "qcom,qupv3-geni-se"; |
| reg = <0x8c0000 0x2000>; |
| qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_2>; |
| qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>; |
| iommus = <&apps_smmu 0x63 0x0>; |
| qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; |
| qcom,iommu-dma = "fastmap"; |
| }; |
| |
| /* |
| * HS UART : Modem/Audio backup |
| */ |
| qupv3_se17_4uart: qcom,qup_uart@88c000 { |
| compatible = "qcom,msm-geni-serial-hs"; |
| reg = <0x88c000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>, |
| <&qupv3_se17_tx>; |
| pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>, |
| <&qupv3_se17_tx>; |
| interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, |
| <&tlmm 55 0>; |
| status = "disabled"; |
| qcom,wakeup-byte = <0xFD>; |
| qcom,wrapper-core = <&qupv3_2>; |
| }; |
| |
| /* |
| * HS UART : 2-wire Modem |
| */ |
| qupv3_se18_2uart: qcom,qup_uart@890000 { |
| compatible = "qcom,msm-geni-serial-hs"; |
| reg = <0x890000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se18_rx>, <&qupv3_se18_tx>; |
| pinctrl-1 = <&qupv3_se18_rx>, <&qupv3_se18_tx>; |
| interrupts-extended = <&intc GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>, |
| <&tlmm 59 0>; |
| status = "disabled"; |
| qcom,wakeup-byte = <0xFD>; |
| qcom,wrapper-core = <&qupv3_2>; |
| }; |
| |
| /* I2C */ |
| qupv3_se14_i2c: i2c@880000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x880000 0x4000>; |
| interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| dmas = <&gpi_dma2 0 0 3 64 0>, |
| <&gpi_dma2 1 0 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se14_i2c_active>; |
| pinctrl-1 = <&qupv3_se14_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_2>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se15_i2c: i2c@884000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x884000 0x4000>; |
| interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP2_S1_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| dmas = <&gpi_dma2 0 1 3 64 0>, |
| <&gpi_dma2 1 1 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se15_i2c_active>; |
| pinctrl-1 = <&qupv3_se15_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_2>; |
| status = "ok"; |
| }; |
| |
| qupv3_se16_i2c: i2c@888000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x888000 0x4000>; |
| interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP2_S2_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| dmas = <&gpi_dma2 0 2 3 64 0>, |
| <&gpi_dma2 1 2 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se16_i2c_active>; |
| pinctrl-1 = <&qupv3_se16_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_2>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se17_i2c: i2c@88c000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x88c000 0x4000>; |
| interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| dmas = <&gpi_dma2 0 3 3 64 0>, |
| <&gpi_dma2 1 3 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se17_i2c_active>; |
| pinctrl-1 = <&qupv3_se17_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_2>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se18_i2c: i2c@890000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x890000 0x4000>; |
| interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| dmas = <&gpi_dma2 0 4 3 64 0>, |
| <&gpi_dma2 1 4 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se18_i2c_active>; |
| pinctrl-1 = <&qupv3_se18_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_2>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se19_i2c: i2c@894000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x894000 0x4000>; |
| interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| dmas = <&gpi_dma2 0 5 3 64 0>, |
| <&gpi_dma2 1 5 3 64 0>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se19_i2c_active>; |
| pinctrl-1 = <&qupv3_se19_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_2>; |
| status = "disabled"; |
| }; |
| |
| /* SPI */ |
| qupv3_se14_spi: spi@880000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x880000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se14_spi_active>; |
| pinctrl-1 = <&qupv3_se14_spi_sleep>; |
| interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_2>; |
| dmas = <&gpi_dma2 0 0 1 64 0>, |
| <&gpi_dma2 1 0 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se15_spi: spi@884000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x884000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP2_S1_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se15_spi_active>; |
| pinctrl-1 = <&qupv3_se15_spi_sleep>; |
| interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_2>; |
| dmas = <&gpi_dma2 0 1 1 64 0>, |
| <&gpi_dma2 1 1 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se16_spi: spi@888000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x888000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP2_S2_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se16_spi_active>; |
| pinctrl-1 = <&qupv3_se16_spi_sleep>; |
| interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_2>; |
| dmas = <&gpi_dma2 0 2 1 64 0>, |
| <&gpi_dma2 1 2 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se17_spi: spi@88c000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x88c000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se17_spi_active>; |
| pinctrl-1 = <&qupv3_se17_spi_sleep>; |
| interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_2>; |
| dmas = <&gpi_dma2 0 3 1 64 0>, |
| <&gpi_dma2 1 3 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se18_spi: spi@890000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x890000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se18_spi_active>; |
| pinctrl-1 = <&qupv3_se18_spi_sleep>; |
| interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_2>; |
| dmas = <&gpi_dma2 0 4 1 64 0>, |
| <&gpi_dma2 1 4 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qupv3_se19_spi: spi@894000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x894000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se19_spi_active>; |
| pinctrl-1 = <&qupv3_se19_spi_sleep>; |
| interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_2>; |
| dmas = <&gpi_dma2 0 5 1 64 0>, |
| <&gpi_dma2 1 5 1 64 0>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| }; |