| #include <dt-bindings/clock/qcom,gcc-kona.h> |
| #include <dt-bindings/phy/qcom,kona-qmp-usb3.h> |
| |
| &soc { |
| /* Primary USB port related controller */ |
| usb0: ssusb@a600000 { |
| compatible = "qcom,dwc-usb3-msm"; |
| reg = <0x0a600000 0x100000>; |
| reg-names = "core_base"; |
| |
| iommus = <&apps_smmu 0x0 0x0>; |
| qcom,iommu-dma = "atomic"; |
| qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>, |
| <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, |
| <&pdc 15 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", |
| "ss_phy_irq", "dm_hs_phy_irq"; |
| qcom,use-pdc-interrupts; |
| |
| USB3_GDSC-supply = <&usb30_prim_gdsc>; |
| dpdm-supply = <&usb2_phy0>; |
| clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>, |
| <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, |
| <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, |
| <&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
| <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>, |
| /* |
| * GCC_USB3_SEC_CLKREF_EN provides ref_clk for both |
| * USB instances. |
| */ |
| <&clock_gcc GCC_USB3_SEC_CLKREF_EN>; |
| clock-names = "core_clk", "iface_clk", "bus_aggr_clk", |
| "utmi_clk", "sleep_clk", "xo"; |
| |
| resets = <&clock_gcc GCC_USB30_PRIM_BCR>; |
| reset-names = "core_reset"; |
| |
| qcom,core-clk-rate = <200000000>; |
| qcom,core-clk-rate-hs = <66666667>; |
| qcom,num-gsi-evt-buffs = <0x3>; |
| qcom,gsi-reg-offset = |
| <0x0fc /* GSI_GENERAL_CFG */ |
| 0x110 /* GSI_DBL_ADDR_L */ |
| 0x120 /* GSI_DBL_ADDR_H */ |
| 0x130 /* GSI_RING_BASE_ADDR_L */ |
| 0x144 /* GSI_RING_BASE_ADDR_H */ |
| 0x1a4>; /* GSI_IF_STS */ |
| qcom,dwc-usb3-msm-tx-fifo-size = <27696>; |
| |
| qcom,msm-bus,name = "usb0"; |
| qcom,msm-bus,num-cases = <4>; |
| qcom,msm-bus,num-paths = <3>; |
| qcom,msm-bus,vectors-KBps = |
| /* suspend vote */ |
| <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>, |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>, |
| |
| /* nominal vote */ |
| <MSM_BUS_MASTER_USB3 |
| MSM_BUS_SLAVE_EBI_CH0 1000000 2500000>, |
| <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>, |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>, |
| |
| /* svs vote */ |
| <MSM_BUS_MASTER_USB3 |
| MSM_BUS_SLAVE_EBI_CH0 240000 700000>, |
| <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>, |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>, |
| |
| /* min vote */ |
| <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 1 1>, |
| <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 1 1>, |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 1 1>; |
| |
| dwc3@a600000 { |
| compatible = "snps,dwc3"; |
| reg = <0x0a600000 0xd93c>; |
| interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; |
| linux,sysdev_is_parent; |
| snps,disable-clk-gating; |
| snps,has-lpm-erratum; |
| snps,hird-threshold = /bits/ 8 <0x10>; |
| snps,usb3-u1u2-disable; |
| usb-core-id = <0>; |
| tx-fifo-resize; |
| maximum-speed = "super-speed-plus"; |
| dr_mode = "drd"; |
| }; |
| |
| qcom,usbbam@a704000 { |
| compatible = "qcom,usb-bam-msm"; |
| reg = <0xa704000 0x17000>; |
| interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; |
| |
| qcom,usb-bam-fifo-baseaddr = <0x146bb000>; |
| qcom,usb-bam-num-pipes = <4>; |
| qcom,disable-clk-gating; |
| qcom,usb-bam-override-threshold = <0x4001>; |
| qcom,usb-bam-max-mbps-highspeed = <400>; |
| qcom,usb-bam-max-mbps-superspeed = <3600>; |
| qcom,reset-bam-on-connect; |
| |
| qcom,pipe0 { |
| label = "ssusb-qdss-in-0"; |
| qcom,usb-bam-mem-type = <2>; |
| qcom,dir = <1>; |
| qcom,pipe-num = <0>; |
| qcom,peer-bam = <0>; |
| qcom,peer-bam-physical-address = <0x6064000>; |
| qcom,src-bam-pipe-index = <0>; |
| qcom,dst-bam-pipe-index = <0>; |
| qcom,data-fifo-offset = <0x0>; |
| qcom,data-fifo-size = <0x1800>; |
| qcom,descriptor-fifo-offset = <0x1800>; |
| qcom,descriptor-fifo-size = <0x800>; |
| }; |
| }; |
| }; |
| |
| /* Primary USB port related High Speed PHY */ |
| usb2_phy0: hsphy@88e3000 { |
| compatible = "qcom,usb-hsphy-snps-femto"; |
| reg = <0x88e3000 0x110>, |
| <0x088e2000 0x4>; |
| reg-names = "hsusb_phy_base", |
| "eud_enable_reg"; |
| |
| vdd-supply = <&pm8150_l5>; |
| vdda18-supply = <&pm8150_l12>; |
| vdda33-supply = <&pm8150_l2>; |
| qcom,vdd-voltage-level = <0 880000 880000>; |
| |
| clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| clock-names = "ref_clk_src"; |
| |
| resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; |
| reset-names = "phy_reset"; |
| qcom,param-override-seq = <0x43 0x70>; |
| }; |
| |
| /* Primary USB port related QMP USB DP Combo PHY */ |
| usb_qmp_dp_phy: ssphy@88e8000 { |
| compatible = "qcom,usb-ssphy-qmp-dp-combo"; |
| reg = <0x88e8000 0x3000>; |
| reg-names = "qmp_phy_base"; |
| |
| vdd-supply = <&pm8150_l18>; |
| qcom,vdd-voltage-level = <0 912000 912000>; |
| qcom,vdd-max-load-uA = <47000>; |
| core-supply = <&pm8150_l9>; |
| qcom,vbus-valid-override; |
| qcom,qmp-phy-init-seq = |
| /* <reg_offset, value, delay> */ |
| <USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0 |
| USB3_DP_QSERDES_COM_SSC_PER1 0x31 0 |
| USB3_DP_QSERDES_COM_SSC_PER2 0x01 0 |
| USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0 |
| USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0 |
| USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0 |
| USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0 |
| USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0 |
| USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0 |
| USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0 |
| USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0 |
| USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0 |
| USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0 |
| USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0 |
| USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0 |
| USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0 |
| USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0 |
| USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0 |
| USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0 |
| USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0 |
| USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0 |
| USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0 |
| USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0 |
| USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0 |
| USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0 |
| USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0 |
| USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0 |
| USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0 |
| USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0 |
| USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0 |
| USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0 |
| USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0 |
| USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0 |
| USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0 |
| USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0 |
| USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0 |
| USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0 |
| USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0 |
| USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0 |
| USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0 |
| USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x60 0 |
| USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x60 0 |
| USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x11 0 |
| USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x02 0 |
| USB3_DP_QSERDES_TXA_LANE_MODE_1 0xD5 0 |
| USB3_DP_QSERDES_TXA_LANE_MODE_2 0x00 0 |
| USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0 |
| USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x40 0 |
| USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09 0 |
| USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0 |
| USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0 |
| USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0 |
| USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0 |
| USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0 |
| USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0 |
| USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0 |
| USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0 |
| USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0 |
| USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0 |
| USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0 |
| USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0C 0 |
| USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0 |
| USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0 |
| USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0 |
| USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0 |
| USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0 |
| USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0 |
| USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0 |
| USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0 |
| USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xFF 0 |
| USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7F 0 |
| USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x7F 0 |
| USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F 0 |
| USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x97 0 |
| USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC 0 |
| USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC 0 |
| USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C 0 |
| USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x7B 0 |
| USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB4 0 |
| USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0 |
| USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0 |
| USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0 |
| USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0 |
| USB3_DP_QSERDES_RXA_GM_CAL 0x1F 0 |
| USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0 |
| USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x60 0 |
| USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x60 0 |
| USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x11 0 |
| USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x02 0 |
| USB3_DP_QSERDES_TXB_LANE_MODE_1 0xD5 0 |
| USB3_DP_QSERDES_TXB_LANE_MODE_2 0x00 0 |
| USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0 |
| USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x54 0 |
| USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09 0 |
| USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0 |
| USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0 |
| USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0 |
| USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0 |
| USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0 |
| USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0 |
| USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0 |
| USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0 |
| USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0 |
| USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0 |
| USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0 |
| USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0C 0 |
| USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0 |
| USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0 |
| USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0 |
| USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0 |
| USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0 |
| USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0 |
| USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0 |
| USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0 |
| USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x7F 0 |
| USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xFF 0 |
| USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F 0 |
| USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0 |
| USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xA6 0 |
| USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC 0 |
| USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC 0 |
| USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C 0 |
| USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x7B 0 |
| USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB4 0 |
| USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0 |
| USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0 |
| USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0 |
| USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0 |
| USB3_DP_QSERDES_RXB_GM_CAL 0x1F 0 |
| USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0 |
| USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0 |
| USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0 |
| USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0 |
| USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0 |
| USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0 |
| USB3_DP_PCS_RX_SIGDET_LVL 0xA9 0 |
| USB3_DP_PCS_CDR_RESET_TIME 0x0A 0 |
| USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0 |
| USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0 |
| USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0 |
| USB3_DP_PCS_EQ_CONFIG1 0x4B 0 |
| USB3_DP_PCS_EQ_CONFIG5 0x10 0 |
| USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0 |
| USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0 |
| 0xffffffff 0xffffffff 0x00>; |
| |
| qcom,qmp-phy-reg-offset = |
| <USB3_DP_PCS_PCS_STATUS1 |
| USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL |
| USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR |
| USB3_DP_PCS_POWER_DOWN_CONTROL |
| USB3_DP_PCS_SW_RESET |
| USB3_DP_PCS_START_CONTROL |
| 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */ |
| 0x2a18 /* USB3_DP_DP_PHY_PD_CTL */ |
| USB3_DP_COM_POWER_DOWN_CTRL |
| USB3_DP_COM_SW_RESET |
| USB3_DP_COM_RESET_OVRD_CTRL |
| USB3_DP_COM_PHY_MODE_CTRL |
| USB3_DP_COM_TYPEC_CTRL |
| USB3_DP_COM_SWI_CTRL |
| USB3_DP_PCS_CLAMP_ENABLE>; |
| |
| clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>, |
| <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, |
| <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, |
| <&clock_gcc USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK>, |
| <&clock_rpmh RPMH_CXO_CLK>, |
| <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; |
| clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", |
| "pipe_clk_ext_src", "ref_clk_src", |
| "com_aux_clk"; |
| |
| resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>, |
| <&clock_gcc GCC_USB3_PHY_PRIM_BCR>; |
| reset-names = "global_phy_reset", "phy_reset"; |
| }; |
| |
| usb_audio_qmi_dev { |
| compatible = "qcom,usb-audio-qmi-dev"; |
| iommus = <&apps_smmu 0x180f 0x0>; |
| qcom,iommu-dma = "disabled"; |
| qcom,usb-audio-stream-id = <0xf>; |
| qcom,usb-audio-intr-num = <2>; |
| }; |
| |
| usb_nop_phy: usb_nop_phy { |
| compatible = "usb-nop-xceiv"; |
| }; |
| |
| /* Secondary USB port related controller */ |
| usb1: ssusb@a800000 { |
| compatible = "qcom,dwc-usb3-msm"; |
| reg = <0xa800000 0x100000>; |
| reg-names = "core_base"; |
| |
| iommus = <&apps_smmu 0x20 0x0>; |
| qcom,iommu-dma = "atomic"; |
| qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_BOTH>, |
| <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, |
| <&pdc 13 IRQ_TYPE_EDGE_BOTH>; |
| interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", |
| "ss_phy_irq", "dm_hs_phy_irq"; |
| qcom,use-pdc-interrupts; |
| |
| USB3_GDSC-supply = <&usb30_sec_gdsc>; |
| clocks = <&clock_gcc GCC_USB30_SEC_MASTER_CLK>, |
| <&clock_gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, |
| <&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, |
| <&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
| <&clock_gcc GCC_USB30_SEC_SLEEP_CLK>, |
| <&clock_gcc GCC_USB3_SEC_CLKREF_EN>; |
| |
| clock-names = "core_clk", "iface_clk", "bus_aggr_clk", |
| "utmi_clk", "sleep_clk", "xo"; |
| |
| resets = <&clock_gcc GCC_USB30_SEC_BCR>; |
| reset-names = "core_reset"; |
| |
| qcom,core-clk-rate = <200000000>; |
| qcom,core-clk-rate-hs = <66666667>; |
| qcom,num-gsi-evt-buffs = <0x3>; |
| qcom,gsi-reg-offset = |
| <0x0fc /* GSI_GENERAL_CFG */ |
| 0x110 /* GSI_DBL_ADDR_L */ |
| 0x120 /* GSI_DBL_ADDR_H */ |
| 0x130 /* GSI_RING_BASE_ADDR_L */ |
| 0x144 /* GSI_RING_BASE_ADDR_H */ |
| 0x1a4>; /* GSI_IF_STS */ |
| qcom,dwc-usb3-msm-tx-fifo-size = <27696>; |
| qcom,charging-disabled; |
| |
| qcom,msm-bus,name = "usb1"; |
| qcom,msm-bus,num-cases = <3>; |
| qcom,msm-bus,num-paths = <3>; |
| qcom,msm-bus,vectors-KBps = |
| /* suspend vote */ |
| <MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| <MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_IPA_CFG 0 0>, |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3_1 0 0>, |
| |
| /* nominal vote */ |
| <MSM_BUS_MASTER_USB3_1 |
| MSM_BUS_SLAVE_EBI_CH0 1000000 2500000>, |
| <MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_IPA_CFG 0 2400>, |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3_1 0 40000>, |
| |
| /* svs vote */ |
| <MSM_BUS_MASTER_USB3_1 |
| MSM_BUS_SLAVE_EBI_CH0 240000 700000>, |
| <MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_IPA_CFG 0 2400>, |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3_1 0 40000>; |
| |
| dwc3@a800000 { |
| compatible = "snps,dwc3"; |
| reg = <0xa800000 0xd93c>; |
| interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| usb-phy = <&usb2_phy1>, <&usb_qmp_phy>; |
| linux,sysdev_is_parent; |
| snps,disable-clk-gating; |
| snps,has-lpm-erratum; |
| snps,hird-threshold = /bits/ 8 <0x10>; |
| snps,usb3_lpm_capable; |
| usb-core-id = <1>; |
| tx-fifo-resize; |
| maximum-speed = "super-speed"; |
| dr_mode = "drd"; |
| }; |
| }; |
| |
| /* Primary USB port related High Speed PHY */ |
| usb2_phy1: hsphy@88e4000 { |
| compatible = "qcom,usb-hsphy-snps-femto"; |
| reg = <0x88e4000 0x110>; |
| reg-names = "hsusb_phy_base"; |
| |
| vdd-supply = <&pm8150_l5>; |
| vdda18-supply = <&pm8150_l12>; |
| vdda33-supply = <&pm8150_l2>; |
| qcom,vdd-voltage-level = <0 880000 880000>; |
| |
| clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| clock-names = "ref_clk_src"; |
| |
| resets = <&clock_gcc GCC_QUSB2PHY_SEC_BCR>; |
| reset-names = "phy_reset"; |
| qcom,param-override-seq = <0x43 0x70>; |
| }; |
| |
| /* Secondary USB port related QMP PHY */ |
| usb_qmp_phy: ssphy@88eb000 { |
| compatible = "qcom,usb-ssphy-qmp-v2"; |
| reg = <0x88eb000 0x1000>, |
| <0x088eb88c 0x4>; |
| reg-names = "qmp_phy_base", |
| "pcs_clamp_enable_reg"; |
| |
| vdd-supply = <&pm8150_l18>; |
| qcom,vdd-voltage-level = <0 912000 912000>; |
| qcom,vdd-max-load-uA = <47000>; |
| core-supply = <&pm8150_l9>; |
| qcom,vbus-valid-override; |
| qcom,qmp-phy-init-seq = |
| /* <reg_offset, value, delay> */ |
| <USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a 0 |
| USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0 |
| USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0 |
| USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0 |
| USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0 |
| USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0 |
| USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0 |
| USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0 |
| USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0 |
| USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06 0 |
| USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0 |
| USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0 |
| USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0 |
| USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0 |
| USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0 |
| USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0 |
| USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0 |
| USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0 |
| USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0 |
| USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0 |
| USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0 |
| USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0 |
| USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0 |
| USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0 |
| USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0 |
| USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0 |
| USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0 |
| USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0 |
| USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0 |
| USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0 |
| USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0 |
| USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0 |
| USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0 |
| USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0 |
| USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0 |
| USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0 |
| USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0 |
| USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0 |
| USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0 |
| USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0 |
| USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xb8 0 |
| USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xff 0 |
| USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xbf 0 |
| USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7f 0 |
| USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0x7f 0 |
| USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb4 0 |
| USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7b 0 |
| USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0 |
| USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0 |
| USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc 0 |
| USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0 |
| USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04 0 |
| USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0 |
| USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05 0 |
| USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05 0 |
| USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f 0 |
| USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0 |
| USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0 |
| USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0 |
| USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A 0 |
| USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0 |
| USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0c 0 |
| USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0 |
| USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0 |
| USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0 |
| USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04 0 |
| USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0 |
| USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0 |
| USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0 |
| USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e 0 |
| USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0 |
| USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0 |
| USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38 0 |
| USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0 |
| USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0 |
| USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0 |
| USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0 |
| USB3_UNI_QSERDES_TX_LANE_MODE_1 0xd5 0 |
| USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82 0 |
| USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0 |
| USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x11 0 |
| USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x02 0 |
| USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0 |
| USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0 |
| USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0 |
| USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0 |
| USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0 |
| USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0 |
| USB3_UNI_PCS_RX_SIGDET_LVL 0xa9 0 |
| USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0 |
| USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0 |
| USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0 |
| USB3_UNI_PCS_CDR_RESET_TIME 0x0a 0 |
| USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0 |
| USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0 |
| USB3_UNI_PCS_EQ_CONFIG1 0x4b 0 |
| USB3_UNI_PCS_EQ_CONFIG5 0x10 0 |
| USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0 |
| 0xffffffff 0xffffffff 0x00>; |
| |
| qcom,qmp-phy-reg-offset = |
| <USB3_UNI_PCS_PCS_STATUS1 |
| USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL |
| USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR |
| USB3_UNI_PCS_POWER_DOWN_CONTROL |
| USB3_UNI_PCS_SW_RESET |
| USB3_UNI_PCS_START_CONTROL>; |
| |
| clocks = <&clock_gcc GCC_USB3_SEC_PHY_AUX_CLK>, |
| <&clock_gcc GCC_USB3_SEC_PHY_PIPE_CLK>, |
| <&clock_gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, |
| <&clock_gcc USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK>, |
| <&clock_rpmh RPMH_CXO_CLK>, |
| <&clock_gcc GCC_USB3_SEC_CLKREF_EN>, |
| <&clock_gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; |
| clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", |
| "pipe_clk_ext_src", "ref_clk_src", |
| "ref_clk", "com_aux_clk"; |
| |
| resets = <&clock_gcc GCC_USB3_PHY_SEC_BCR>, |
| <&clock_gcc GCC_USB3PHY_PHY_SEC_BCR>; |
| reset-names = "phy_reset", "phy_phy_reset"; |
| }; |
| }; |