| &soc { |
| pil_gpu: qcom,kgsl-hyp { |
| compatible = "qcom,pil-tz-generic"; |
| qcom,pas-id = <13>; |
| qcom,firmware-name = "a512_zap"; |
| }; |
| |
| msm_bus: qcom,kgsl-busmon{ |
| label = "kgsl-busmon"; |
| compatible = "qcom,kgsl-busmon"; |
| }; |
| |
| gpu_bw_tbl: gpu-bw-tbl { |
| compatible = "operating-points-v2"; |
| opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */ |
| opp-100 { opp-hz = /bits/ 64 < 381 >; }; /* 1.100 MHz */ |
| opp-150 { opp-hz = /bits/ 64 < 572 >; }; /* 2.150 MHz */ |
| opp-200 { opp-hz = /bits/ 64 < 762 >; }; /* 3.200 MHz */ |
| opp-300 { opp-hz = /bits/ 64 < 1144 >; }; /* 4.300 MHz */ |
| opp-412 { opp-hz = /bits/ 64 < 1571 >; }; /* 5.412 MHz */ |
| opp-547 { opp-hz = /bits/ 64 < 2086 >; }; /* 6.547 MHz */ |
| opp-681 { opp-hz = /bits/ 64 < 2597 >; }; /* 7.681 MHz */ |
| opp-768 { opp-hz = /bits/ 64 < 2929 >; }; /* 8.768 MHz */ |
| opp-1017 { opp-hz = /bits/ 64 < 3879 >; }; /* 9.1017 MHz */ |
| opp-1296 { opp-hz = /bits/ 64 < 4943 >; }; /* 10.1296 MHz */ |
| opp-1353 { opp-hz = /bits/ 64 < 5161 >; }; /* 11.1353 MHz */ |
| opp-1555 { opp-hz = /bits/ 64 < 5931 >; }; /* 12.1555 MHz */ |
| opp-1804 { opp-hz = /bits/ 64 < 6881 >; }; /* 13.1804 MHz */ |
| }; |
| |
| gpubw: qcom,gpubw { |
| compatible = "qcom,devbw"; |
| governor = "bw_vbif"; |
| qcom,src-dst-ports = <26 512>; |
| operating-points-v2 = <&gpu_bw_tbl>; |
| /* |
| * active-only flag is used while registering the bus |
| * governor. It helps release the bus vote when the CPU |
| * subsystem is inactive |
| */ |
| qcom,active-only; |
| }; |
| |
| msm_gpu: qcom,kgsl-3d0@5000000 { |
| label = "kgsl-3d0"; |
| compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; |
| status = "ok"; |
| reg = <0x5000000 0x40000 |
| 0x780000 0x6220>; |
| reg-names = "kgsl_3d0_reg_memory", "qfprom_memory"; |
| interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "kgsl_3d0_irq"; |
| qcom,id = <0>; |
| |
| qcom,chipid = <0x05010200>; |
| |
| qcom,initial-pwrlevel = <6>; |
| |
| /* <HZ/12> */ |
| qcom,idle-timeout = <80>; |
| |
| qcom,highest-bank-bit = <14>; |
| |
| /* size in bytes */ |
| qcom,snapshot-size = <1048576>; |
| #cooling-cells = <2>; |
| |
| clocks = <&clock_gfx GPUCC_GFX3D_CLK>, |
| <&clock_gcc GCC_GPU_CFG_AHB_CLK>, |
| <&clock_gfx GPUCC_RBBMTIMER_CLK>, |
| <&clock_gcc GCC_GPU_BIMC_GFX_CLK>, |
| <&clock_gcc GCC_BIMC_GFX_CLK>, |
| <&clock_gpu GPUCC_RBCPR_CLK>; |
| |
| clock-names = "core_clk", "iface_clk", "rbbmtimer_clk", |
| "mem_clk", "alt_mem_iface_clk", "rbcpr_clk"; |
| |
| /* Bus Scale Settings */ |
| qcom,gpubw-dev = <&gpubw>; |
| qcom,bus-control; |
| /* GPU to BIMC bus width, VBIF data transfer in 1 cycle */ |
| qcom,msm-bus,name = "grp3d"; |
| qcom,msm-bus,num-cases = <14>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <26 512 0 0>, |
| |
| <26 512 0 400000>, /* 1 bus=100 */ |
| <26 512 0 600000>, /* 2 bus=150 */ |
| <26 512 0 800000>, /* 3 bus=200 */ |
| <26 512 0 1200000>, /* 4 bus=300 */ |
| <26 512 0 1648000>, /* 5 bus=412 */ |
| <26 512 0 2188000>, /* 6 bus=547 */ |
| <26 512 0 2724000>, /* 7 bus=681 */ |
| <26 512 0 3072000>, /* 8 bus=768 */ |
| <26 512 0 4068000>, /* 9 bus=1017 */ |
| <26 512 0 5184000>, /* 10 bus=1296 */ |
| <26 512 0 5412000>, /* 11 bus=1353 */ |
| <26 512 0 6220000>, /* 12 bus=1555 */ |
| <26 512 0 7216000>; /* 13 bus=1804 */ |
| |
| /* GDSC regulator names */ |
| regulator-names = "vddcx", "vdd"; |
| /* GDSC oxili regulators */ |
| vddcx-supply = <&gdsc_gpu_cx>; |
| vdd-supply = <&gdsc_gpu_gx>; |
| |
| /* Cx ipeak limit supprt */ |
| qcom,gpu-cx-ipeak = <&cx_ipeak_lm 1>; |
| qcom,gpu-cx-ipeak-clk = <700000000>; |
| |
| /* CPU latency parameter */ |
| qcom,pm-qos-active-latency = <518>; |
| qcom,pm-qos-wakeup-latency = <518>; |
| |
| /* Quirks */ |
| qcom,gpu-quirk-dp2clockgating-disable; |
| qcom,gpu-quirk-lmloadkill-disable; |
| |
| /* Enable context aware freq. scaling */ |
| qcom,enable-ca-jump; |
| |
| /* Context aware jump busy penalty in us */ |
| qcom,ca-busy-penalty = <12000>; |
| |
| /* Context aware jump target power level */ |
| qcom,ca-target-pwrlevel = <4>; |
| |
| qcom,gpu-speed-bin = <0x41a0 0x1fe00000 21>; |
| |
| /* GPU Mempools */ |
| qcom,gpu-mempools { |
| #address-cells= <1>; |
| #size-cells = <0>; |
| compatible = "qcom,gpu-mempools"; |
| |
| qcom,mempool-max-pages = <32768>; |
| |
| /* 4K Page Pool configuration */ |
| qcom,gpu-mempool@0 { |
| reg = <0>; |
| qcom,mempool-page-size = <4096>; |
| }; |
| /* 64K Page Pool configuration */ |
| qcom,gpu-mempool@1 { |
| reg = <1>; |
| qcom,mempool-page-size = <65536>; |
| qcom,mempool-allocate; |
| }; |
| }; |
| |
| /* |
| * Speed-bin zero is default speed bin. |
| * For rest of the speed bins, speed-bin value |
| * is calulated as FMAX/4.8 MHz round up to zero |
| * decimal places. |
| */ |
| qcom,gpu-pwrlevel-bins { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| compatible="qcom,gpu-pwrlevel-bins"; |
| |
| qcom,gpu-pwrlevels-0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <0>; |
| |
| qcom,initial-pwrlevel = <6>; |
| |
| /* TURBO */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <750000000>; |
| qcom,bus-freq = <13>; |
| qcom,bus-min = <12>; |
| qcom,bus-max = <13>; |
| }; |
| |
| /* TURBO */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <700000000>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <11>; |
| qcom,bus-max = <13>; |
| }; |
| |
| /* NOM_L1 */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <647000000>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <10>; |
| qcom,bus-max = <12>; |
| }; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <588000000>; |
| qcom,bus-freq = <10>; |
| qcom,bus-min = <9>; |
| qcom,bus-max = <12>; |
| }; |
| |
| /* SVS_L1 */ |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <465000000>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@5 { |
| reg = <5>; |
| qcom,gpu-freq = <370000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <6>; |
| qcom,bus-max = <9>; |
| }; |
| |
| /* Low SVS */ |
| qcom,gpu-pwrlevel@6 { |
| reg = <6>; |
| qcom,gpu-freq = <266000000>; |
| qcom,bus-freq = <3>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <6>; |
| }; |
| |
| /* Min SVS */ |
| qcom,gpu-pwrlevel@7 { |
| reg = <7>; |
| qcom,gpu-freq = <160000000>; |
| qcom,bus-freq = <3>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <5>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@8 { |
| reg = <8>; |
| qcom,gpu-freq = <19200000>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <157>; |
| |
| qcom,initial-pwrlevel = <6>; |
| |
| /* TURBO */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <750000000>; |
| qcom,bus-freq = <13>; |
| qcom,bus-min = <12>; |
| qcom,bus-max = <13>; |
| }; |
| |
| /* TURBO */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <700000000>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <11>; |
| qcom,bus-max = <13>; |
| }; |
| |
| /* NOM_L1 */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <647000000>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <10>; |
| qcom,bus-max = <12>; |
| }; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <588000000>; |
| qcom,bus-freq = <10>; |
| qcom,bus-min = <9>; |
| qcom,bus-max = <12>; |
| }; |
| |
| /* SVS_L1 */ |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <465000000>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@5 { |
| reg = <5>; |
| qcom,gpu-freq = <370000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <6>; |
| qcom,bus-max = <9>; |
| }; |
| |
| /* Low SVS */ |
| qcom,gpu-pwrlevel@6 { |
| reg = <6>; |
| qcom,gpu-freq = <266000000>; |
| qcom,bus-freq = <3>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <6>; |
| }; |
| |
| /* Min SVS */ |
| qcom,gpu-pwrlevel@7 { |
| reg = <7>; |
| qcom,gpu-freq = <160000000>; |
| qcom,bus-freq = <3>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <5>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@8 { |
| reg = <8>; |
| qcom,gpu-freq = <19200000>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-2 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <146>; |
| |
| qcom,initial-pwrlevel = <5>; |
| |
| /* TURBO */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <700000000>; |
| qcom,bus-freq = <13>; |
| qcom,bus-min = <12>; |
| qcom,bus-max = <13>; |
| }; |
| |
| /* NOM_L1 */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <647000000>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <10>; |
| qcom,bus-max = <12>; |
| }; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <588000000>; |
| qcom,bus-freq = <10>; |
| qcom,bus-min = <9>; |
| qcom,bus-max = <12>; |
| }; |
| |
| /* SVS_L1 */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <465000000>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <370000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <6>; |
| qcom,bus-max = <9>; |
| }; |
| |
| /* Low SVS */ |
| qcom,gpu-pwrlevel@5 { |
| reg = <5>; |
| qcom,gpu-freq = <266000000>; |
| qcom,bus-freq = <3>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <6>; |
| }; |
| |
| /* Min SVS */ |
| qcom,gpu-pwrlevel@6 { |
| reg = <6>; |
| qcom,gpu-freq = <160000000>; |
| qcom,bus-freq = <3>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <5>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@7 { |
| reg = <7>; |
| qcom,gpu-freq = <19200000>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-3 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <135>; |
| |
| qcom,initial-pwrlevel = <4>; |
| |
| /* NOM_L1 */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <647000000>; |
| qcom,bus-freq = <13>; |
| qcom,bus-min = <12>; |
| qcom,bus-max = <13>; |
| }; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <588000000>; |
| qcom,bus-freq = <10>; |
| qcom,bus-min = <9>; |
| qcom,bus-max = <12>; |
| }; |
| |
| /* SVS_L1 */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <465000000>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <370000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <6>; |
| qcom,bus-max = <9>; |
| }; |
| |
| /* Low SVS */ |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <266000000>; |
| qcom,bus-freq = <3>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <6>; |
| }; |
| |
| /* Min SVS */ |
| qcom,gpu-pwrlevel@5 { |
| reg = <5>; |
| qcom,gpu-freq = <160000000>; |
| qcom,bus-freq = <3>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <5>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@6 { |
| reg = <6>; |
| qcom,gpu-freq = <19200000>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-4 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <78>; |
| |
| qcom,initial-pwrlevel = <1>; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <370000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <6>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* Low SVS */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <266000000>; |
| qcom,bus-freq = <3>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <6>; |
| }; |
| |
| /* Min SVS */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <160000000>; |
| qcom,bus-freq = <3>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <5>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <19200000>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-5 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <90>; |
| |
| qcom,initial-pwrlevel = <2>; |
| |
| /* SVS_L1 */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <430000000>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <10>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <370000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <6>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* Low SVS */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <266000000>; |
| qcom,bus-freq = <3>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <6>; |
| }; |
| |
| /* Min SVS */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <160000000>; |
| qcom,bus-freq = <3>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <5>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <19200000>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-6 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <122>; |
| |
| qcom,initial-pwrlevel = <3>; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <585000000>; |
| qcom,bus-freq = <12>; |
| qcom,bus-min = <11>; |
| qcom,bus-max = <12>; |
| }; |
| |
| /* SVS_L1 */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <465000000>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <370000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <6>; |
| qcom,bus-max = <9>; |
| }; |
| |
| /* Low SVS */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <266000000>; |
| qcom,bus-freq = <3>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <6>; |
| }; |
| |
| /* Min SVS */ |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <160000000>; |
| qcom,bus-freq = <3>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <5>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@5 { |
| reg = <5>; |
| qcom,gpu-freq = <19200000>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| }; |
| }; |
| |
| kgsl_msm_iommu: qcom,kgsl-iommu { |
| compatible = "qcom,kgsl-smmu-v2"; |
| |
| reg = <0x05040000 0x10000>; |
| qcom,protect = <0x40000 0x10000>; |
| qcom,micro-mmu-control = <0x6000>; |
| |
| clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>, |
| <&clock_gcc GCC_GPU_BIMC_GFX_CLK>, |
| <&clock_gcc GCC_BIMC_GFX_CLK>; |
| |
| clock-names = "iface_clk", "mem_clk", "alt_mem_iface_clk"; |
| |
| qcom,secure_align_mask = <0xfff>; |
| qcom,retention; |
| qcom,hyp_secure_alloc; |
| |
| gfx3d_user: gfx3d_user { |
| compatible = "qcom,smmu-kgsl-cb"; |
| label = "gfx3d_user"; |
| iommus = <&kgsl_smmu 0>; |
| qcom,iommu-dma = "disabled"; |
| qcom,gpu-offset = <0x48000>; |
| }; |
| |
| gfx3d_secure: gfx3d_secure { |
| compatible = "qcom,smmu-kgsl-cb"; |
| iommus = <&kgsl_smmu 2>; |
| qcom,iommu-dma = "disabled"; |
| }; |
| }; |
| }; |