| /* SPDX-License-Identifier: GPL-2.0-only */ |
| /* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ |
| |
| #ifndef _DT_BINDINGS_CLK_QCOM_GCC_LITO_H |
| #define _DT_BINDINGS_CLK_QCOM_GCC_LITO_H |
| |
| #define GPLL0 0 |
| #define GPLL0_OUT_EVEN 1 |
| #define GPLL6 2 |
| #define GPLL9 3 |
| #define GCC_CAMERA_HF_AXI_CLK 4 |
| #define GCC_CAMERA_SF_AXI_CLK 5 |
| #define GCC_CAMERA_THROTTLE_HF_AXI_CLK 6 |
| #define GCC_CAMERA_THROTTLE_SF_AXI_CLK 7 |
| #define GCC_CAMERA_XO_CLK 8 |
| #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 9 |
| #define GCC_CPUSS_AHB_CLK 10 |
| #define GCC_CPUSS_AHB_CLK_SRC 11 |
| #define GCC_CPUSS_RBCPR_CLK 12 |
| #define GCC_DDRSS_GPU_AXI_CLK 13 |
| #define GCC_DISP_AHB_CLK 14 |
| #define GCC_DISP_GPLL0_CLK_SRC 15 |
| #define GCC_DISP_HF_AXI_CLK 16 |
| #define GCC_DISP_SF_AXI_CLK 17 |
| #define GCC_DISP_THROTTLE_HF_AXI_CLK 18 |
| #define GCC_DISP_THROTTLE_SF_AXI_CLK 19 |
| #define GCC_DISP_XO_CLK 20 |
| #define GCC_DPM_AHB_CLK 21 |
| #define GCC_DPM_CLK 22 |
| #define GCC_DPM_CLK_SRC 23 |
| #define GCC_GP1_CLK 25 |
| #define GCC_GP1_CLK_SRC 26 |
| #define GCC_GP2_CLK 27 |
| #define GCC_GP2_CLK_SRC 28 |
| #define GCC_GP3_CLK 29 |
| #define GCC_GP3_CLK_SRC 30 |
| #define GCC_GPU_CFG_AHB_CLK 31 |
| #define GCC_GPU_GPLL0_CLK_SRC 32 |
| #define GCC_GPU_GPLL0_DIV_CLK_SRC 33 |
| #define GCC_GPU_IREF_CLK 34 |
| #define GCC_GPU_MEMNOC_GFX_CLK 35 |
| #define GCC_GPU_SNOC_DVM_GFX_CLK 36 |
| #define GCC_NPU_AXI_CLK 37 |
| #define GCC_NPU_BWMON2_AXI_CLK 38 |
| #define GCC_NPU_BWMON_AXI_CLK 39 |
| #define GCC_NPU_BWMON_CFG_AHB_CLK 40 |
| #define GCC_NPU_CFG_AHB_CLK 41 |
| #define GCC_NPU_DMA_CLK 42 |
| #define GCC_NPU_DMA_CLK_SRC 43 |
| #define GCC_NPU_GPLL0_CLK_SRC 44 |
| #define GCC_NPU_GPLL0_DIV_CLK_SRC 45 |
| #define GCC_PDM2_CLK 46 |
| #define GCC_PDM2_CLK_SRC 47 |
| #define GCC_PDM_AHB_CLK 48 |
| #define GCC_PDM_XO4_CLK 49 |
| #define GCC_PRNG_AHB_CLK 50 |
| #define GCC_QMIP_CAMERA_NRT_AHB_CLK 51 |
| #define GCC_QMIP_CAMERA_RT_AHB_CLK 52 |
| #define GCC_QMIP_DISP_AHB_CLK 53 |
| #define GCC_QMIP_RT_DISP_AHB_CLK 54 |
| #define GCC_QMIP_VIDEO_CVP_AHB_CLK 55 |
| #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 56 |
| #define GCC_QUPV3_WRAP0_CORE_2X_CLK 57 |
| #define GCC_QUPV3_WRAP0_CORE_CLK 58 |
| #define GCC_QUPV3_WRAP0_S0_CLK 59 |
| #define GCC_QUPV3_WRAP0_S0_CLK_SRC 60 |
| #define GCC_QUPV3_WRAP0_S1_CLK 61 |
| #define GCC_QUPV3_WRAP0_S1_CLK_SRC 62 |
| #define GCC_QUPV3_WRAP0_S2_CLK 63 |
| #define GCC_QUPV3_WRAP0_S2_CLK_SRC 64 |
| #define GCC_QUPV3_WRAP0_S3_CLK 65 |
| #define GCC_QUPV3_WRAP0_S3_CLK_SRC 66 |
| #define GCC_QUPV3_WRAP0_S4_CLK 67 |
| #define GCC_QUPV3_WRAP0_S4_CLK_SRC 68 |
| #define GCC_QUPV3_WRAP0_S5_CLK 69 |
| #define GCC_QUPV3_WRAP0_S5_CLK_SRC 70 |
| #define GCC_QUPV3_WRAP1_CORE_2X_CLK 71 |
| #define GCC_QUPV3_WRAP1_CORE_CLK 72 |
| #define GCC_QUPV3_WRAP1_S0_CLK 73 |
| #define GCC_QUPV3_WRAP1_S0_CLK_SRC 74 |
| #define GCC_QUPV3_WRAP1_S1_CLK 75 |
| #define GCC_QUPV3_WRAP1_S1_CLK_SRC 76 |
| #define GCC_QUPV3_WRAP1_S2_CLK 77 |
| #define GCC_QUPV3_WRAP1_S2_CLK_SRC 78 |
| #define GCC_QUPV3_WRAP1_S3_CLK 79 |
| #define GCC_QUPV3_WRAP1_S3_CLK_SRC 80 |
| #define GCC_QUPV3_WRAP1_S4_CLK 81 |
| #define GCC_QUPV3_WRAP1_S4_CLK_SRC 82 |
| #define GCC_QUPV3_WRAP1_S5_CLK 83 |
| #define GCC_QUPV3_WRAP1_S5_CLK_SRC 84 |
| #define GCC_QUPV3_WRAP_0_M_AHB_CLK 85 |
| #define GCC_QUPV3_WRAP_0_S_AHB_CLK 86 |
| #define GCC_QUPV3_WRAP_1_M_AHB_CLK 87 |
| #define GCC_QUPV3_WRAP_1_S_AHB_CLK 88 |
| #define GCC_SDCC1_AHB_CLK 89 |
| #define GCC_SDCC1_APPS_CLK 90 |
| #define GCC_SDCC1_APPS_CLK_SRC 91 |
| #define GCC_SDCC1_ICE_CORE_CLK 92 |
| #define GCC_SDCC1_ICE_CORE_CLK_SRC 93 |
| #define GCC_SDCC2_AHB_CLK 94 |
| #define GCC_SDCC2_APPS_CLK 95 |
| #define GCC_SDCC2_APPS_CLK_SRC 96 |
| #define GCC_SDCC4_AHB_CLK 97 |
| #define GCC_SDCC4_APPS_CLK 98 |
| #define GCC_SDCC4_APPS_CLK_SRC 99 |
| #define GCC_SYS_NOC_CPUSS_AHB_CLK 100 |
| #define GCC_UFS_1X_CLKREF_CLK 101 |
| #define GCC_UFS_PHY_AHB_CLK 102 |
| #define GCC_UFS_PHY_AXI_CLK 103 |
| #define GCC_UFS_PHY_AXI_CLK_SRC 104 |
| #define GCC_UFS_PHY_ICE_CORE_CLK 105 |
| #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 106 |
| #define GCC_UFS_PHY_PHY_AUX_CLK 107 |
| #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 108 |
| #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 109 |
| #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 110 |
| #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 111 |
| #define GCC_UFS_PHY_UNIPRO_CORE_CLK 112 |
| #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 113 |
| #define GCC_USB30_PRIM_MASTER_CLK 114 |
| #define GCC_USB30_PRIM_MASTER_CLK_SRC 115 |
| #define GCC_USB30_PRIM_MOCK_UTMI_CLK 116 |
| #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 117 |
| #define GCC_USB30_PRIM_SLEEP_CLK 118 |
| #define GCC_USB3_PRIM_CLKREF_CLK 119 |
| #define GCC_USB3_PRIM_PHY_AUX_CLK 120 |
| #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 121 |
| #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 122 |
| #define GCC_USB3_PRIM_PHY_PIPE_CLK 123 |
| #define GCC_VIDEO_AHB_CLK 124 |
| #define GCC_VIDEO_AXI_CLK 125 |
| #define GCC_VIDEO_THROTTLE1_AXI_CLK 126 |
| #define GCC_VIDEO_THROTTLE_AXI_CLK 127 |
| #define GCC_VIDEO_XO_CLK 128 |
| #define GCC_AGGRE_UFS_PHY_AXI_CLK 129 |
| #define GCC_AGGRE_USB3_PRIM_AXI_CLK 130 |
| #define GCC_BOOT_ROM_AHB_CLK 131 |
| #define GCC_CAMERA_AHB_CLK 132 |
| #define GCC_CPUSS_GNOC_CLK 133 |
| |
| #define GCC_DPM_BCR 0 |
| #define GCC_GPU_BCR 1 |
| #define GCC_MMSS_BCR 2 |
| #define GCC_NPU_BWMON_BCR 3 |
| #define GCC_NPU_BCR 4 |
| #define GCC_PDM_BCR 5 |
| #define GCC_PRNG_BCR 6 |
| #define GCC_QUPV3_WRAPPER_0_BCR 7 |
| #define GCC_QUPV3_WRAPPER_1_BCR 8 |
| #define GCC_SDCC1_BCR 9 |
| #define GCC_SDCC2_BCR 10 |
| #define GCC_SDCC4_BCR 11 |
| #define GCC_UFS_PHY_BCR 12 |
| #define GCC_USB30_PRIM_BCR 13 |
| #define GCC_USB_PHY_CFG_AHB2PHY_BCR 14 |
| |
| #endif |