/* | |
* Devices shared by all Juno boards | |
*/ | |
memtimer: timer@2a810000 { | |
compatible = "arm,armv7-timer-mem"; | |
reg = <0x0 0x2a810000 0x0 0x10000>; | |
clock-frequency = <50000000>; | |
#address-cells = <2>; | |
#size-cells = <2>; | |
ranges; | |
status = "disabled"; | |
frame@2a830000 { | |
frame-number = <1>; | |
interrupts = <0 60 4>; | |
reg = <0x0 0x2a830000 0x0 0x10000>; | |
}; | |
}; | |
mailbox: mhu@2b1f0000 { | |
compatible = "arm,mhu", "arm,primecell"; | |
reg = <0x0 0x2b1f0000 0x0 0x1000>; | |
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, | |
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
interrupt-names = "mhu_lpri_rx", | |
"mhu_hpri_rx"; | |
#mbox-cells = <1>; | |
clocks = <&soc_refclk100mhz>; | |
clock-names = "apb_pclk"; | |
}; | |
gic: interrupt-controller@2c010000 { | |
compatible = "arm,gic-400", "arm,cortex-a15-gic"; | |
reg = <0x0 0x2c010000 0 0x1000>, | |
<0x0 0x2c02f000 0 0x2000>, | |
<0x0 0x2c04f000 0 0x2000>, | |
<0x0 0x2c06f000 0 0x2000>; | |
#address-cells = <2>; | |
#interrupt-cells = <3>; | |
#size-cells = <2>; | |
interrupt-controller; | |
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; | |
ranges = <0 0 0 0x2c1c0000 0 0x40000>; | |
v2m_0: v2m@0 { | |
compatible = "arm,gic-v2m-frame"; | |
msi-controller; | |
reg = <0 0 0 0x1000>; | |
}; | |
}; | |
timer { | |
compatible = "arm,armv8-timer"; | |
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, | |
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, | |
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, | |
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; | |
}; | |
/* | |
* Juno TRMs specify the size for these coresight components as 64K. | |
* The actual size is just 4K though 64K is reserved. Access to the | |
* unmapped reserved region results in a DECERR response. | |
*/ | |
etf@20010000 { | |
compatible = "arm,coresight-tmc", "arm,primecell"; | |
reg = <0 0x20010000 0 0x1000>; | |
clocks = <&soc_smc50mhz>; | |
clock-names = "apb_pclk"; | |
power-domains = <&scpi_devpd 0>; | |
ports { | |
#address-cells = <1>; | |
#size-cells = <0>; | |
/* input port */ | |
port@0 { | |
reg = <0>; | |
etf_in_port: endpoint { | |
slave-mode; | |
remote-endpoint = <&main_funnel_out_port>; | |
}; | |
}; | |
/* output port */ | |
port@1 { | |
reg = <0>; | |
etf_out_port: endpoint { | |
remote-endpoint = <&replicator_in_port0>; | |
}; | |
}; | |
}; | |
}; | |
tpiu@20030000 { | |
compatible = "arm,coresight-tpiu", "arm,primecell"; | |
reg = <0 0x20030000 0 0x1000>; | |
clocks = <&soc_smc50mhz>; | |
clock-names = "apb_pclk"; | |
power-domains = <&scpi_devpd 0>; | |
port { | |
tpiu_in_port: endpoint { | |
slave-mode; | |
remote-endpoint = <&replicator_out_port0>; | |
}; | |
}; | |
}; | |
main-funnel@20040000 { | |
compatible = "arm,coresight-funnel", "arm,primecell"; | |
reg = <0 0x20040000 0 0x1000>; | |
clocks = <&soc_smc50mhz>; | |
clock-names = "apb_pclk"; | |
power-domains = <&scpi_devpd 0>; | |
ports { | |
#address-cells = <1>; | |
#size-cells = <0>; | |
port@0 { | |
reg = <0>; | |
main_funnel_out_port: endpoint { | |
remote-endpoint = <&etf_in_port>; | |
}; | |
}; | |
port@1 { | |
reg = <0>; | |
main_funnel_in_port0: endpoint { | |
slave-mode; | |
remote-endpoint = <&cluster0_funnel_out_port>; | |
}; | |
}; | |
port@2 { | |
reg = <1>; | |
main_funnel_in_port1: endpoint { | |
slave-mode; | |
remote-endpoint = <&cluster1_funnel_out_port>; | |
}; | |
}; | |
}; | |
}; | |
etr@20070000 { | |
compatible = "arm,coresight-tmc", "arm,primecell"; | |
reg = <0 0x20070000 0 0x1000>; | |
clocks = <&soc_smc50mhz>; | |
clock-names = "apb_pclk"; | |
power-domains = <&scpi_devpd 0>; | |
port { | |
etr_in_port: endpoint { | |
slave-mode; | |
remote-endpoint = <&replicator_out_port1>; | |
}; | |
}; | |
}; | |
etm0: etm@22040000 { | |
compatible = "arm,coresight-etm4x", "arm,primecell"; | |
reg = <0 0x22040000 0 0x1000>; | |
clocks = <&soc_smc50mhz>; | |
clock-names = "apb_pclk"; | |
power-domains = <&scpi_devpd 0>; | |
port { | |
cluster0_etm0_out_port: endpoint { | |
remote-endpoint = <&cluster0_funnel_in_port0>; | |
}; | |
}; | |
}; | |
cluster0-funnel@220c0000 { | |
compatible = "arm,coresight-funnel", "arm,primecell"; | |
reg = <0 0x220c0000 0 0x1000>; | |
clocks = <&soc_smc50mhz>; | |
clock-names = "apb_pclk"; | |
power-domains = <&scpi_devpd 0>; | |
ports { | |
#address-cells = <1>; | |
#size-cells = <0>; | |
port@0 { | |
reg = <0>; | |
cluster0_funnel_out_port: endpoint { | |
remote-endpoint = <&main_funnel_in_port0>; | |
}; | |
}; | |
port@1 { | |
reg = <0>; | |
cluster0_funnel_in_port0: endpoint { | |
slave-mode; | |
remote-endpoint = <&cluster0_etm0_out_port>; | |
}; | |
}; | |
port@2 { | |
reg = <1>; | |
cluster0_funnel_in_port1: endpoint { | |
slave-mode; | |
remote-endpoint = <&cluster0_etm1_out_port>; | |
}; | |
}; | |
}; | |
}; | |
etm1: etm@22140000 { | |
compatible = "arm,coresight-etm4x", "arm,primecell"; | |
reg = <0 0x22140000 0 0x1000>; | |
clocks = <&soc_smc50mhz>; | |
clock-names = "apb_pclk"; | |
power-domains = <&scpi_devpd 0>; | |
port { | |
cluster0_etm1_out_port: endpoint { | |
remote-endpoint = <&cluster0_funnel_in_port1>; | |
}; | |
}; | |
}; | |
etm2: etm@23040000 { | |
compatible = "arm,coresight-etm4x", "arm,primecell"; | |
reg = <0 0x23040000 0 0x1000>; | |
clocks = <&soc_smc50mhz>; | |
clock-names = "apb_pclk"; | |
power-domains = <&scpi_devpd 0>; | |
port { | |
cluster1_etm0_out_port: endpoint { | |
remote-endpoint = <&cluster1_funnel_in_port0>; | |
}; | |
}; | |
}; | |
cluster1-funnel@230c0000 { | |
compatible = "arm,coresight-funnel", "arm,primecell"; | |
reg = <0 0x230c0000 0 0x1000>; | |
clocks = <&soc_smc50mhz>; | |
clock-names = "apb_pclk"; | |
power-domains = <&scpi_devpd 0>; | |
ports { | |
#address-cells = <1>; | |
#size-cells = <0>; | |
port@0 { | |
reg = <0>; | |
cluster1_funnel_out_port: endpoint { | |
remote-endpoint = <&main_funnel_in_port1>; | |
}; | |
}; | |
port@1 { | |
reg = <0>; | |
cluster1_funnel_in_port0: endpoint { | |
slave-mode; | |
remote-endpoint = <&cluster1_etm0_out_port>; | |
}; | |
}; | |
port@2 { | |
reg = <1>; | |
cluster1_funnel_in_port1: endpoint { | |
slave-mode; | |
remote-endpoint = <&cluster1_etm1_out_port>; | |
}; | |
}; | |
port@3 { | |
reg = <2>; | |
cluster1_funnel_in_port2: endpoint { | |
slave-mode; | |
remote-endpoint = <&cluster1_etm2_out_port>; | |
}; | |
}; | |
port@4 { | |
reg = <3>; | |
cluster1_funnel_in_port3: endpoint { | |
slave-mode; | |
remote-endpoint = <&cluster1_etm3_out_port>; | |
}; | |
}; | |
}; | |
}; | |
etm3: etm@23140000 { | |
compatible = "arm,coresight-etm4x", "arm,primecell"; | |
reg = <0 0x23140000 0 0x1000>; | |
clocks = <&soc_smc50mhz>; | |
clock-names = "apb_pclk"; | |
power-domains = <&scpi_devpd 0>; | |
port { | |
cluster1_etm1_out_port: endpoint { | |
remote-endpoint = <&cluster1_funnel_in_port1>; | |
}; | |
}; | |
}; | |
etm4: etm@23240000 { | |
compatible = "arm,coresight-etm4x", "arm,primecell"; | |
reg = <0 0x23240000 0 0x1000>; | |
clocks = <&soc_smc50mhz>; | |
clock-names = "apb_pclk"; | |
power-domains = <&scpi_devpd 0>; | |
port { | |
cluster1_etm2_out_port: endpoint { | |
remote-endpoint = <&cluster1_funnel_in_port2>; | |
}; | |
}; | |
}; | |
etm5: etm@23340000 { | |
compatible = "arm,coresight-etm4x", "arm,primecell"; | |
reg = <0 0x23340000 0 0x1000>; | |
clocks = <&soc_smc50mhz>; | |
clock-names = "apb_pclk"; | |
power-domains = <&scpi_devpd 0>; | |
port { | |
cluster1_etm3_out_port: endpoint { | |
remote-endpoint = <&cluster1_funnel_in_port3>; | |
}; | |
}; | |
}; | |
coresight-replicator { | |
/* | |
* Non-configurable replicators don't show up on the | |
* AMBA bus. As such no need to add "arm,primecell". | |
*/ | |
compatible = "arm,coresight-replicator"; | |
ports { | |
#address-cells = <1>; | |
#size-cells = <0>; | |
/* replicator output ports */ | |
port@0 { | |
reg = <0>; | |
replicator_out_port0: endpoint { | |
remote-endpoint = <&tpiu_in_port>; | |
}; | |
}; | |
port@1 { | |
reg = <1>; | |
replicator_out_port1: endpoint { | |
remote-endpoint = <&etr_in_port>; | |
}; | |
}; | |
/* replicator input port */ | |
port@2 { | |
reg = <0>; | |
replicator_in_port0: endpoint { | |
slave-mode; | |
remote-endpoint = <&etf_out_port>; | |
}; | |
}; | |
}; | |
}; | |
sram: sram@2e000000 { | |
compatible = "arm,juno-sram-ns", "mmio-sram"; | |
reg = <0x0 0x2e000000 0x0 0x8000>; | |
#address-cells = <1>; | |
#size-cells = <1>; | |
ranges = <0 0x0 0x2e000000 0x8000>; | |
cpu_scp_lpri: scp-shmem@0 { | |
compatible = "arm,juno-scp-shmem"; | |
reg = <0x0 0x200>; | |
}; | |
cpu_scp_hpri: scp-shmem@200 { | |
compatible = "arm,juno-scp-shmem"; | |
reg = <0x200 0x200>; | |
}; | |
}; | |
pcie_ctlr: pcie-controller@40000000 { | |
compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic"; | |
device_type = "pci"; | |
reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */ | |
bus-range = <0 255>; | |
linux,pci-domain = <0>; | |
#address-cells = <3>; | |
#size-cells = <2>; | |
dma-coherent; | |
ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>, | |
<0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, | |
<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; | |
#interrupt-cells = <1>; | |
interrupt-map-mask = <0 0 0 7>; | |
interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>, | |
<0 0 0 2 &gic 0 0 0 137 4>, | |
<0 0 0 3 &gic 0 0 0 138 4>, | |
<0 0 0 4 &gic 0 0 0 139 4>; | |
msi-parent = <&v2m_0>; | |
status = "disabled"; | |
}; | |
scpi { | |
compatible = "arm,scpi"; | |
mboxes = <&mailbox 1>; | |
shmem = <&cpu_scp_hpri>; | |
clocks { | |
compatible = "arm,scpi-clocks"; | |
scpi_dvfs: scpi-dvfs { | |
compatible = "arm,scpi-dvfs-clocks"; | |
#clock-cells = <1>; | |
clock-indices = <0>, <1>, <2>; | |
clock-output-names = "atlclk", "aplclk","gpuclk"; | |
}; | |
scpi_clk: scpi-clk { | |
compatible = "arm,scpi-variable-clocks"; | |
#clock-cells = <1>; | |
clock-indices = <3>; | |
clock-output-names = "pxlclk"; | |
}; | |
}; | |
scpi_devpd: scpi-power-domains { | |
compatible = "arm,scpi-power-domains"; | |
num-domains = <2>; | |
#power-domain-cells = <1>; | |
}; | |
scpi_sensors0: sensors { | |
compatible = "arm,scpi-sensors"; | |
#thermal-sensor-cells = <1>; | |
}; | |
}; | |
thermal-zones { | |
pmic { | |
polling-delay = <1000>; | |
polling-delay-passive = <100>; | |
thermal-sensors = <&scpi_sensors0 0>; | |
}; | |
soc { | |
polling-delay = <1000>; | |
polling-delay-passive = <100>; | |
thermal-sensors = <&scpi_sensors0 3>; | |
}; | |
big_cluster_thermal_zone: big_cluster { | |
polling-delay = <1000>; | |
polling-delay-passive = <100>; | |
thermal-sensors = <&scpi_sensors0 21>; | |
status = "disabled"; | |
}; | |
little_cluster_thermal_zone: little_cluster { | |
polling-delay = <1000>; | |
polling-delay-passive = <100>; | |
thermal-sensors = <&scpi_sensors0 22>; | |
status = "disabled"; | |
}; | |
gpu0_thermal_zone: gpu0 { | |
polling-delay = <1000>; | |
polling-delay-passive = <100>; | |
thermal-sensors = <&scpi_sensors0 23>; | |
status = "disabled"; | |
}; | |
gpu1_thermal_zone: gpu1 { | |
polling-delay = <1000>; | |
polling-delay-passive = <100>; | |
thermal-sensors = <&scpi_sensors0 24>; | |
status = "disabled"; | |
}; | |
}; | |
/include/ "juno-clocks.dtsi" | |
dma@7ff00000 { | |
compatible = "arm,pl330", "arm,primecell"; | |
reg = <0x0 0x7ff00000 0 0x1000>; | |
#dma-cells = <1>; | |
#dma-channels = <8>; | |
#dma-requests = <32>; | |
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, | |
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, | |
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, | |
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, | |
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, | |
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&soc_faxiclk>; | |
clock-names = "apb_pclk"; | |
}; | |
hdlcd@7ff50000 { | |
compatible = "arm,hdlcd"; | |
reg = <0 0x7ff50000 0 0x1000>; | |
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&scpi_clk 3>; | |
clock-names = "pxlclk"; | |
port { | |
hdlcd1_output: hdlcd1-endpoint { | |
remote-endpoint = <&tda998x_1_input>; | |
}; | |
}; | |
}; | |
hdlcd@7ff60000 { | |
compatible = "arm,hdlcd"; | |
reg = <0 0x7ff60000 0 0x1000>; | |
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&scpi_clk 3>; | |
clock-names = "pxlclk"; | |
port { | |
hdlcd0_output: hdlcd0-endpoint { | |
remote-endpoint = <&tda998x_0_input>; | |
}; | |
}; | |
}; | |
soc_uart0: uart@7ff80000 { | |
compatible = "arm,pl011", "arm,primecell"; | |
reg = <0x0 0x7ff80000 0x0 0x1000>; | |
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&soc_uartclk>, <&soc_refclk100mhz>; | |
clock-names = "uartclk", "apb_pclk"; | |
}; | |
i2c@7ffa0000 { | |
compatible = "snps,designware-i2c"; | |
reg = <0x0 0x7ffa0000 0x0 0x1000>; | |
#address-cells = <1>; | |
#size-cells = <0>; | |
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; | |
clock-frequency = <400000>; | |
i2c-sda-hold-time-ns = <500>; | |
clocks = <&soc_smc50mhz>; | |
hdmi-transmitter@70 { | |
compatible = "nxp,tda998x"; | |
reg = <0x70>; | |
port { | |
tda998x_0_input: tda998x-0-endpoint { | |
remote-endpoint = <&hdlcd0_output>; | |
}; | |
}; | |
}; | |
hdmi-transmitter@71 { | |
compatible = "nxp,tda998x"; | |
reg = <0x71>; | |
port { | |
tda998x_1_input: tda998x-1-endpoint { | |
remote-endpoint = <&hdlcd1_output>; | |
}; | |
}; | |
}; | |
}; | |
ohci@7ffb0000 { | |
compatible = "generic-ohci"; | |
reg = <0x0 0x7ffb0000 0x0 0x10000>; | |
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&soc_usb48mhz>; | |
}; | |
ehci@7ffc0000 { | |
compatible = "generic-ehci"; | |
reg = <0x0 0x7ffc0000 0x0 0x10000>; | |
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&soc_usb48mhz>; | |
}; | |
memory-controller@7ffd0000 { | |
compatible = "arm,pl354", "arm,primecell"; | |
reg = <0 0x7ffd0000 0 0x1000>; | |
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, | |
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
clocks = <&soc_smc50mhz>; | |
clock-names = "apb_pclk"; | |
}; | |
memory@80000000 { | |
device_type = "memory"; | |
/* last 16MB of the first memory area is reserved for secure world use by firmware */ | |
reg = <0x00000000 0x80000000 0x0 0x7f000000>, | |
<0x00000008 0x80000000 0x1 0x80000000>; | |
}; | |
smb@08000000 { | |
compatible = "simple-bus"; | |
#address-cells = <2>; | |
#size-cells = <1>; | |
ranges = <0 0 0 0x08000000 0x04000000>, | |
<1 0 0 0x14000000 0x04000000>, | |
<2 0 0 0x18000000 0x04000000>, | |
<3 0 0 0x1c000000 0x04000000>, | |
<4 0 0 0x0c000000 0x04000000>, | |
<5 0 0 0x10000000 0x04000000>; | |
#interrupt-cells = <1>; | |
interrupt-map-mask = <0 0 15>; | |
interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>, | |
<0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>, | |
<0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>, | |
<0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>, | |
<0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>, | |
<0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>, | |
<0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>, | |
<0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>, | |
<0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>, | |
<0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>, | |
<0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>, | |
<0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>, | |
<0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>; | |
/include/ "juno-motherboard.dtsi" | |
}; | |
site2: tlx@60000000 { | |
compatible = "simple-bus"; | |
#address-cells = <1>; | |
#size-cells = <1>; | |
ranges = <0 0 0x60000000 0x10000000>; | |
#interrupt-cells = <1>; | |
interrupt-map-mask = <0 0>; | |
interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>; | |
}; |