| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. |
| */ |
| |
| &soc { |
| tlmm: pinctrl@f000000 { |
| compatible = "qcom,kona-pinctrl"; |
| reg = <0x0F000000 0x1000000>; |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| |
| trigout_a: trigout_a { |
| mux { |
| pins = "gpio2"; |
| function = "qdss_cti"; |
| }; |
| |
| config { |
| pins = "gpio2"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qupv3_se2_2uart_pins: qupv3_se2_2uart_pins { |
| qupv3_se2_2uart_active: qupv3_se2_2uart_active { |
| mux { |
| pins = "gpio117", "gpio118"; |
| function = "qup2"; |
| }; |
| |
| config { |
| pins = "gpio117", "gpio118"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| qupv3_se2_2uart_sleep: qupv3_se2_2uart_sleep { |
| mux { |
| pins = "gpio117", "gpio118"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio117", "gpio118"; |
| drive-strength = <2>; |
| bias-pull-down; |
| }; |
| }; |
| }; |
| |
| qupv3_se6_4uart_pins: qupv3_se6_4uart_pins { |
| qupv3_se6_ctsrx: qupv3_se6_ctsrx { |
| mux { |
| pins = "gpio16", "gpio19"; |
| function = "qup6"; |
| }; |
| |
| config { |
| pins = "gpio16", "gpio19"; |
| drive-strength = <2>; |
| bias-no-pull; |
| }; |
| }; |
| |
| qupv3_se6_rts: qupv3_se6_rts { |
| mux { |
| pins = "gpio17"; |
| function = "qup6"; |
| }; |
| |
| config { |
| pins = "gpio17"; |
| drive-strength = <2>; |
| bias-pull-down; |
| }; |
| }; |
| |
| qupv3_se6_tx: qupv3_se6_tx { |
| mux { |
| pins = "gpio18"; |
| function = "qup6"; |
| }; |
| |
| config { |
| pins = "gpio18"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| }; |
| }; |
| |
| qupv3_se12_2uart_pins: qupv3_se12_2uart_pins { |
| qupv3_se12_2uart_active: qupv3_se12_2uart_active { |
| mux { |
| pins = "gpio34", "gpio35"; |
| function = "qup12"; |
| }; |
| |
| config { |
| pins = "gpio34", "gpio35"; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| qupv3_se12_2uart_sleep: qupv3_se12_2uart_sleep { |
| mux { |
| pins = "gpio34", "gpio35"; |
| drive-strength = <2>; |
| bias-pull-down; |
| }; |
| |
| config { |
| pins = "gpio34", "gpio35"; |
| drive-strength = <2>; |
| bias-pull-down; |
| }; |
| }; |
| }; |
| |
| qupv3_se17_4uart_pins: qupv3_se17_4uart_pins { |
| qupv3_se17_ctsrx: qupv3_se17_ctsrx { |
| mux { |
| pins = "gpio52", "gpio55"; |
| function = "qup17"; |
| }; |
| |
| config { |
| pins = "gpio52", "gpio55"; |
| drive-strength = <2>; |
| bias-no-pull; |
| }; |
| }; |
| |
| qupv3_se17_rts: qupv3_se17_rts { |
| mux { |
| pins = "gpio53"; |
| function = "qup17"; |
| }; |
| |
| config { |
| pins = "gpio53"; |
| drive-strength = <2>; |
| bias-pull-down; |
| }; |
| }; |
| |
| qupv3_se17_tx: qupv3_se17_tx { |
| mux { |
| pins = "gpio54"; |
| function = "qup17"; |
| }; |
| |
| config { |
| pins = "gpio54"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| }; |
| }; |
| |
| qupv3_se18_2uart_pins: qupv3_se18_2uart_pins { |
| qupv3_se18_rx: qupv3_se18_rx { |
| mux { |
| pins = "gpio59"; |
| function = "qup18"; |
| }; |
| |
| config { |
| pins = "gpio59"; |
| drive-strength = <2>; |
| bias-no-pull; |
| }; |
| }; |
| |
| qupv3_se18_tx: qupv3_se18_tx { |
| mux { |
| pins = "gpio58"; |
| function = "qup18"; |
| }; |
| |
| config { |
| pins = "gpio58"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| }; |
| }; |
| |
| ufs_dev_reset_assert: ufs_dev_reset_assert { |
| config { |
| pins = "ufs_reset"; |
| bias-pull-down; /* default: pull down */ |
| /* |
| * UFS_RESET driver strengths are having |
| * different values/steps compared to typical |
| * GPIO drive strengths. |
| * |
| * Following table clarifies: |
| * |
| * HDRV value | UFS_RESET | Typical GPIO |
| * (dec) | (mA) | (mA) |
| * 0 | 0.8 | 2 |
| * 1 | 1.55 | 4 |
| * 2 | 2.35 | 6 |
| * 3 | 3.1 | 8 |
| * 4 | 3.9 | 10 |
| * 5 | 4.65 | 12 |
| * 6 | 5.4 | 14 |
| * 7 | 6.15 | 16 |
| * |
| * POR value for UFS_RESET HDRV is 3 which means |
| * 3.1mA and we want to use that. Hence just |
| * specify 8mA to "drive-strength" binding and |
| * that should result into writing 3 to HDRV |
| * field. |
| */ |
| drive-strength = <8>; /* default: 3.1 mA */ |
| output-low; /* active low reset */ |
| }; |
| }; |
| |
| ufs_dev_reset_deassert: ufs_dev_reset_deassert { |
| config { |
| pins = "ufs_reset"; |
| bias-pull-down; /* default: pull down */ |
| /* |
| * default: 3.1 mA |
| * check comments under ufs_dev_reset_assert |
| */ |
| drive-strength = <8>; |
| output-high; /* active low reset */ |
| }; |
| }; |
| |
| ap2mdm { |
| ap2mdm_active: ap2mdm_active { |
| mux { |
| /* ap2mdm-status |
| * ap2mdm-errfatal |
| * ap2mdm-vddmin |
| */ |
| pins = "gpio56", "gpio57"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio56", "gpio57"; |
| drive-strength = <16>; |
| bias-disable; |
| }; |
| }; |
| |
| ap2mdm_sleep: ap2mdm_sleep { |
| mux { |
| /* ap2mdm-status |
| * ap2mdm-errfatal |
| * ap2mdm-vddmin |
| */ |
| pins = "gpio56", "gpio57"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio56", "gpio57"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| |
| }; |
| }; |
| |
| mdm2ap { |
| mdm2ap_active: mdm2ap_active { |
| mux { |
| /* mdm2ap-status |
| * mdm2ap-errfatal |
| * mdm2ap-vddmin |
| */ |
| pins = "gpio1", "gpio3"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio1", "gpio3"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| }; |
| |
| mdm2ap_sleep: mdm2ap_sleep { |
| mux { |
| /* mdm2ap-status |
| * mdm2ap-errfatal |
| * mdm2ap-vddmin |
| */ |
| pins = "gpio1", "gpio3"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio1", "gpio3"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| }; |
| }; |
| |
| ap2mdm_pon_reset { |
| ap2mdm_pon_reset_default: ap2mdm_pon_reset_default { |
| mux { |
| /* MDM PON conrol*/ |
| pins = "gpio145"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio145"; |
| drive-strength = <16>; |
| bias-disable; |
| }; |
| }; |
| }; |
| |
| pcie2 { |
| pcie2_perst_default: pcie2_perst_default { |
| mux { |
| pins = "gpio85"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio85"; |
| drive-strength = <2>; |
| bias-pull-down; |
| }; |
| }; |
| |
| pcie2_clkreq_default: pcie2_clkreq_default { |
| mux { |
| pins = "gpio86"; |
| function = "pci_e1"; |
| }; |
| |
| config { |
| pins = "gpio86"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| }; |
| |
| pcie2_wake_default: pcie2_wake_default { |
| mux { |
| pins = "gpio87"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio87"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| }; |
| }; |
| |
| wsa_swr_clk_pin { |
| wsa_swr_clk_sleep: wsa_swr_clk_sleep { |
| mux { |
| pins = "gpio156"; |
| function = "WSA_CLK"; |
| }; |
| |
| config { |
| pins = "gpio156"; |
| drive-strength = <2>; |
| bias-bus-hold; |
| }; |
| }; |
| |
| wsa_swr_clk_active: wsa_swr_clk_active { |
| mux { |
| pins = "gpio156"; |
| function = "WSA_CLK"; |
| }; |
| |
| config { |
| pins = "gpio156"; |
| drive-strength = <2>; |
| bias-bus-hold; |
| }; |
| }; |
| }; |
| |
| wsa_swr_data_pin { |
| wsa_swr_data_sleep: wsa_swr_data_sleep { |
| mux { |
| pins = "gpio157"; |
| function = "WSA_DATA"; |
| }; |
| |
| config { |
| pins = "gpio157"; |
| drive-strength = <4>; |
| bias-bus-hold; |
| }; |
| }; |
| |
| wsa_swr_data_active: wsa_swr_data_active { |
| mux { |
| pins = "gpio157"; |
| function = "WSA_DATA"; |
| }; |
| |
| config { |
| pins = "gpio157"; |
| drive-strength = <4>; |
| bias-bus-hold; |
| }; |
| }; |
| }; |
| |
| pri_aux_pcm_clk { |
| pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep { |
| mux { |
| pins = "gpio138"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio138"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| pri_aux_pcm_clk_active: pri_aux_pcm_clk_active { |
| mux { |
| pins = "gpio138"; |
| function = "mi2s0_sck"; |
| }; |
| |
| config { |
| pins = "gpio138"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| output-high; |
| }; |
| }; |
| }; |
| |
| pri_aux_pcm_sync { |
| pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep { |
| mux { |
| pins = "gpio141"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio141"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| pri_aux_pcm_sync_active: pri_aux_pcm_sync_active { |
| mux { |
| pins = "gpio141"; |
| function = "mi2s0_ws"; |
| }; |
| |
| config { |
| pins = "gpio141"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| output-high; |
| }; |
| }; |
| }; |
| |
| pri_aux_pcm_din { |
| pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep { |
| mux { |
| pins = "gpio139"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio139"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| pri_aux_pcm_din_active: pri_aux_pcm_din_active { |
| mux { |
| pins = "gpio139"; |
| function = "mi2s0_data0"; |
| }; |
| |
| config { |
| pins = "gpio139"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| pri_aux_pcm_dout { |
| pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep { |
| mux { |
| pins = "gpio140"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio140"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| pri_aux_pcm_dout_active: pri_aux_pcm_dout_active { |
| mux { |
| pins = "gpio140"; |
| function = "mi2s0_data1"; |
| }; |
| |
| config { |
| pins = "gpio140"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| sec_aux_pcm { |
| sec_aux_pcm_clk_sleep: sec_aux_pcm_clk_sleep { |
| mux { |
| pins = "gpio142"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio142"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| sec_aux_pcm_clk_active: sec_aux_pcm_clk_active { |
| mux { |
| pins = "gpio142"; |
| function = "mi2s1_sck"; |
| }; |
| |
| config { |
| pins = "gpio142"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| |
| sec_aux_pcm_ws_sleep: sec_aux_pcm_ws_sleep { |
| mux { |
| pins = "gpio145"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio145"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| sec_aux_pcm_ws_active: sec_aux_pcm_ws_active { |
| mux { |
| pins = "gpio145"; |
| function = "mi2s1_ws"; |
| }; |
| |
| config { |
| pins = "gpio145"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| sec_aux_pcm_din { |
| sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep { |
| mux { |
| pins = "gpio143"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio143"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| sec_aux_pcm_din_active: sec_aux_pcm_din_active { |
| mux { |
| pins = "gpio143"; |
| function = "mi2s1_data0"; |
| }; |
| |
| config { |
| pins = "gpio143"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| sec_aux_pcm_dout { |
| sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep { |
| mux { |
| pins = "gpio144"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio144"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| sec_aux_pcm_dout_active: sec_aux_pcm_dout_active { |
| mux { |
| pins = "gpio144"; |
| function = "mi2s1_data1"; |
| }; |
| |
| config { |
| pins = "gpio144"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| tert_aux_pcm { |
| tert_aux_pcm_clk_sleep: tert_aux_pcm_clk_sleep { |
| mux { |
| pins = "gpio133"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio133"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| tert_aux_pcm_clk_active: tert_aux_pcm_clk_active { |
| mux { |
| pins = "gpio133"; |
| function = "mi2s2_sck"; |
| }; |
| |
| config { |
| pins = "gpio133"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| output-high; |
| }; |
| }; |
| |
| tert_aux_pcm_ws_sleep: tert_aux_pcm_ws_sleep { |
| mux { |
| pins = "gpio135"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio135"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| tert_aux_pcm_ws_active: tert_aux_pcm_ws_active { |
| mux { |
| pins = "gpio135"; |
| function = "mi2s2_ws"; |
| }; |
| |
| config { |
| pins = "gpio135"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| output-high; |
| }; |
| }; |
| }; |
| |
| tert_aux_pcm_din { |
| tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep { |
| mux { |
| pins = "gpio134"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio134"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| tert_aux_pcm_din_active: tert_aux_pcm_din_active { |
| mux { |
| pins = "gpio134"; |
| function = "mi2s2_data0"; |
| }; |
| |
| config { |
| pins = "gpio134"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| tert_aux_pcm_dout { |
| tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep { |
| mux { |
| pins = "gpio137"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio137"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| tert_aux_pcm_dout_active: tert_aux_pcm_dout_active { |
| mux { |
| pins = "gpio137"; |
| function = "mi2s2_data1"; |
| }; |
| |
| config { |
| pins = "gpio137"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| pri_tdm_clk { |
| pri_tdm_clk_sleep: pri_tdm_clk_sleep { |
| mux { |
| pins = "gpio138"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio138"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| pri_tdm_clk_active: pri_tdm_clk_active { |
| mux { |
| pins = "gpio138"; |
| function = "mi2s0_sck"; |
| }; |
| |
| config { |
| pins = "gpio138"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| output-high; |
| }; |
| }; |
| }; |
| |
| pri_tdm_sync { |
| pri_tdm_sync_sleep: pri_tdm_sync_sleep { |
| mux { |
| pins = "gpio141"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio141"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| pri_tdm_sync_active: pri_tdm_sync_active { |
| mux { |
| pins = "gpio141"; |
| function = "mi2s0_ws"; |
| }; |
| |
| config { |
| pins = "gpio141"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| output-high; |
| }; |
| }; |
| }; |
| |
| pri_tdm_din { |
| pri_tdm_din_sleep: pri_tdm_din_sleep { |
| mux { |
| pins = "gpio139"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio139"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| pri_tdm_din_active: pri_tdm_din_active { |
| mux { |
| pins = "gpio139"; |
| function = "mi2s0_data0"; |
| }; |
| |
| config { |
| pins = "gpio139"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| pri_tdm_dout { |
| pri_tdm_dout_sleep: pri_tdm_dout_sleep { |
| mux { |
| pins = "gpio140"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio140"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| pri_tdm_dout_active: pri_tdm_dout_active { |
| mux { |
| pins = "gpio140"; |
| function = "mi2s0_data1"; |
| }; |
| |
| config { |
| pins = "gpio140"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| sec_tdm { |
| sec_tdm_sck_sleep: sec_tdm_sck_sleep { |
| mux { |
| pins = "gpio142"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio142"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| sec_tdm_sck_active: sec_tdm_sck_active { |
| mux { |
| pins = "gpio142"; |
| function = "mi2s1_sck"; |
| }; |
| |
| config { |
| pins = "gpio142"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| |
| sec_tdm_ws_sleep: sec_tdm_ws_sleep { |
| mux { |
| pins = "gpio145"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio145"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| sec_tdm_ws_active: sec_tdm_ws_active { |
| mux { |
| pins = "gpio145"; |
| function = "mi2s1_ws"; |
| }; |
| |
| config { |
| pins = "gpio145"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| sec_tdm_din { |
| sec_tdm_din_sleep: sec_tdm_din_sleep { |
| mux { |
| pins = "gpio143"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio143"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| sec_tdm_din_active: sec_tdm_din_active { |
| mux { |
| pins = "gpio143"; |
| function = "mi2s1_data0"; |
| }; |
| |
| config { |
| pins = "gpio143"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| sec_tdm_dout { |
| sec_tdm_dout_sleep: sec_tdm_dout_sleep { |
| mux { |
| pins = "gpio144"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio144"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| sec_tdm_dout_active: sec_tdm_dout_active { |
| mux { |
| pins = "gpio144"; |
| function = "mi2s1_data1"; |
| }; |
| |
| config { |
| pins = "gpio144"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| tert_tdm { |
| tert_tdm_clk_sleep: tert_tdm_clk_sleep { |
| mux { |
| pins = "gpio133"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio133"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| tert_tdm_clk_active: tert_tdm_clk_active { |
| mux { |
| pins = "gpio133"; |
| function = "mi2s2_sck"; |
| }; |
| |
| config { |
| pins = "gpio133"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| output-high; |
| }; |
| }; |
| |
| tert_tdm_ws_sleep: tert_tdm_ws_sleep { |
| mux { |
| pins = "gpio135"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio135"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| tert_tdm_ws_active: tert_tdm_ws_active { |
| mux { |
| pins = "gpio135"; |
| function = "mi2s2_ws"; |
| }; |
| |
| config { |
| pins = "gpio135"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| output-high; |
| }; |
| }; |
| }; |
| |
| tert_tdm_din { |
| tert_tdm_din_sleep: tert_tdm_din_sleep { |
| mux { |
| pins = "gpio134"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio134"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| tert_tdm_din_active: tert_tdm_din_active { |
| mux { |
| pins = "gpio134"; |
| function = "mi2s2_data0"; |
| }; |
| |
| config { |
| pins = "gpio134"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| tert_tdm_dout { |
| tert_tdm_dout_sleep: tert_tdm_dout_sleep { |
| mux { |
| pins = "gpio137"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio137"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| tert_tdm_dout_active: tert_tdm_dout_active { |
| mux { |
| pins = "gpio137"; |
| function = "mi2s2_data1"; |
| }; |
| |
| config { |
| pins = "gpio137"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| pri_mi2s_mclk { |
| pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep { |
| mux { |
| pins = "gpio136"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio136"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| pri_mi2s_mclk_active: pri_mi2s_mclk_active { |
| mux { |
| pins = "gpio136"; |
| function = "pri_mi2s"; |
| }; |
| |
| config { |
| pins = "gpio136"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| output-high; |
| }; |
| }; |
| }; |
| |
| pri_mi2s_sck { |
| pri_mi2s_sck_sleep: pri_mi2s_sck_sleep { |
| mux { |
| pins = "gpio138"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio138"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| pri_mi2s_sck_active: pri_mi2s_sck_active { |
| mux { |
| pins = "gpio138"; |
| function = "mi2s0_sck"; |
| }; |
| |
| config { |
| pins = "gpio138"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| output-high; |
| }; |
| }; |
| }; |
| |
| pri_mi2s_ws { |
| pri_mi2s_ws_sleep: pri_mi2s_ws_sleep { |
| mux { |
| pins = "gpio141"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio141"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| pri_mi2s_ws_active: pri_mi2s_ws_active { |
| mux { |
| pins = "gpio141"; |
| function = "mi2s0_ws"; |
| }; |
| |
| config { |
| pins = "gpio141"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| output-high; |
| }; |
| }; |
| }; |
| |
| pri_mi2s_sd0 { |
| pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep { |
| mux { |
| pins = "gpio139"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio139"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| pri_mi2s_sd0_active: pri_mi2s_sd0_active { |
| mux { |
| pins = "gpio139"; |
| function = "mi2s0_data0"; |
| }; |
| |
| config { |
| pins = "gpio139"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| output-high; |
| }; |
| }; |
| }; |
| |
| pri_mi2s_sd1 { |
| pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep { |
| mux { |
| pins = "gpio140"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio140"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| pri_mi2s_sd1_active: pri_mi2s_sd1_active { |
| mux { |
| pins = "gpio140"; |
| function = "mi2s0_data1"; |
| }; |
| |
| config { |
| pins = "gpio140"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| output-high; |
| }; |
| }; |
| }; |
| |
| sec_mi2s_mclk { |
| sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep { |
| mux { |
| pins = "gpio137"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio137"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| sec_mi2s_mclk_active: sec_mi2s_mclk_active { |
| mux { |
| pins = "gpio137"; |
| function = "sec_mi2s"; |
| }; |
| |
| config { |
| pins = "gpio137"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| output-high; |
| }; |
| }; |
| }; |
| |
| sec_mi2s_sck { |
| sec_mi2s_sck_sleep: sec_mi2s_sck_sleep { |
| mux { |
| pins = "gpio142"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio142"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| sec_mi2s_sck_active: sec_mi2s_sck_active { |
| mux { |
| pins = "gpio142"; |
| function = "mi2s1_sck"; |
| }; |
| |
| config { |
| pins = "gpio142"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| sec_mi2s_ws { |
| sec_mi2s_ws_sleep: sec_mi2s_ws_sleep { |
| mux { |
| pins = "gpio145"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio145"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| sec_mi2s_ws_active: sec_mi2s_ws_active { |
| mux { |
| pins = "gpio145"; |
| function = "mi2s1_ws"; |
| }; |
| |
| config { |
| pins = "gpio145"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| sec_mi2s_sd0 { |
| sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep { |
| mux { |
| pins = "gpio143"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio143"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| sec_mi2s_sd0_active: sec_mi2s_sd0_active { |
| mux { |
| pins = "gpio143"; |
| function = "mi2s1_data0"; |
| }; |
| |
| config { |
| pins = "gpio143"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| sec_mi2s_sd1 { |
| sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep { |
| mux { |
| pins = "gpio144"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio144"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| sec_mi2s_sd1_active: sec_mi2s_sd1_active { |
| mux { |
| pins = "gpio144"; |
| function = "mi2s1_data1"; |
| }; |
| |
| config { |
| pins = "gpio144"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| tert_mi2s_sck { |
| tert_mi2s_sck_sleep: tert_mi2s_sck_sleep { |
| mux { |
| pins = "gpio133"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio133"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| tert_mi2s_sck_active: tert_mi2s_sck_active { |
| mux { |
| pins = "gpio133"; |
| function = "mi2s2_sck"; |
| }; |
| |
| config { |
| pins = "gpio133"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| tert_mi2s_ws { |
| tert_mi2s_ws_sleep: tert_mi2s_ws_sleep { |
| mux { |
| pins = "gpio135"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio135"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| tert_mi2s_ws_active: tert_mi2s_ws_active { |
| mux { |
| pins = "gpio135"; |
| function = "mi2s2_ws"; |
| }; |
| |
| config { |
| pins = "gpio135"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| tert_mi2s_sd0 { |
| tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep { |
| mux { |
| pins = "gpio134"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio134"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| tert_mi2s_sd0_active: tert_mi2s_sd0_active { |
| mux { |
| pins = "gpio134"; |
| function = "mi2s2_data0"; |
| }; |
| |
| config { |
| pins = "gpio134"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| tert_mi2s_sd1 { |
| tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep { |
| mux { |
| pins = "gpio137"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio137"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; /* PULL DOWN */ |
| input-enable; |
| }; |
| }; |
| |
| tert_mi2s_sd1_active: tert_mi2s_sd1_active { |
| mux { |
| pins = "gpio137"; |
| function = "mi2s2_data1"; |
| }; |
| |
| config { |
| pins = "gpio137"; |
| drive-strength = <8>; /* 8 mA */ |
| bias-disable; /* NO PULL */ |
| }; |
| }; |
| }; |
| |
| /* WSA speaker reset pins */ |
| spkr_1_sd_n { |
| spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { |
| mux { |
| pins = "gpio26"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio26"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; |
| input-enable; |
| }; |
| }; |
| |
| spkr_1_sd_n_active: spkr_1_sd_n_active { |
| mux { |
| pins = "gpio26"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio26"; |
| drive-strength = <16>; /* 16 mA */ |
| bias-disable; |
| output-high; |
| }; |
| }; |
| }; |
| |
| spkr_2_sd_n { |
| spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { |
| mux { |
| pins = "gpio127"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio127"; |
| drive-strength = <2>; /* 2 mA */ |
| bias-pull-down; |
| input-enable; |
| }; |
| }; |
| |
| spkr_2_sd_n_active: spkr_2_sd_n_active { |
| mux { |
| pins = "gpio127"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio127"; |
| drive-strength = <16>; /* 16 mA */ |
| bias-disable; |
| output-high; |
| }; |
| }; |
| }; |
| |
| wcd938x_reset_active: wcd938x_reset_active { |
| mux { |
| pins = "gpio32"; |
| function = "func2"; |
| }; |
| |
| config { |
| pins = "gpio32"; |
| drive-strength = <16>; |
| output-high; |
| }; |
| }; |
| |
| wcd938x_reset_sleep: wcd938x_reset_sleep { |
| mux { |
| pins = "gpio32"; |
| function = "func2"; |
| }; |
| |
| config { |
| pins = "gpio32"; |
| drive-strength = <16>; |
| bias-disable; |
| output-low; |
| }; |
| }; |
| |
| cdc_dmic01_clk_active: dmic01_clk_active { |
| mux { |
| pins = "gpio152"; |
| function = "func1"; |
| }; |
| |
| config { |
| pins = "gpio152"; |
| drive-strength = <8>; |
| output-high; |
| }; |
| }; |
| |
| cdc_dmic01_clk_sleep: dmic01_clk_sleep { |
| mux { |
| pins = "gpio152"; |
| function = "func1"; |
| }; |
| |
| config { |
| pins = "gpio152"; |
| drive-strength = <2>; |
| bias-disable; |
| output-low; |
| }; |
| }; |
| |
| cdc_dmic01_data_active: dmic01_data_active { |
| mux { |
| pins = "gpio153"; |
| function = "func1"; |
| }; |
| |
| config { |
| pins = "gpio153"; |
| drive-strength = <8>; |
| input-enable; |
| }; |
| }; |
| |
| cdc_dmic01_data_sleep: dmic01_data_sleep { |
| mux { |
| pins = "gpio153"; |
| function = "func1"; |
| }; |
| |
| config { |
| pins = "gpio27"; |
| drive-strength = <2>; |
| pull-down; |
| input-enable; |
| }; |
| }; |
| |
| cdc_dmic23_clk_active: dmic23_clk_active { |
| mux { |
| pins = "gpio154"; |
| function = "func1"; |
| }; |
| |
| config { |
| pins = "gpio154"; |
| drive-strength = <8>; |
| output-high; |
| }; |
| }; |
| |
| cdc_dmic23_clk_sleep: dmic23_clk_sleep { |
| mux { |
| pins = "gpio154"; |
| function = "func1"; |
| }; |
| |
| config { |
| pins = "gpio154"; |
| drive-strength = <2>; |
| bias-disable; |
| output-low; |
| }; |
| }; |
| |
| cdc_dmic23_data_active: dmic23_data_active { |
| mux { |
| pins = "gpio155"; |
| function = "func1"; |
| }; |
| |
| config { |
| pins = "gpio155"; |
| drive-strength = <8>; |
| input-enable; |
| }; |
| }; |
| |
| cdc_dmic23_data_sleep: dmic23_data_sleep { |
| mux { |
| pins = "gpio155"; |
| function = "func1"; |
| }; |
| |
| config { |
| pins = "gpio155"; |
| drive-strength = <2>; |
| pull-down; |
| input-enable; |
| }; |
| }; |
| |
| tx_swr_clk_sleep: tx_swr_clk_sleep { |
| mux { |
| pins = "gpio146"; |
| function = "func2"; |
| }; |
| |
| config { |
| pins = "gpio146"; |
| drive-strength = <2>; |
| bias-bus-hold; |
| }; |
| }; |
| |
| tx_swr_clk_active: tx_swr_clk_active { |
| mux { |
| pins = "gpio146"; |
| function = "func2"; |
| }; |
| |
| config { |
| pins = "gpio146"; |
| drive-strength = <8>; |
| bias-bus-hold; |
| }; |
| }; |
| |
| tx_swr_data1_sleep: tx_swr_data1_sleep { |
| mux { |
| pins = "gpio147"; |
| function = "func3"; |
| }; |
| |
| config { |
| pins = "gpio147"; |
| drive-strength = <2>; |
| bias-bus-hold; |
| }; |
| }; |
| |
| tx_swr_data1_active: tx_swr_data1_active { |
| mux { |
| pins = "gpio147"; |
| function = "func3"; |
| }; |
| |
| config { |
| pins = "gpio147"; |
| drive-strength = <8>; |
| bias-bus-hold; |
| }; |
| }; |
| |
| tx_swr_data2_sleep: tx_swr_data2_sleep { |
| mux { |
| pins = "gpio148"; |
| function = "func2"; |
| }; |
| |
| config { |
| pins = "gpio148"; |
| drive-strength = <2>; |
| bias-bus-hold; |
| }; |
| }; |
| |
| tx_swr_data2_active: tx_swr_data2_active { |
| mux { |
| pins = "gpio148"; |
| function = "func2"; |
| }; |
| |
| config { |
| pins = "gpio148"; |
| drive-strength = <8>; |
| bias-bus-hold; |
| }; |
| }; |
| |
| rx_swr_clk_sleep: rx_swr_clk_sleep { |
| mux { |
| pins = "gpio149"; |
| function = "func2"; |
| }; |
| |
| config { |
| pins = "gpio149"; |
| drive-strength = <2>; |
| bias-bus-hold; |
| }; |
| }; |
| |
| rx_swr_clk_active: rx_swr_clk_active { |
| mux { |
| pins = "gpio149"; |
| function = "func2"; |
| }; |
| |
| config { |
| pins = "gpio149"; |
| drive-strength = <8>; |
| bias-bus-hold; |
| }; |
| }; |
| |
| rx_swr_data_sleep: rx_swr_data_sleep { |
| mux { |
| pins = "gpio150", "gpio151"; |
| function = "func2"; |
| }; |
| |
| config { |
| pins = "gpio150", "gpio151"; |
| drive-strength = <2>; |
| bias-bus-hold; |
| }; |
| }; |
| |
| rx_swr_data_active: rx_swr_data_active { |
| mux { |
| pins = "gpio150", "gpio151"; |
| function = "func2"; |
| }; |
| |
| config { |
| pins = "gpio150", "gpio151"; |
| drive-strength = <8>; |
| bias-bus-hold; |
| }; |
| }; |
| |
| cam_sensor_mclk0_active: cam_sensor_mclk0_active { |
| /* MCLK0 */ |
| mux { |
| pins = "gpio94"; |
| function = "cam_mclk"; |
| }; |
| |
| config { |
| pins = "gpio94"; |
| bias-disable; /* No PULL */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { |
| /* MCLK0 */ |
| mux { |
| pins = "gpio94"; |
| function = "cam_mclk"; |
| }; |
| |
| config { |
| pins = "gpio94"; |
| bias-pull-down; /* PULL DOWN */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cam_sensor_mclk1_active: cam_sensor_mclk1_active { |
| /* MCLK1 */ |
| mux { |
| pins = "gpio95"; |
| function = "cam_mclk"; |
| }; |
| |
| config { |
| pins = "gpio95"; |
| bias-disable; /* No PULL */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { |
| /* MCLK1 */ |
| mux { |
| pins = "gpio95"; |
| function = "cam_mclk"; |
| }; |
| |
| config { |
| pins = "gpio95"; |
| bias-pull-down; /* PULL DOWN */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cam_sensor_mclk2_active: cam_sensor_mclk2_active { |
| /* MCLK2 */ |
| mux { |
| pins = "gpio96"; |
| function = "cam_mclk"; |
| }; |
| |
| config { |
| pins = "gpio96"; |
| bias-disable; /* No PULL */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { |
| /* MCLK2 */ |
| mux { |
| pins = "gpio96"; |
| function = "cam_mclk"; |
| }; |
| |
| config { |
| pins = "gpio96"; |
| bias-pull-down; /* PULL DOWN */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cam_sensor_mclk3_active: cam_sensor_mclk3_active { |
| /* MCLK3 */ |
| mux { |
| pins = "gpio97"; |
| function = "cam_mclk"; |
| }; |
| |
| config { |
| pins = "gpio97"; |
| bias-disable; /* No PULL */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { |
| /* MCLK3 */ |
| mux { |
| pins = "gpio97"; |
| function = "cam_mclk"; |
| }; |
| |
| config { |
| pins = "gpio97"; |
| bias-pull-down; /* PULL DOWN */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cam_sensor_active_rear: cam_sensor_active_rear { |
| /* RESET REAR */ |
| mux { |
| pins = "gpio93"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio93"; |
| bias-disable; /* No PULL */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cam_sensor_suspend_rear: cam_sensor_suspend_rear { |
| /* RESET REAR */ |
| mux { |
| pins = "gpio93"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio93"; |
| bias-pull-down; /* PULL DOWN */ |
| drive-strength = <2>; /* 2 MA */ |
| output-low; |
| }; |
| }; |
| |
| cam_sensor_active_rear_aux: cam_sensor_active_rear_aux { |
| /* RESET REARAUX */ |
| mux { |
| pins = "gpio92"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio92"; |
| bias-disable; /* No PULL */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cam_sensor_suspend_rear_aux: cam_sensor_suspend_rear_aux { |
| /* RESET REARAUX */ |
| mux { |
| pins = "gpio92"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio92"; |
| bias-pull-down; /* PULL DOWN */ |
| drive-strength = <2>; /* 2 MA */ |
| output-low; |
| }; |
| }; |
| |
| cam_sensor_active_front: cam_sensor_active_front { |
| /* RESET FRONT */ |
| mux { |
| pins = "gpio78"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio78"; |
| bias-disable; /* No PULL */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cam_sensor_suspend_front: cam_sensor_suspend_front { |
| /* RESET FRONT */ |
| mux { |
| pins = "gpio78"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio78"; |
| bias-pull-down; /* PULL DOWN */ |
| drive-strength = <2>; /* 2 MA */ |
| output-low; |
| }; |
| }; |
| |
| cci0_active: cci0_active { |
| mux { |
| /* CLK, DATA */ |
| pins = "gpio101","gpio102"; // Only 2 |
| function = "cci_i2c"; |
| }; |
| |
| config { |
| pins = "gpio101","gpio102"; |
| bias-pull-up; /* PULL UP*/ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cci0_suspend: cci0_suspend { |
| mux { |
| /* CLK, DATA */ |
| pins = "gpio101","gpio102"; |
| function = "cci_i2c"; |
| }; |
| |
| config { |
| pins = "gpio101","gpio102"; |
| bias-pull-down; /* PULL DOWN */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cci1_active: cci1_active { |
| mux { |
| /* CLK, DATA */ |
| pins = "gpio103","gpio104"; |
| function = "cci_i2c"; |
| }; |
| |
| config { |
| pins = "gpio103","gpio104"; |
| bias-pull-up; /* PULL UP*/ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cci1_suspend: cci1_suspend { |
| mux { |
| /* CLK, DATA */ |
| pins = "gpio103","gpio104"; |
| function = "cci_i2c"; |
| }; |
| |
| config { |
| pins = "gpio103","gpio104"; |
| bias-pull-down; /* PULL DOWN */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cci2_active: cci2_active { |
| mux { |
| /* CLK, DATA */ |
| pins = "gpio105","gpio106"; |
| function = "cci_i2c"; |
| }; |
| |
| config { |
| pins = "gpio105","gpio106"; |
| bias-pull-up; /* PULL UP*/ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cci2_suspend: cci2_suspend { |
| mux { |
| /* CLK, DATA */ |
| pins = "gpio105","gpio106"; |
| function = "cci_i2c"; |
| }; |
| |
| config { |
| pins = "gpio105","gpio106"; |
| bias-pull-down; /* PULL DOWN */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cci3_active: cci3_active { |
| mux { |
| /* CLK, DATA */ |
| pins = "gpio107","gpio108"; |
| function = "cci_i2c"; |
| }; |
| |
| config { |
| pins = "gpio107","gpio108"; |
| bias-pull-up; /* PULL UP*/ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cci3_suspend: cci3_suspend { |
| mux { |
| /* CLK, DATA */ |
| pins = "gpio107","gpio108"; |
| function = "cci_i2c"; |
| }; |
| |
| config { |
| pins = "gpio107","gpio108"; |
| bias-pull-down; /* PULL DOWN */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| }; |
| }; |