arch/arm64/boot/dts/qcom/kona-qupv3.dtsi

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 */

#include <dt-bindings/msm/msm-bus-ids.h>

&soc {
	/* QUPv3_0  wrapper  instance : North QUP*/
	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x9c0000 0x2000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_0>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,iommu-s1-bypass;
		iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb {
			compatible = "qcom,qupv3-geni-se-cb";
			iommus = <&apps_smmu 0x5a3 0x0>;
			qcom,iommu-dma = "disabled";
		};
	};

	/* Debug UART Instance for RUMI platform */
	qupv3_se2_2uart: qcom,qup_uart@988000 {
		compatible = "qcom,msm-geni-console";
		reg = <0x988000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se2_2uart_active>;
		pinctrl-1 = <&qupv3_se2_2uart_sleep>;
		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
		qcom,wrapper-core = <&qupv3_0>;
		qcom,change-sampling-rate;
		status = "disabled";
	};

	/*
	 * HS UART instances. HS UART usecases can be supported on these
	 * instances only.
	 */
	qupv3_se6_4uart: qcom,qup_uart@998000 {
		compatible = "qcom,msm-geni-serial-hs";
		reg = <0x998000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
							<&qupv3_se6_tx> ;
		pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
							<&qupv3_se6_tx> ;
		interrupts-extended = <&pdc GIC_SPI 607 0>,
				<&tlmm 19 0>;
		status = "disabled";
		qcom,wakeup-byte = <0xFD>;
		qcom,wrapper-core = <&qupv3_0>;
	};

	/* QUPv3_1  wrapper  instance : South_1 QUP */
	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0xac0000 0x2000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_1>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,iommu-s1-bypass;
		iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb {
			compatible = "qcom,qupv3-geni-se-cb";
			iommus = <&apps_smmu 0x43 0x0>;
			qcom,iommu-dma = "disabled";
		};
	};

	/* Debug UART Instance for CDP/MTP platform */
	qupv3_se12_2uart: qcom,qup_uart@a90000 {
		compatible = "qcom,msm-geni-console";
		reg = <0xa90000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se12_2uart_active>;
		pinctrl-1 = <&qupv3_se12_2uart_sleep>;
		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
		qcom,wrapper-core = <&qupv3_1>;
		qcom,change-sampling-rate;
		status = "disabled";
	};

	/* QUPv3_2  wrapper  instance : South_2 QUP */
	qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x8c0000 0x2000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_2>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,iommu-s1-bypass;
		iommu_qupv3_2_geni_se_cb: qcom,iommu_qupv3_2_geni_se_cb {
			compatible = "qcom,qupv3-geni-se-cb";
			iommus = <&apps_smmu 0x63 0x0>;
			qcom,iommu-dma = "disabled";
		};
	};

	/*
	 * HS UART : Modem/Audio backup
	 */
	qupv3_se17_4uart: qcom,qup_uart@88c000 {
		compatible = "qcom,msm-geni-serial-hs";
		reg = <0x88c000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
							<&qupv3_se17_tx> ;
		pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
							<&qupv3_se17_tx> ;
		interrupts-extended = <&pdc GIC_SPI 585 0>,
				<&tlmm 55 0>;
		status = "disabled";
		qcom,wakeup-byte = <0xFD>;
		qcom,wrapper-core = <&qupv3_2>;
	};

	/*
	 * HS UART : 2-wire Modem
	 */
	qupv3_se18_2uart: qcom,qup_uart@890000 {
		compatible = "qcom,msm-geni-serial-hs";
		reg = <0x890000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se18_rx>, <&qupv3_se18_tx>;
		pinctrl-1 = <&qupv3_se18_rx>, <&qupv3_se18_tx>;
		interrupts-extended = <&pdc GIC_SPI 586 0>,
						<&tlmm 59 0>;
		status = "disabled";
		qcom,wakeup-byte = <0xFD>;
		qcom,wrapper-core = <&qupv3_2>;
	};
};