| // SPDX-License-Identifier: GPL-2.0-only |
| /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */ |
| |
| #define pr_fmt(fmt) "clk: %s: " fmt, __func__ |
| |
| #include <linux/kernel.h> |
| #include <linux/err.h> |
| #include <linux/platform_device.h> |
| #include <linux/module.h> |
| #include <linux/of.h> |
| #include <linux/of_device.h> |
| #include <linux/clk.h> |
| #include <linux/clk-provider.h> |
| #include <linux/regmap.h> |
| #include <linux/mfd/syscon.h> |
| |
| #include "clk-debug.h" |
| |
| static struct measure_clk_data debug_mux_priv = { |
| .ctl_reg = 0x62038, |
| .status_reg = 0x6203C, |
| .xo_div4_cbcr = 0x4300C, |
| }; |
| |
| static const char *const debug_mux_parent_names[] = { |
| "cam_cc_bps_ahb_clk", |
| "cam_cc_bps_areg_clk", |
| "cam_cc_bps_axi_clk", |
| "cam_cc_bps_clk", |
| "cam_cc_camnoc_axi_clk", |
| "cam_cc_cci_0_clk", |
| "cam_cc_cci_1_clk", |
| "cam_cc_core_ahb_clk", |
| "cam_cc_cpas_ahb_clk", |
| "cam_cc_csi0phytimer_clk", |
| "cam_cc_csi1phytimer_clk", |
| "cam_cc_csi2phytimer_clk", |
| "cam_cc_csi3phytimer_clk", |
| "cam_cc_csi4phytimer_clk", |
| "cam_cc_csi5phytimer_clk", |
| "cam_cc_csiphy0_clk", |
| "cam_cc_csiphy1_clk", |
| "cam_cc_csiphy2_clk", |
| "cam_cc_csiphy3_clk", |
| "cam_cc_csiphy4_clk", |
| "cam_cc_csiphy5_clk", |
| "cam_cc_fd_core_clk", |
| "cam_cc_fd_core_uar_clk", |
| "cam_cc_icp_ahb_clk", |
| "cam_cc_icp_clk", |
| "cam_cc_ife_0_ahb_clk", |
| "cam_cc_ife_0_areg_clk", |
| "cam_cc_ife_0_axi_clk", |
| "cam_cc_ife_0_clk", |
| "cam_cc_ife_0_cphy_rx_clk", |
| "cam_cc_ife_0_csid_clk", |
| "cam_cc_ife_0_dsp_clk", |
| "cam_cc_ife_1_ahb_clk", |
| "cam_cc_ife_1_areg_clk", |
| "cam_cc_ife_1_axi_clk", |
| "cam_cc_ife_1_clk", |
| "cam_cc_ife_1_cphy_rx_clk", |
| "cam_cc_ife_1_csid_clk", |
| "cam_cc_ife_1_dsp_clk", |
| "cam_cc_ife_lite_ahb_clk", |
| "cam_cc_ife_lite_axi_clk", |
| "cam_cc_ife_lite_clk", |
| "cam_cc_ife_lite_cphy_rx_clk", |
| "cam_cc_ife_lite_csid_clk", |
| "cam_cc_ipe_0_ahb_clk", |
| "cam_cc_ipe_0_areg_clk", |
| "cam_cc_ipe_0_axi_clk", |
| "cam_cc_ipe_0_clk", |
| "cam_cc_jpeg_clk", |
| "cam_cc_mclk0_clk", |
| "cam_cc_mclk1_clk", |
| "cam_cc_mclk2_clk", |
| "cam_cc_mclk3_clk", |
| "cam_cc_mclk4_clk", |
| "cam_cc_mclk5_clk", |
| "cam_cc_mclk6_clk", |
| "cam_cc_sbi_ahb_clk", |
| "cam_cc_sbi_axi_clk", |
| "cam_cc_sbi_clk", |
| "cam_cc_sbi_cphy_rx_clk", |
| "cam_cc_sbi_csid_clk", |
| "cam_cc_sbi_ife_0_clk", |
| "cam_cc_sbi_ife_1_clk", |
| "disp_cc_mdss_ahb_clk", |
| "disp_cc_mdss_byte0_clk", |
| "disp_cc_mdss_byte0_intf_clk", |
| "disp_cc_mdss_byte1_clk", |
| "disp_cc_mdss_byte1_intf_clk", |
| "disp_cc_mdss_dp_aux1_clk", |
| "disp_cc_mdss_dp_aux_clk", |
| "disp_cc_mdss_dp_link1_clk", |
| "disp_cc_mdss_dp_link1_intf_clk", |
| "disp_cc_mdss_dp_link_clk", |
| "disp_cc_mdss_dp_link_intf_clk", |
| "disp_cc_mdss_dp_pixel1_clk", |
| "disp_cc_mdss_dp_pixel2_clk", |
| "disp_cc_mdss_dp_pixel_clk", |
| "disp_cc_mdss_edp_aux_clk", |
| "disp_cc_mdss_edp_gtc_clk", |
| "disp_cc_mdss_edp_link_clk", |
| "disp_cc_mdss_edp_link_intf_clk", |
| "disp_cc_mdss_edp_pixel_clk", |
| "disp_cc_mdss_esc0_clk", |
| "disp_cc_mdss_esc1_clk", |
| "disp_cc_mdss_mdp_clk", |
| "disp_cc_mdss_mdp_lut_clk", |
| "disp_cc_mdss_non_gdsc_ahb_clk", |
| "disp_cc_mdss_pclk0_clk", |
| "disp_cc_mdss_pclk1_clk", |
| "disp_cc_mdss_rot_clk", |
| "disp_cc_mdss_rscc_ahb_clk", |
| "disp_cc_mdss_rscc_vsync_clk", |
| "disp_cc_mdss_vsync_clk", |
| "gcc_aggre_noc_pcie_tbu_clk", |
| "gcc_aggre_ufs_card_axi_clk", |
| "gcc_aggre_ufs_phy_axi_clk", |
| "gcc_aggre_usb3_prim_axi_clk", |
| "gcc_aggre_usb3_sec_axi_clk", |
| "gcc_camera_ahb_clk", |
| "gcc_camera_hf_axi_clk", |
| "gcc_camera_sf_axi_clk", |
| "gcc_cfg_noc_usb3_prim_axi_clk", |
| "gcc_cfg_noc_usb3_sec_axi_clk", |
| "gcc_cpuss_rbcpr_clk", |
| "gcc_ddrss_gpu_axi_clk", |
| "gcc_ddrss_pcie_sf_tbu_clk", |
| "gcc_disp_ahb_clk", |
| "gcc_disp_hf_axi_clk", |
| "gcc_disp_sf_axi_clk", |
| "gcc_dpm_clk", |
| "gcc_gp1_clk", |
| "gcc_gp2_clk", |
| "gcc_gp3_clk", |
| "gcc_gpu_cfg_ahb_clk", |
| "gcc_gpu_gpll0_clk_src", |
| "gcc_gpu_gpll0_div_clk_src", |
| "gcc_gpu_memnoc_gfx_clk", |
| "gcc_gpu_snoc_dvm_gfx_clk", |
| "gcc_npu_axi_clk", |
| "gcc_npu_bwmon_axi_clk", |
| "gcc_npu_bwmon_cfg_ahb_clk", |
| "gcc_npu_cfg_ahb_clk", |
| "gcc_npu_dma_clk", |
| "gcc_npu_gpll0_clk_src", |
| "gcc_npu_gpll0_div_clk_src", |
| "gcc_pcie0_phy_refgen_clk", |
| "gcc_pcie1_phy_refgen_clk", |
| "gcc_pcie2_phy_refgen_clk", |
| "gcc_pcie_0_aux_clk", |
| "gcc_pcie_0_cfg_ahb_clk", |
| "gcc_pcie_0_mstr_axi_clk", |
| "gcc_pcie_0_pipe_clk", |
| "gcc_pcie_0_slv_axi_clk", |
| "gcc_pcie_0_slv_q2a_axi_clk", |
| "gcc_pcie_1_aux_clk", |
| "gcc_pcie_1_cfg_ahb_clk", |
| "gcc_pcie_1_mstr_axi_clk", |
| "gcc_pcie_1_pipe_clk", |
| "gcc_pcie_1_slv_axi_clk", |
| "gcc_pcie_1_slv_q2a_axi_clk", |
| "gcc_pcie_2_aux_clk", |
| "gcc_pcie_2_cfg_ahb_clk", |
| "gcc_pcie_2_mstr_axi_clk", |
| "gcc_pcie_2_pipe_clk", |
| "gcc_pcie_2_slv_axi_clk", |
| "gcc_pcie_2_slv_q2a_axi_clk", |
| "gcc_pcie_phy_aux_clk", |
| "gcc_pdm2_clk", |
| "gcc_prng_ahb_clk", |
| "gcc_qupv3_wrap0_core_2x_clk", |
| "gcc_qupv3_wrap0_core_clk", |
| "gcc_qupv3_wrap0_s0_clk", |
| "gcc_qupv3_wrap0_s1_clk", |
| "gcc_qupv3_wrap0_s2_clk", |
| "gcc_qupv3_wrap0_s3_clk", |
| "gcc_qupv3_wrap0_s4_clk", |
| "gcc_qupv3_wrap0_s5_clk", |
| "gcc_qupv3_wrap0_s6_clk", |
| "gcc_qupv3_wrap0_s7_clk", |
| "gcc_qupv3_wrap1_core_2x_clk", |
| "gcc_qupv3_wrap1_core_clk", |
| "gcc_qupv3_wrap1_s0_clk", |
| "gcc_qupv3_wrap1_s1_clk", |
| "gcc_qupv3_wrap1_s2_clk", |
| "gcc_qupv3_wrap1_s3_clk", |
| "gcc_qupv3_wrap1_s4_clk", |
| "gcc_qupv3_wrap1_s5_clk", |
| "gcc_qupv3_wrap2_core_2x_clk", |
| "gcc_qupv3_wrap2_core_clk", |
| "gcc_qupv3_wrap2_s0_clk", |
| "gcc_qupv3_wrap2_s1_clk", |
| "gcc_qupv3_wrap2_s2_clk", |
| "gcc_qupv3_wrap2_s3_clk", |
| "gcc_qupv3_wrap2_s4_clk", |
| "gcc_qupv3_wrap2_s5_clk", |
| "gcc_sdcc2_ahb_clk", |
| "gcc_sdcc2_apps_clk", |
| "gcc_sdcc4_ahb_clk", |
| "gcc_sdcc4_apps_clk", |
| "gcc_sys_noc_cpuss_ahb_clk", |
| "gcc_tsif_ref_clk", |
| "gcc_ufs_card_ahb_clk", |
| "gcc_ufs_card_axi_clk", |
| "gcc_ufs_card_ice_core_clk", |
| "gcc_ufs_card_phy_aux_clk", |
| "gcc_ufs_card_rx_symbol_0_clk", |
| "gcc_ufs_card_rx_symbol_1_clk", |
| "gcc_ufs_card_tx_symbol_0_clk", |
| "gcc_ufs_card_unipro_core_clk", |
| "gcc_ufs_phy_ahb_clk", |
| "gcc_ufs_phy_axi_clk", |
| "gcc_ufs_phy_ice_core_clk", |
| "gcc_ufs_phy_phy_aux_clk", |
| "gcc_ufs_phy_rx_symbol_0_clk", |
| "gcc_ufs_phy_rx_symbol_1_clk", |
| "gcc_ufs_phy_tx_symbol_0_clk", |
| "gcc_ufs_phy_unipro_core_clk", |
| "gcc_usb30_prim_master_clk", |
| "gcc_usb30_prim_mock_utmi_clk", |
| "gcc_usb30_sec_master_clk", |
| "gcc_usb30_sec_mock_utmi_clk", |
| "gcc_usb3_prim_phy_aux_clk", |
| "gcc_usb3_prim_phy_com_aux_clk", |
| "gcc_usb3_prim_phy_pipe_clk", |
| "gcc_usb3_sec_phy_aux_clk", |
| "gcc_usb3_sec_phy_com_aux_clk", |
| "gcc_usb3_sec_phy_pipe_clk", |
| "gcc_video_ahb_clk", |
| "gcc_video_axi0_clk", |
| "gcc_video_axi1_clk", |
| "gpu_cc_ahb_clk", |
| "gpu_cc_cx_gmu_clk", |
| "gpu_cc_cx_snoc_dvm_clk", |
| "gpu_cc_gx_gmu_clk", |
| "gpu_cc_gx_vsense_clk", |
| "measure_only_cnoc_clk", |
| "measure_only_gpu_cc_cx_gfx3d_clk", |
| "measure_only_gpu_cc_cx_gfx3d_slv_clk", |
| "measure_only_gpu_cc_gx_gfx3d_clk", |
| "measure_only_ipa_2x_clk", |
| "measure_only_snoc_clk", |
| "npu_cc_bto_core_clk", |
| "npu_cc_bwmon_clk", |
| "npu_cc_cal_hm0_cdc_clk", |
| "npu_cc_cal_hm0_clk", |
| "npu_cc_cal_hm0_dpm_ip_clk", |
| "npu_cc_cal_hm0_perf_cnt_clk", |
| "npu_cc_cal_hm1_cdc_clk", |
| "npu_cc_cal_hm1_clk", |
| "npu_cc_cal_hm1_dpm_ip_clk", |
| "npu_cc_cal_hm1_perf_cnt_clk", |
| "npu_cc_core_clk", |
| "npu_cc_dl_dpm_clk", |
| "npu_cc_dl_llm_clk", |
| "npu_cc_dpm_clk", |
| "npu_cc_dpm_temp_clk", |
| "npu_cc_dsp_ahbm_clk", |
| "npu_cc_dsp_ahbs_clk", |
| "npu_cc_dsp_axi_clk", |
| "npu_cc_dsp_bwmon_ahb_clk", |
| "npu_cc_dsp_bwmon_clk", |
| "npu_cc_isense_clk", |
| "npu_cc_llm_clk", |
| "npu_cc_llm_curr_clk", |
| "npu_cc_llm_temp_clk", |
| "npu_cc_noc_axi_clk", |
| "npu_cc_noc_dma_clk", |
| "npu_cc_s2p_clk", |
| "video_cc_ahb_clk", |
| "video_cc_mvs0_clk", |
| "video_cc_mvs0c_clk", |
| "video_cc_mvs1_clk", |
| "video_cc_mvs1_div2_clk", |
| "video_cc_mvs1c_clk", |
| }; |
| |
| static struct clk_debug_mux gcc_debug_mux = { |
| .priv = &debug_mux_priv, |
| .debug_offset = 0x62000, |
| .post_div_offset = 0x62004, |
| .cbcr_offset = 0x62008, |
| .src_sel_mask = 0x3FF, |
| .src_sel_shift = 0, |
| .post_div_mask = 0xF, |
| .post_div_shift = 0, |
| MUX_SRC_LIST( |
| { "cam_cc_bps_ahb_clk", 0x55, 2, CAM_CC, |
| 0x18, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_bps_areg_clk", 0x55, 2, CAM_CC, |
| 0x17, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_bps_axi_clk", 0x55, 2, CAM_CC, |
| 0x16, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_bps_clk", 0x55, 2, CAM_CC, |
| 0x14, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_camnoc_axi_clk", 0x55, 2, CAM_CC, |
| 0x3C, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_cci_0_clk", 0x55, 2, CAM_CC, |
| 0x39, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_cci_1_clk", 0x55, 2, CAM_CC, |
| 0x3A, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_core_ahb_clk", 0x55, 2, CAM_CC, |
| 0x40, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_cpas_ahb_clk", 0x55, 2, CAM_CC, |
| 0x3B, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_csi0phytimer_clk", 0x55, 2, CAM_CC, |
| 0x8, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_csi1phytimer_clk", 0x55, 2, CAM_CC, |
| 0xA, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_csi2phytimer_clk", 0x55, 2, CAM_CC, |
| 0xC, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_csi3phytimer_clk", 0x55, 2, CAM_CC, |
| 0xE, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_csi4phytimer_clk", 0x55, 2, CAM_CC, |
| 0x10, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_csi5phytimer_clk", 0x55, 2, CAM_CC, |
| 0x12, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_csiphy0_clk", 0x55, 2, CAM_CC, |
| 0x9, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_csiphy1_clk", 0x55, 2, CAM_CC, |
| 0xB, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_csiphy2_clk", 0x55, 2, CAM_CC, |
| 0xD, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_csiphy3_clk", 0x55, 2, CAM_CC, |
| 0xF, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_csiphy4_clk", 0x55, 2, CAM_CC, |
| 0x11, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_csiphy5_clk", 0x55, 2, CAM_CC, |
| 0x13, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_fd_core_clk", 0x55, 2, CAM_CC, |
| 0x37, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_fd_core_uar_clk", 0x55, 2, CAM_CC, |
| 0x38, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_icp_ahb_clk", 0x55, 2, CAM_CC, |
| 0x36, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_icp_clk", 0x55, 2, CAM_CC, |
| 0x35, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_0_ahb_clk", 0x55, 2, CAM_CC, |
| 0x26, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_0_areg_clk", 0x55, 2, CAM_CC, |
| 0x1F, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_0_axi_clk", 0x55, 2, CAM_CC, |
| 0x25, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_0_clk", 0x55, 2, CAM_CC, |
| 0x1E, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_0_cphy_rx_clk", 0x55, 2, CAM_CC, |
| 0x24, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_0_csid_clk", 0x55, 2, CAM_CC, |
| 0x22, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_0_dsp_clk", 0x55, 2, CAM_CC, |
| 0x21, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_1_ahb_clk", 0x55, 2, CAM_CC, |
| 0x2E, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_1_areg_clk", 0x55, 2, CAM_CC, |
| 0x29, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_1_axi_clk", 0x55, 2, CAM_CC, |
| 0x2D, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_1_clk", 0x55, 2, CAM_CC, |
| 0x27, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_1_cphy_rx_clk", 0x55, 2, CAM_CC, |
| 0x2C, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_1_csid_clk", 0x55, 2, CAM_CC, |
| 0x2B, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_1_dsp_clk", 0x55, 2, CAM_CC, |
| 0x2A, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_lite_ahb_clk", 0x55, 2, CAM_CC, |
| 0x32, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_lite_axi_clk", 0x55, 2, CAM_CC, |
| 0x49, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_lite_clk", 0x55, 2, CAM_CC, |
| 0x2F, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_lite_cphy_rx_clk", 0x55, 2, CAM_CC, |
| 0x31, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ife_lite_csid_clk", 0x55, 2, CAM_CC, |
| 0x30, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ipe_0_ahb_clk", 0x55, 2, CAM_CC, |
| 0x1D, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ipe_0_areg_clk", 0x55, 2, CAM_CC, |
| 0x1C, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ipe_0_axi_clk", 0x55, 2, CAM_CC, |
| 0x1B, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_ipe_0_clk", 0x55, 2, CAM_CC, |
| 0x19, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_jpeg_clk", 0x55, 2, CAM_CC, |
| 0x33, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_mclk0_clk", 0x55, 2, CAM_CC, |
| 0x1, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_mclk1_clk", 0x55, 2, CAM_CC, |
| 0x2, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_mclk2_clk", 0x55, 2, CAM_CC, |
| 0x3, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_mclk3_clk", 0x55, 2, CAM_CC, |
| 0x4, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_mclk4_clk", 0x55, 2, CAM_CC, |
| 0x5, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_mclk5_clk", 0x55, 2, CAM_CC, |
| 0x6, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_mclk6_clk", 0x55, 2, CAM_CC, |
| 0x7, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_sbi_ahb_clk", 0x55, 2, CAM_CC, |
| 0x4E, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_sbi_axi_clk", 0x55, 2, CAM_CC, |
| 0x4D, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_sbi_clk", 0x55, 2, CAM_CC, |
| 0x4A, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_sbi_cphy_rx_clk", 0x55, 2, CAM_CC, |
| 0x4C, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_sbi_csid_clk", 0x55, 2, CAM_CC, |
| 0x4B, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_sbi_ife_0_clk", 0x55, 2, CAM_CC, |
| 0x4F, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "cam_cc_sbi_ife_1_clk", 0x55, 2, CAM_CC, |
| 0x50, 0xFF, 0, 0xF, 0, 4, 0xD000, 0xD004, 0xD008 }, |
| { "disp_cc_mdss_ahb_clk", 0x56, 2, DISP_CC, |
| 0x2B, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_byte0_clk", 0x56, 2, DISP_CC, |
| 0x15, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_byte0_intf_clk", 0x56, 2, DISP_CC, |
| 0x16, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_byte1_clk", 0x56, 2, DISP_CC, |
| 0x17, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_byte1_intf_clk", 0x56, 2, DISP_CC, |
| 0x18, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_dp_aux1_clk", 0x56, 2, DISP_CC, |
| 0x25, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_dp_aux_clk", 0x56, 2, DISP_CC, |
| 0x20, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_dp_link1_clk", 0x56, 2, DISP_CC, |
| 0x22, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_dp_link1_intf_clk", 0x56, 2, DISP_CC, |
| 0x23, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_dp_link_clk", 0x56, 2, DISP_CC, |
| 0x1B, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_dp_link_intf_clk", 0x56, 2, DISP_CC, |
| 0x1C, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_dp_pixel1_clk", 0x56, 2, DISP_CC, |
| 0x1F, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_dp_pixel2_clk", 0x56, 2, DISP_CC, |
| 0x21, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_dp_pixel_clk", 0x56, 2, DISP_CC, |
| 0x1E, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_edp_aux_clk", 0x56, 2, DISP_CC, |
| 0x29, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_edp_gtc_clk", 0x56, 2, DISP_CC, |
| 0x2A, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_edp_link_clk", 0x56, 2, DISP_CC, |
| 0x27, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_edp_link_intf_clk", 0x56, 2, DISP_CC, |
| 0x28, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_edp_pixel_clk", 0x56, 2, DISP_CC, |
| 0x26, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_esc0_clk", 0x56, 2, DISP_CC, |
| 0x19, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_esc1_clk", 0x56, 2, DISP_CC, |
| 0x1A, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_mdp_clk", 0x56, 2, DISP_CC, |
| 0x11, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_mdp_lut_clk", 0x56, 2, DISP_CC, |
| 0x13, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_non_gdsc_ahb_clk", 0x56, 2, DISP_CC, |
| 0x2C, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_pclk0_clk", 0x56, 2, DISP_CC, |
| 0xF, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_pclk1_clk", 0x56, 2, DISP_CC, |
| 0x10, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_rot_clk", 0x56, 2, DISP_CC, |
| 0x12, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_rscc_ahb_clk", 0x56, 2, DISP_CC, |
| 0x2E, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_rscc_vsync_clk", 0x56, 2, DISP_CC, |
| 0x2D, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "disp_cc_mdss_vsync_clk", 0x56, 2, DISP_CC, |
| 0x14, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, |
| { "gcc_aggre_noc_pcie_tbu_clk", 0x36, 2, GCC, |
| 0x36, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_aggre_ufs_card_axi_clk", 0x142, 2, GCC, |
| 0x142, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_aggre_ufs_phy_axi_clk", 0x141, 2, GCC, |
| 0x141, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_aggre_usb3_prim_axi_clk", 0x13F, 2, GCC, |
| 0x13F, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_aggre_usb3_sec_axi_clk", 0x140, 2, GCC, |
| 0x140, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_camera_ahb_clk", 0x44, 2, GCC, |
| 0x44, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_camera_hf_axi_clk", 0x4D, 2, GCC, |
| 0x4D, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_camera_sf_axi_clk", 0x4E, 2, GCC, |
| 0x4E, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_cfg_noc_usb3_prim_axi_clk", 0x21, 2, GCC, |
| 0x21, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_cfg_noc_usb3_sec_axi_clk", 0x22, 2, GCC, |
| 0x22, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_cpuss_rbcpr_clk", 0xE1, 2, GCC, |
| 0xE1, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ddrss_gpu_axi_clk", 0xC4, 2, GCC, |
| 0xC4, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ddrss_pcie_sf_tbu_clk", 0xC5, 2, GCC, |
| 0xC5, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_disp_ahb_clk", 0x45, 2, GCC, |
| 0x45, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_disp_hf_axi_clk", 0x4F, 2, GCC, |
| 0x4F, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_disp_sf_axi_clk", 0x50, 2, GCC, |
| 0x50, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_dpm_clk", 0x197, 2, GCC, |
| 0x197, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_gp1_clk", 0xEF, 2, GCC, |
| 0xEF, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_gp2_clk", 0xF0, 2, GCC, |
| 0xF0, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_gp3_clk", 0xF1, 2, GCC, |
| 0xF1, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_gpu_cfg_ahb_clk", 0x161, 2, GCC, |
| 0x161, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_gpu_gpll0_clk_src", 0x167, 2, GCC, |
| 0x167, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_gpu_gpll0_div_clk_src", 0x168, 2, GCC, |
| 0x168, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_gpu_memnoc_gfx_clk", 0x164, 2, GCC, |
| 0x164, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_gpu_snoc_dvm_gfx_clk", 0x166, 2, GCC, |
| 0x166, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_npu_axi_clk", 0x17A, 2, GCC, |
| 0x17A, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_npu_bwmon_axi_clk", 0x19A, 2, GCC, |
| 0x19A, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_npu_bwmon_cfg_ahb_clk", 0x199, 2, GCC, |
| 0x199, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_npu_cfg_ahb_clk", 0x179, 2, GCC, |
| 0x179, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_npu_dma_clk", 0x17B, 2, GCC, |
| 0x17B, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_npu_gpll0_clk_src", 0x17E, 2, GCC, |
| 0x17E, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_npu_gpll0_div_clk_src", 0x17F, 2, GCC, |
| 0x17F, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie0_phy_refgen_clk", 0x103, 2, GCC, |
| 0x103, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie1_phy_refgen_clk", 0x104, 2, GCC, |
| 0x104, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie2_phy_refgen_clk", 0x105, 2, GCC, |
| 0x105, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_0_aux_clk", 0xF6, 2, GCC, |
| 0xF6, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_0_cfg_ahb_clk", 0xF5, 2, GCC, |
| 0xF5, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_0_mstr_axi_clk", 0xF4, 2, GCC, |
| 0xF4, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_0_pipe_clk", 0xF7, 2, GCC, |
| 0xF7, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_0_slv_axi_clk", 0xF3, 2, GCC, |
| 0xF3, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_0_slv_q2a_axi_clk", 0xF2, 2, GCC, |
| 0xF2, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_1_aux_clk", 0xFE, 2, GCC, |
| 0xFE, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_1_cfg_ahb_clk", 0xFD, 2, GCC, |
| 0xFD, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_1_mstr_axi_clk", 0xFC, 2, GCC, |
| 0xFC, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_1_pipe_clk", 0xFF, 2, GCC, |
| 0xFF, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_1_slv_axi_clk", 0xFB, 2, GCC, |
| 0xFB, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_1_slv_q2a_axi_clk", 0xFA, 2, GCC, |
| 0xFA, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_2_aux_clk", 0x191, 2, GCC, |
| 0x191, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_2_cfg_ahb_clk", 0x190, 2, GCC, |
| 0x190, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_2_mstr_axi_clk", 0x18F, 2, GCC, |
| 0x18F, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_2_pipe_clk", 0x192, 2, GCC, |
| 0x192, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_2_slv_axi_clk", 0x18E, 2, GCC, |
| 0x18E, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_2_slv_q2a_axi_clk", 0x18D, 2, GCC, |
| 0x18D, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pcie_phy_aux_clk", 0x102, 2, GCC, |
| 0x102, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_pdm2_clk", 0x9D, 2, GCC, |
| 0x9D, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_prng_ahb_clk", 0x9E, 2, GCC, |
| 0x9E, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap0_core_2x_clk", 0x88, 2, GCC, |
| 0x88, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap0_core_clk", 0x87, 2, GCC, |
| 0x87, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap0_s0_clk", 0x89, 2, GCC, |
| 0x89, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap0_s1_clk", 0x8A, 2, GCC, |
| 0x8A, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap0_s2_clk", 0x8B, 2, GCC, |
| 0x8B, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap0_s3_clk", 0x8C, 2, GCC, |
| 0x8C, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap0_s4_clk", 0x8D, 2, GCC, |
| 0x8D, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap0_s5_clk", 0x8E, 2, GCC, |
| 0x8E, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap0_s6_clk", 0x8F, 2, GCC, |
| 0x8F, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap0_s7_clk", 0x90, 2, GCC, |
| 0x90, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap1_core_2x_clk", 0x94, 2, GCC, |
| 0x94, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap1_core_clk", 0x93, 2, GCC, |
| 0x93, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap1_s0_clk", 0x95, 2, GCC, |
| 0x95, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap1_s1_clk", 0x96, 2, GCC, |
| 0x96, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap1_s2_clk", 0x97, 2, GCC, |
| 0x97, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap1_s3_clk", 0x98, 2, GCC, |
| 0x98, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap1_s4_clk", 0x99, 2, GCC, |
| 0x99, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap1_s5_clk", 0x9A, 2, GCC, |
| 0x9A, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap2_core_2x_clk", 0x184, 2, GCC, |
| 0x184, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap2_core_clk", 0x183, 2, GCC, |
| 0x183, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap2_s0_clk", 0x185, 2, GCC, |
| 0x185, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap2_s1_clk", 0x186, 2, GCC, |
| 0x186, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap2_s2_clk", 0x187, 2, GCC, |
| 0x187, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap2_s3_clk", 0x188, 2, GCC, |
| 0x188, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap2_s4_clk", 0x189, 2, GCC, |
| 0x189, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_qupv3_wrap2_s5_clk", 0x18A, 2, GCC, |
| 0x18A, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_sdcc2_ahb_clk", 0x82, 2, GCC, |
| 0x82, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_sdcc2_apps_clk", 0x81, 2, GCC, |
| 0x81, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_sdcc4_ahb_clk", 0x84, 2, GCC, |
| 0x84, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_sdcc4_apps_clk", 0x83, 2, GCC, |
| 0x83, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_sys_noc_cpuss_ahb_clk", 0xC, 2, GCC, |
| 0xC, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_tsif_ref_clk", 0xA0, 2, GCC, |
| 0xA0, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_card_ahb_clk", 0x107, 2, GCC, |
| 0x107, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_card_axi_clk", 0x106, 2, GCC, |
| 0x106, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_card_ice_core_clk", 0x10D, 2, GCC, |
| 0x10D, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_card_phy_aux_clk", 0x10E, 2, GCC, |
| 0x10E, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_card_rx_symbol_0_clk", 0x109, 2, GCC, |
| 0x109, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_card_rx_symbol_1_clk", 0x10F, 2, GCC, |
| 0x10F, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_card_tx_symbol_0_clk", 0x108, 2, GCC, |
| 0x108, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_card_unipro_core_clk", 0x10C, 2, GCC, |
| 0x10C, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_phy_ahb_clk", 0x113, 2, GCC, |
| 0x113, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_phy_axi_clk", 0x112, 2, GCC, |
| 0x112, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_phy_ice_core_clk", 0x119, 2, GCC, |
| 0x119, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_phy_phy_aux_clk", 0x11A, 2, GCC, |
| 0x11A, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_phy_rx_symbol_0_clk", 0x115, 2, GCC, |
| 0x115, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_phy_rx_symbol_1_clk", 0x11B, 2, GCC, |
| 0x11B, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_phy_tx_symbol_0_clk", 0x114, 2, GCC, |
| 0x114, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_ufs_phy_unipro_core_clk", 0x118, 2, GCC, |
| 0x118, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_usb30_prim_master_clk", 0x6E, 2, GCC, |
| 0x6E, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_usb30_prim_mock_utmi_clk", 0x70, 2, GCC, |
| 0x70, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_usb30_sec_master_clk", 0x75, 2, GCC, |
| 0x75, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_usb30_sec_mock_utmi_clk", 0x77, 2, GCC, |
| 0x77, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_usb3_prim_phy_aux_clk", 0x71, 2, GCC, |
| 0x71, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_usb3_prim_phy_com_aux_clk", 0x72, 2, GCC, |
| 0x72, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_usb3_prim_phy_pipe_clk", 0x73, 2, GCC, |
| 0x73, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_usb3_sec_phy_aux_clk", 0x78, 2, GCC, |
| 0x78, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_usb3_sec_phy_com_aux_clk", 0x79, 2, GCC, |
| 0x79, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_usb3_sec_phy_pipe_clk", 0x7A, 2, GCC, |
| 0x7A, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_video_ahb_clk", 0x43, 2, GCC, |
| 0x43, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_video_axi0_clk", 0x4B, 2, GCC, |
| 0x4B, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gcc_video_axi1_clk", 0x4C, 2, GCC, |
| 0x4C, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "gpu_cc_ahb_clk", 0x163, 2, GPU_CC, |
| 0x10, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, |
| { "gpu_cc_cx_gmu_clk", 0x163, 2, GPU_CC, |
| 0x18, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, |
| { "gpu_cc_cx_snoc_dvm_clk", 0x163, 2, GPU_CC, |
| 0x15, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, |
| { "gpu_cc_gx_gmu_clk", 0x163, 2, GPU_CC, |
| 0xF, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, |
| { "gpu_cc_gx_vsense_clk", 0x163, 2, GPU_CC, |
| 0xC, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, |
| { "measure_only_cnoc_clk", 0x19, 2, GCC, |
| 0x19, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "measure_only_gpu_cc_cx_gfx3d_clk", 0x163, 2, GPU_CC, |
| 0x1A, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, |
| { "measure_only_gpu_cc_cx_gfx3d_slv_clk", 0x163, 2, GPU_CC, |
| 0x1B, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, |
| { "measure_only_gpu_cc_gx_gfx3d_clk", 0x163, 2, GPU_CC, |
| 0xB, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, |
| { "measure_only_ipa_2x_clk", 0x147, 2, GCC, |
| 0x147, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "measure_only_snoc_clk", 0x7, 2, GCC, |
| 0x7, 0x3FF, 0, 0xF, 0, 2, 0x62000, 0x62004, 0x62008 }, |
| { "npu_cc_bto_core_clk", 0x180, 2, NPU_CC, |
| 0x19, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_bwmon_clk", 0x180, 2, NPU_CC, |
| 0x18, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_cal_hm0_cdc_clk", 0x180, 2, NPU_CC, |
| 0xB, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_cal_hm0_clk", 0x180, 2, NPU_CC, |
| 0x2, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_cal_hm0_dpm_ip_clk", 0x180, 2, NPU_CC, |
| 0xC, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_cal_hm0_perf_cnt_clk", 0x180, 2, NPU_CC, |
| 0xD, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_cal_hm1_cdc_clk", 0x180, 2, NPU_CC, |
| 0xE, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_cal_hm1_clk", 0x180, 2, NPU_CC, |
| 0x3, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_cal_hm1_dpm_ip_clk", 0x180, 2, NPU_CC, |
| 0xF, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_cal_hm1_perf_cnt_clk", 0x180, 2, NPU_CC, |
| 0x10, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_core_clk", 0x180, 2, NPU_CC, |
| 0x4, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_dl_dpm_clk", 0x180, 2, NPU_CC, |
| 0x23, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_dl_llm_clk", 0x180, 2, NPU_CC, |
| 0x22, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_dpm_clk", 0x180, 2, NPU_CC, |
| 0x8, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_dpm_temp_clk", 0x180, 2, NPU_CC, |
| 0x14, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_dsp_ahbm_clk", 0x180, 2, NPU_CC, |
| 0x1C, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_dsp_ahbs_clk", 0x180, 2, NPU_CC, |
| 0x1B, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_dsp_axi_clk", 0x180, 2, NPU_CC, |
| 0x1E, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_dsp_bwmon_ahb_clk", 0x180, 2, NPU_CC, |
| 0x1D, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_dsp_bwmon_clk", 0x180, 2, NPU_CC, |
| 0x1F, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_isense_clk", 0x180, 2, NPU_CC, |
| 0x7, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_llm_clk", 0x180, 2, NPU_CC, |
| 0x6, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_llm_curr_clk", 0x180, 2, NPU_CC, |
| 0x21, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_llm_temp_clk", 0x180, 2, NPU_CC, |
| 0x15, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_noc_axi_clk", 0x180, 2, NPU_CC, |
| 0x12, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_noc_dma_clk", 0x180, 2, NPU_CC, |
| 0x11, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "npu_cc_s2p_clk", 0x180, 2, NPU_CC, |
| 0x16, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, |
| { "video_cc_ahb_clk", 0x57, 2, VIDEO_CC, |
| 0x7, 0x3F, 0, 0x7, 0, 3, 0xA4C, 0xE9C, 0xEBC }, |
| { "video_cc_mvs0_clk", 0x57, 2, VIDEO_CC, |
| 0x3, 0x3F, 0, 0x7, 0, 3, 0xA4C, 0xE9C, 0xEBC }, |
| { "video_cc_mvs0c_clk", 0x57, 2, VIDEO_CC, |
| 0x1, 0x3F, 0, 0x7, 0, 3, 0xA4C, 0xE9C, 0xEBC }, |
| { "video_cc_mvs1_clk", 0x57, 2, VIDEO_CC, |
| 0x5, 0x3F, 0, 0x7, 0, 3, 0xA4C, 0xE9C, 0xEBC }, |
| { "video_cc_mvs1_div2_clk", 0x57, 2, VIDEO_CC, |
| 0x8, 0x3F, 0, 0x7, 0, 3, 0xA4C, 0xE9C, 0xEBC }, |
| { "video_cc_mvs1c_clk", 0x57, 2, VIDEO_CC, |
| 0x9, 0x3F, 0, 0x7, 0, 3, 0xA4C, 0xE9C, 0xEBC }, |
| ), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gcc_debug_mux", |
| .ops = &clk_debug_mux_ops, |
| .parent_names = debug_mux_parent_names, |
| .num_parents = ARRAY_SIZE(debug_mux_parent_names), |
| .flags = CLK_IS_MEASURE, |
| }, |
| }; |
| |
| static const struct of_device_id clk_debug_match_table[] = { |
| { .compatible = "qcom,kona-debugcc" }, |
| { } |
| }; |
| |
| static int map_debug_bases(struct platform_device *pdev, char *base, int cc) |
| { |
| if (!of_get_property(pdev->dev.of_node, base, NULL)) |
| return -ENODEV; |
| |
| gcc_debug_mux.regmap[cc] = |
| syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
| base); |
| if (IS_ERR(gcc_debug_mux.regmap[cc])) { |
| pr_err("Failed to map %s (ret=%ld)\n", base, |
| PTR_ERR(gcc_debug_mux.regmap[cc])); |
| return PTR_ERR(gcc_debug_mux.regmap[cc]); |
| } |
| return 0; |
| } |
| |
| static int clk_debug_kona_probe(struct platform_device *pdev) |
| { |
| struct clk *clk; |
| int ret = 0; |
| |
| clk = devm_clk_get(&pdev->dev, "xo_clk_src"); |
| if (IS_ERR(clk)) { |
| if (PTR_ERR(clk) != -EPROBE_DEFER) |
| dev_err(&pdev->dev, "Unable to get xo clock\n"); |
| return PTR_ERR(clk); |
| } |
| |
| debug_mux_priv.cxo = clk; |
| |
| gcc_debug_mux.regmap = devm_kcalloc(&pdev->dev, MAX_NUM_CC, |
| sizeof(*gcc_debug_mux.regmap), GFP_KERNEL); |
| if (!gcc_debug_mux.regmap) |
| return -ENOMEM; |
| |
| ret = map_debug_bases(pdev, "qcom,gcc", GCC); |
| if (ret) |
| return ret; |
| |
| ret = map_debug_bases(pdev, "qcom,dispcc", DISP_CC); |
| if (ret) |
| return ret; |
| |
| ret = map_debug_bases(pdev, "qcom,videocc", VIDEO_CC); |
| if (ret) |
| return ret; |
| |
| ret = map_debug_bases(pdev, "qcom,camcc", CAM_CC); |
| if (ret) |
| return ret; |
| |
| ret = map_debug_bases(pdev, "qcom,gpucc", GPU_CC); |
| if (ret) |
| return ret; |
| |
| ret = map_debug_bases(pdev, "qcom,npucc", NPU_CC); |
| if (ret) |
| return ret; |
| |
| clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw); |
| if (IS_ERR(clk)) { |
| dev_err(&pdev->dev, "Unable to register GCC debug mux\n"); |
| return PTR_ERR(clk); |
| } |
| |
| ret = clk_debug_measure_register(&gcc_debug_mux.hw); |
| if (ret) |
| dev_err(&pdev->dev, "Could not register Measure clock\n"); |
| |
| return ret; |
| } |
| |
| static struct platform_driver clk_debug_driver = { |
| .probe = clk_debug_kona_probe, |
| .driver = { |
| .name = "debugcc-kona", |
| .of_match_table = clk_debug_match_table, |
| .owner = THIS_MODULE, |
| }, |
| }; |
| |
| int __init clk_debug_kona_init(void) |
| { |
| return platform_driver_register(&clk_debug_driver); |
| } |
| fs_initcall(clk_debug_kona_init); |
| |
| MODULE_DESCRIPTION("QTI DEBUG CC KONA Driver"); |
| MODULE_LICENSE("GPL v2"); |
| MODULE_ALIAS("platform:debugcc-kona"); |