| /* |
| * dts file for Hisilicon Hi6220 SoC |
| * |
| * Copyright (C) 2015, Hisilicon Ltd. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/hi6220-clock.h> |
| |
| / { |
| compatible = "hisilicon,hi6220"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| core2 { |
| cpu = <&cpu2>; |
| }; |
| core3 { |
| cpu = <&cpu3>; |
| }; |
| }; |
| cluster1 { |
| core0 { |
| cpu = <&cpu4>; |
| }; |
| core1 { |
| cpu = <&cpu5>; |
| }; |
| core2 { |
| cpu = <&cpu6>; |
| }; |
| core3 { |
| cpu = <&cpu7>; |
| }; |
| }; |
| }; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| }; |
| |
| cpu1: cpu@1 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| }; |
| |
| cpu2: cpu@2 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x2>; |
| enable-method = "psci"; |
| }; |
| |
| cpu3: cpu@3 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x3>; |
| enable-method = "psci"; |
| }; |
| |
| cpu4: cpu@100 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| }; |
| |
| cpu5: cpu@101 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x101>; |
| enable-method = "psci"; |
| }; |
| |
| cpu6: cpu@102 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x102>; |
| enable-method = "psci"; |
| }; |
| |
| cpu7: cpu@103 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x103>; |
| enable-method = "psci"; |
| }; |
| }; |
| |
| gic: interrupt-controller@f6801000 { |
| compatible = "arm,gic-400"; |
| reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ |
| <0x0 0xf6802000 0 0x2000>, /* GICC */ |
| <0x0 0xf6804000 0 0x2000>, /* GICH */ |
| <0x0 0xf6806000 0 0x2000>; /* GICV */ |
| #address-cells = <0>; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| ao_ctrl: ao_ctrl@f7800000 { |
| compatible = "hisilicon,hi6220-aoctrl", "syscon"; |
| reg = <0x0 0xf7800000 0x0 0x2000>; |
| #clock-cells = <1>; |
| }; |
| |
| sys_ctrl: sys_ctrl@f7030000 { |
| compatible = "hisilicon,hi6220-sysctrl", "syscon"; |
| reg = <0x0 0xf7030000 0x0 0x2000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| media_ctrl: media_ctrl@f4410000 { |
| compatible = "hisilicon,hi6220-mediactrl", "syscon"; |
| reg = <0x0 0xf4410000 0x0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| pm_ctrl: pm_ctrl@f7032000 { |
| compatible = "hisilicon,hi6220-pmctrl", "syscon"; |
| reg = <0x0 0xf7032000 0x0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| uart0: uart@f8015000 { /* console */ |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xf8015000 0x0 0x1000>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ao_ctrl HI6220_UART0_PCLK>, |
| <&ao_ctrl HI6220_UART0_PCLK>; |
| clock-names = "uartclk", "apb_pclk"; |
| }; |
| |
| uart1: uart@f7111000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xf7111000 0x0 0x1000>; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&sys_ctrl HI6220_UART1_PCLK>, |
| <&sys_ctrl HI6220_UART1_PCLK>; |
| clock-names = "uartclk", "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| uart2: uart@f7112000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xf7112000 0x0 0x1000>; |
| interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&sys_ctrl HI6220_UART2_PCLK>, |
| <&sys_ctrl HI6220_UART2_PCLK>; |
| clock-names = "uartclk", "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| uart3: uart@f7113000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xf7113000 0x0 0x1000>; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&sys_ctrl HI6220_UART3_PCLK>, |
| <&sys_ctrl HI6220_UART3_PCLK>; |
| clock-names = "uartclk", "apb_pclk"; |
| }; |
| |
| uart4: uart@f7114000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xf7114000 0x0 0x1000>; |
| interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&sys_ctrl HI6220_UART4_PCLK>, |
| <&sys_ctrl HI6220_UART4_PCLK>; |
| clock-names = "uartclk", "apb_pclk"; |
| status = "disabled"; |
| }; |
| }; |
| }; |