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gerrit-public.fairphone.software / kernel / msm-4.19 / 0080b7aae88c75e2a6b38dfcb228b0f239e18e3c / . / drivers / char / synclink_gt.c
blob: 8818042bad7cdc1703a950d9e4e6f4a55a44a48d [file] [log] [blame]
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1/*
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame^]2 * $Id: synclink_gt.c,v 4.25 2006/02/06 21:20:33 paulkf Exp $
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3 *
4 * Device driver for Microgate SyncLink GT serial adapters.
5 *
6 * written by Paul Fulghum for Microgate Corporation
7 * paulkf@microgate.com
8 *
9 * Microgate and SyncLink are trademarks of Microgate Corporation
10 *
11 * This code is released under the GNU General Public License (GPL)
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
17 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
21 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
23 * OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26/*
27 * DEBUG OUTPUT DEFINITIONS
28 *
29 * uncomment lines below to enable specific types of debug output
30 *
31 * DBGINFO information - most verbose output
32 * DBGERR serious errors
33 * DBGBH bottom half service routine debugging
34 * DBGISR interrupt service routine debugging
35 * DBGDATA output receive and transmit data
36 * DBGTBUF output transmit DMA buffers and registers
37 * DBGRBUF output receive DMA buffers and registers
38 */
39
40#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
41#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
42#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
43#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
44#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
45//#define DBGTBUF(info) dump_tbufs(info)
46//#define DBGRBUF(info) dump_rbufs(info)
47
48
49#include <linux/config.h>
50#include <linux/module.h>
51#include <linux/version.h>
52#include <linux/errno.h>
53#include <linux/signal.h>
54#include <linux/sched.h>
55#include <linux/timer.h>
56#include <linux/interrupt.h>
57#include <linux/pci.h>
58#include <linux/tty.h>
59#include <linux/tty_flip.h>
60#include <linux/serial.h>
61#include <linux/major.h>
62#include <linux/string.h>
63#include <linux/fcntl.h>
64#include <linux/ptrace.h>
65#include <linux/ioport.h>
66#include <linux/mm.h>
67#include <linux/slab.h>
68#include <linux/netdevice.h>
69#include <linux/vmalloc.h>
70#include <linux/init.h>
71#include <linux/delay.h>
72#include <linux/ioctl.h>
73#include <linux/termios.h>
74#include <linux/bitops.h>
75#include <linux/workqueue.h>
76#include <linux/hdlc.h>
77
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]78#include <asm/system.h>
79#include <asm/io.h>
80#include <asm/irq.h>
81#include <asm/dma.h>
82#include <asm/types.h>
83#include <asm/uaccess.h>
84
85#include "linux/synclink.h"
86
87#ifdef CONFIG_HDLC_MODULE
88#define CONFIG_HDLC 1
89#endif
90
91/*
92 * module identification
93 */
94static char *driver_name = "SyncLink GT";
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame^]95static char *driver_version = "$Revision: 4.25 $";
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]96static char *tty_driver_name = "synclink_gt";
97static char *tty_dev_prefix = "ttySLG";
98MODULE_LICENSE("GPL");
99#define MGSL_MAGIC 0x5401
100#define MAX_DEVICES 12
101
102static struct pci_device_id pci_table[] = {
103 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
104 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
105 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
106 {0,}, /* terminate list */
107};
108MODULE_DEVICE_TABLE(pci, pci_table);
109
110static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
111static void remove_one(struct pci_dev *dev);
112static struct pci_driver pci_driver = {
113 .name = "synclink_gt",
114 .id_table = pci_table,
115 .probe = init_one,
116 .remove = __devexit_p(remove_one),
117};
118
119static int pci_registered;
120
121/*
122 * module configuration and status
123 */
124static struct slgt_info *slgt_device_list;
125static int slgt_device_count;
126
127static int ttymajor;
128static int debug_level;
129static int maxframe[MAX_DEVICES];
130static int dosyncppp[MAX_DEVICES];
131
132module_param(ttymajor, int, 0);
133module_param(debug_level, int, 0);
134module_param_array(maxframe, int, NULL, 0);
135module_param_array(dosyncppp, int, NULL, 0);
136
137MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
138MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
139MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
140MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
141
142/*
143 * tty support and callbacks
144 */
145#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
146
147static struct tty_driver *serial_driver;
148
149static int open(struct tty_struct *tty, struct file * filp);
150static void close(struct tty_struct *tty, struct file * filp);
151static void hangup(struct tty_struct *tty);
152static void set_termios(struct tty_struct *tty, struct termios *old_termios);
153
154static int write(struct tty_struct *tty, const unsigned char *buf, int count);
155static void put_char(struct tty_struct *tty, unsigned char ch);
156static void send_xchar(struct tty_struct *tty, char ch);
157static void wait_until_sent(struct tty_struct *tty, int timeout);
158static int write_room(struct tty_struct *tty);
159static void flush_chars(struct tty_struct *tty);
160static void flush_buffer(struct tty_struct *tty);
161static void tx_hold(struct tty_struct *tty);
162static void tx_release(struct tty_struct *tty);
163
164static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
165static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
166static int chars_in_buffer(struct tty_struct *tty);
167static void throttle(struct tty_struct * tty);
168static void unthrottle(struct tty_struct * tty);
169static void set_break(struct tty_struct *tty, int break_state);
170
171/*
172 * generic HDLC support and callbacks
173 */
174#ifdef CONFIG_HDLC
175#define dev_to_port(D) (dev_to_hdlc(D)->priv)
176static void hdlcdev_tx_done(struct slgt_info *info);
177static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
178static int hdlcdev_init(struct slgt_info *info);
179static void hdlcdev_exit(struct slgt_info *info);
180#endif
181
182
183/*
184 * device specific structures, macros and functions
185 */
186
187#define SLGT_MAX_PORTS 4
188#define SLGT_REG_SIZE 256
189
190/*
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame^]191 * conditional wait facility
192 */
193struct cond_wait {
194 struct cond_wait *next;
195 wait_queue_head_t q;
196 wait_queue_t wait;
197 unsigned int data;
198};
199static void init_cond_wait(struct cond_wait *w, unsigned int data);
200static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
201static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
202static void flush_cond_wait(struct cond_wait **head);
203
204/*
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]205 * DMA buffer descriptor and access macros
206 */
207struct slgt_desc
208{
209 unsigned short count;
210 unsigned short status;
211 unsigned int pbuf; /* physical address of data buffer */
212 unsigned int next; /* physical address of next descriptor */
213
214 /* driver book keeping */
215 char *buf; /* virtual address of data buffer */
216 unsigned int pdesc; /* physical address of this descriptor */
217 dma_addr_t buf_dma_addr;
218};
219
220#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
221#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
222#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
223#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
224#define desc_count(a) (le16_to_cpu((a).count))
225#define desc_status(a) (le16_to_cpu((a).status))
226#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
227#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
228#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
229#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
230#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
231
232struct _input_signal_events {
233 int ri_up;
234 int ri_down;
235 int dsr_up;
236 int dsr_down;
237 int dcd_up;
238 int dcd_down;
239 int cts_up;
240 int cts_down;
241};
242
243/*
244 * device instance data structure
245 */
246struct slgt_info {
247 void *if_ptr; /* General purpose pointer (used by SPPP) */
248
249 struct slgt_info *next_device; /* device list link */
250
251 int magic;
252 int flags;
253
254 char device_name[25];
255 struct pci_dev *pdev;
256
257 int port_count; /* count of ports on adapter */
258 int adapter_num; /* adapter instance number */
259 int port_num; /* port instance number */
260
261 /* array of pointers to port contexts on this adapter */
262 struct slgt_info *port_array[SLGT_MAX_PORTS];
263
264 int count; /* count of opens */
265 int line; /* tty line instance number */
266 unsigned short close_delay;
267 unsigned short closing_wait; /* time to wait before closing */
268
269 struct mgsl_icount icount;
270
271 struct tty_struct *tty;
272 int timeout;
273 int x_char; /* xon/xoff character */
274 int blocked_open; /* # of blocked opens */
275 unsigned int read_status_mask;
276 unsigned int ignore_status_mask;
277
278 wait_queue_head_t open_wait;
279 wait_queue_head_t close_wait;
280
281 wait_queue_head_t status_event_wait_q;
282 wait_queue_head_t event_wait_q;
283 struct timer_list tx_timer;
284 struct timer_list rx_timer;
285
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame^]286 unsigned int gpio_present;
287 struct cond_wait *gpio_wait_q;
288
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]289 spinlock_t lock; /* spinlock for synchronizing with ISR */
290
291 struct work_struct task;
292 u32 pending_bh;
293 int bh_requested;
294 int bh_running;
295
296 int isr_overflow;
297 int irq_requested; /* nonzero if IRQ requested */
298 int irq_occurred; /* for diagnostics use */
299
300 /* device configuration */
301
302 unsigned int bus_type;
303 unsigned int irq_level;
304 unsigned long irq_flags;
305
306 unsigned char __iomem * reg_addr; /* memory mapped registers address */
307 u32 phys_reg_addr;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]308 int reg_addr_requested;
309
310 MGSL_PARAMS params; /* communications parameters */
311 u32 idle_mode;
312 u32 max_frame_size; /* as set by device config */
313
314 unsigned int raw_rx_size;
315 unsigned int if_mode;
316
317 /* device status */
318
319 int rx_enabled;
320 int rx_restart;
321
322 int tx_enabled;
323 int tx_active;
324
325 unsigned char signals; /* serial signal states */
Darren Jenkins2641dfd2006-02-28 16:59:20 -0800[diff] [blame]326 int init_error; /* initialization error */
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]327
328 unsigned char *tx_buf;
329 int tx_count;
330
331 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
332 char char_buf[MAX_ASYNC_BUFFER_SIZE];
333 BOOLEAN drop_rts_on_tx_done;
334 struct _input_signal_events input_signal_events;
335
336 int dcd_chkcount; /* check counts to prevent */
337 int cts_chkcount; /* too many IRQs if a signal */
338 int dsr_chkcount; /* is floating */
339 int ri_chkcount;
340
341 char *bufs; /* virtual address of DMA buffer lists */
342 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
343
344 unsigned int rbuf_count;
345 struct slgt_desc *rbufs;
346 unsigned int rbuf_current;
347 unsigned int rbuf_index;
348
349 unsigned int tbuf_count;
350 struct slgt_desc *tbufs;
351 unsigned int tbuf_current;
352 unsigned int tbuf_start;
353
354 unsigned char *tmp_rbuf;
355 unsigned int tmp_rbuf_count;
356
357 /* SPPP/Cisco HDLC device parts */
358
359 int netcount;
360 int dosyncppp;
361 spinlock_t netlock;
362#ifdef CONFIG_HDLC
363 struct net_device *netdev;
364#endif
365
366};
367
368static MGSL_PARAMS default_params = {
369 .mode = MGSL_MODE_HDLC,
370 .loopback = 0,
371 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
372 .encoding = HDLC_ENCODING_NRZI_SPACE,
373 .clock_speed = 0,
374 .addr_filter = 0xff,
375 .crc_type = HDLC_CRC_16_CCITT,
376 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
377 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
378 .data_rate = 9600,
379 .data_bits = 8,
380 .stop_bits = 1,
381 .parity = ASYNC_PARITY_NONE
382};
383
384
385#define BH_RECEIVE 1
386#define BH_TRANSMIT 2
387#define BH_STATUS 4
388#define IO_PIN_SHUTDOWN_LIMIT 100
389
390#define DMABUFSIZE 256
391#define DESC_LIST_SIZE 4096
392
393#define MASK_PARITY BIT1
394#define MASK_FRAMING BIT2
395#define MASK_BREAK BIT3
396#define MASK_OVERRUN BIT4
397
398#define GSR 0x00 /* global status */
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame^]399#define JCR 0x04 /* JTAG control */
400#define IODR 0x08 /* GPIO direction */
401#define IOER 0x0c /* GPIO interrupt enable */
402#define IOVR 0x10 /* GPIO value */
403#define IOSR 0x14 /* GPIO interrupt status */
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]404#define TDR 0x80 /* tx data */
405#define RDR 0x80 /* rx data */
406#define TCR 0x82 /* tx control */
407#define TIR 0x84 /* tx idle */
408#define TPR 0x85 /* tx preamble */
409#define RCR 0x86 /* rx control */
410#define VCR 0x88 /* V.24 control */
411#define CCR 0x89 /* clock control */
412#define BDR 0x8a /* baud divisor */
413#define SCR 0x8c /* serial control */
414#define SSR 0x8e /* serial status */
415#define RDCSR 0x90 /* rx DMA control/status */
416#define TDCSR 0x94 /* tx DMA control/status */
417#define RDDAR 0x98 /* rx DMA descriptor address */
418#define TDDAR 0x9c /* tx DMA descriptor address */
419
420#define RXIDLE BIT14
421#define RXBREAK BIT14
422#define IRQ_TXDATA BIT13
423#define IRQ_TXIDLE BIT12
424#define IRQ_TXUNDER BIT11 /* HDLC */
425#define IRQ_RXDATA BIT10
426#define IRQ_RXIDLE BIT9 /* HDLC */
427#define IRQ_RXBREAK BIT9 /* async */
428#define IRQ_RXOVER BIT8
429#define IRQ_DSR BIT7
430#define IRQ_CTS BIT6
431#define IRQ_DCD BIT5
432#define IRQ_RI BIT4
433#define IRQ_ALL 0x3ff0
434#define IRQ_MASTER BIT0
435
436#define slgt_irq_on(info, mask) \
437 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
438#define slgt_irq_off(info, mask) \
439 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
440
441static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
442static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
443static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
444static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
445static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
446static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
447
448static void msc_set_vcr(struct slgt_info *info);
449
450static int startup(struct slgt_info *info);
451static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
452static void shutdown(struct slgt_info *info);
453static void program_hw(struct slgt_info *info);
454static void change_params(struct slgt_info *info);
455
456static int register_test(struct slgt_info *info);
457static int irq_test(struct slgt_info *info);
458static int loopback_test(struct slgt_info *info);
459static int adapter_test(struct slgt_info *info);
460
461static void reset_adapter(struct slgt_info *info);
462static void reset_port(struct slgt_info *info);
463static void async_mode(struct slgt_info *info);
464static void hdlc_mode(struct slgt_info *info);
465
466static void rx_stop(struct slgt_info *info);
467static void rx_start(struct slgt_info *info);
468static void reset_rbufs(struct slgt_info *info);
469static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
470static void rdma_reset(struct slgt_info *info);
471static int rx_get_frame(struct slgt_info *info);
472static int rx_get_buf(struct slgt_info *info);
473
474static void tx_start(struct slgt_info *info);
475static void tx_stop(struct slgt_info *info);
476static void tx_set_idle(struct slgt_info *info);
477static unsigned int free_tbuf_count(struct slgt_info *info);
478static void reset_tbufs(struct slgt_info *info);
479static void tdma_reset(struct slgt_info *info);
480static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
481
482static void get_signals(struct slgt_info *info);
483static void set_signals(struct slgt_info *info);
484static void enable_loopback(struct slgt_info *info);
485static void set_rate(struct slgt_info *info, u32 data_rate);
486
487static int bh_action(struct slgt_info *info);
488static void bh_handler(void* context);
489static void bh_transmit(struct slgt_info *info);
490static void isr_serial(struct slgt_info *info);
491static void isr_rdma(struct slgt_info *info);
492static void isr_txeom(struct slgt_info *info, unsigned short status);
493static void isr_tdma(struct slgt_info *info);
494static irqreturn_t slgt_interrupt(int irq, void *dev_id, struct pt_regs * regs);
495
496static int alloc_dma_bufs(struct slgt_info *info);
497static void free_dma_bufs(struct slgt_info *info);
498static int alloc_desc(struct slgt_info *info);
499static void free_desc(struct slgt_info *info);
500static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
501static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
502
503static int alloc_tmp_rbuf(struct slgt_info *info);
504static void free_tmp_rbuf(struct slgt_info *info);
505
506static void tx_timeout(unsigned long context);
507static void rx_timeout(unsigned long context);
508
509/*
510 * ioctl handlers
511 */
512static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
513static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
514static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
515static int get_txidle(struct slgt_info *info, int __user *idle_mode);
516static int set_txidle(struct slgt_info *info, int idle_mode);
517static int tx_enable(struct slgt_info *info, int enable);
518static int tx_abort(struct slgt_info *info);
519static int rx_enable(struct slgt_info *info, int enable);
520static int modem_input_wait(struct slgt_info *info,int arg);
521static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
522static int tiocmget(struct tty_struct *tty, struct file *file);
523static int tiocmset(struct tty_struct *tty, struct file *file,
524 unsigned int set, unsigned int clear);
525static void set_break(struct tty_struct *tty, int break_state);
526static int get_interface(struct slgt_info *info, int __user *if_mode);
527static int set_interface(struct slgt_info *info, int if_mode);
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame^]528static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
529static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
530static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]531
532/*
533 * driver functions
534 */
535static void add_device(struct slgt_info *info);
536static void device_init(int adapter_num, struct pci_dev *pdev);
537static int claim_resources(struct slgt_info *info);
538static void release_resources(struct slgt_info *info);
539
540/*
541 * DEBUG OUTPUT CODE
542 */
543#ifndef DBGINFO
544#define DBGINFO(fmt)
545#endif
546#ifndef DBGERR
547#define DBGERR(fmt)
548#endif
549#ifndef DBGBH
550#define DBGBH(fmt)
551#endif
552#ifndef DBGISR
553#define DBGISR(fmt)
554#endif
555
556#ifdef DBGDATA
557static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
558{
559 int i;
560 int linecount;
561 printk("%s %s data:\n",info->device_name, label);
562 while(count) {
563 linecount = (count > 16) ? 16 : count;
564 for(i=0; i < linecount; i++)
565 printk("%02X ",(unsigned char)data[i]);
566 for(;i<17;i++)
567 printk(" ");
568 for(i=0;i<linecount;i++) {
569 if (data[i]>=040 && data[i]<=0176)
570 printk("%c",data[i]);
571 else
572 printk(".");
573 }
574 printk("\n");
575 data += linecount;
576 count -= linecount;
577 }
578}
579#else
580#define DBGDATA(info, buf, size, label)
581#endif
582
583#ifdef DBGTBUF
584static void dump_tbufs(struct slgt_info *info)
585{
586 int i;
587 printk("tbuf_current=%d\n", info->tbuf_current);
588 for (i=0 ; i < info->tbuf_count ; i++) {
589 printk("%d: count=%04X status=%04X\n",
590 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
591 }
592}
593#else
594#define DBGTBUF(info)
595#endif
596
597#ifdef DBGRBUF
598static void dump_rbufs(struct slgt_info *info)
599{
600 int i;
601 printk("rbuf_current=%d\n", info->rbuf_current);
602 for (i=0 ; i < info->rbuf_count ; i++) {
603 printk("%d: count=%04X status=%04X\n",
604 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
605 }
606}
607#else
608#define DBGRBUF(info)
609#endif
610
611static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
612{
613#ifdef SANITY_CHECK
614 if (!info) {
615 printk("null struct slgt_info for (%s) in %s\n", devname, name);
616 return 1;
617 }
618 if (info->magic != MGSL_MAGIC) {
619 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
620 return 1;
621 }
622#else
623 if (!info)
624 return 1;
625#endif
626 return 0;
627}
628
629/**
630 * line discipline callback wrappers
631 *
632 * The wrappers maintain line discipline references
633 * while calling into the line discipline.
634 *
635 * ldisc_receive_buf - pass receive data to line discipline
636 */
637static void ldisc_receive_buf(struct tty_struct *tty,
638 const __u8 *data, char *flags, int count)
639{
640 struct tty_ldisc *ld;
641 if (!tty)
642 return;
643 ld = tty_ldisc_ref(tty);
644 if (ld) {
645 if (ld->receive_buf)
646 ld->receive_buf(tty, data, flags, count);
647 tty_ldisc_deref(ld);
648 }
649}
650
651/* tty callbacks */
652
653static int open(struct tty_struct *tty, struct file *filp)
654{
655 struct slgt_info *info;
656 int retval, line;
657 unsigned long flags;
658
659 line = tty->index;
660 if ((line < 0) || (line >= slgt_device_count)) {
661 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
662 return -ENODEV;
663 }
664
665 info = slgt_device_list;
666 while(info && info->line != line)
667 info = info->next_device;
668 if (sanity_check(info, tty->name, "open"))
669 return -ENODEV;
670 if (info->init_error) {
671 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
672 return -ENODEV;
673 }
674
675 tty->driver_data = info;
676 info->tty = tty;
677
678 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
679
680 /* If port is closing, signal caller to try again */
681 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
682 if (info->flags & ASYNC_CLOSING)
683 interruptible_sleep_on(&info->close_wait);
684 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
685 -EAGAIN : -ERESTARTSYS);
686 goto cleanup;
687 }
688
689 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
690
691 spin_lock_irqsave(&info->netlock, flags);
692 if (info->netcount) {
693 retval = -EBUSY;
694 spin_unlock_irqrestore(&info->netlock, flags);
695 goto cleanup;
696 }
697 info->count++;
698 spin_unlock_irqrestore(&info->netlock, flags);
699
700 if (info->count == 1) {
701 /* 1st open on this device, init hardware */
702 retval = startup(info);
703 if (retval < 0)
704 goto cleanup;
705 }
706
707 retval = block_til_ready(tty, filp, info);
708 if (retval) {
709 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
710 goto cleanup;
711 }
712
713 retval = 0;
714
715cleanup:
716 if (retval) {
717 if (tty->count == 1)
718 info->tty = NULL; /* tty layer will release tty struct */
719 if(info->count)
720 info->count--;
721 }
722
723 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
724 return retval;
725}
726
727static void close(struct tty_struct *tty, struct file *filp)
728{
729 struct slgt_info *info = tty->driver_data;
730
731 if (sanity_check(info, tty->name, "close"))
732 return;
733 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
734
735 if (!info->count)
736 return;
737
738 if (tty_hung_up_p(filp))
739 goto cleanup;
740
741 if ((tty->count == 1) && (info->count != 1)) {
742 /*
743 * tty->count is 1 and the tty structure will be freed.
744 * info->count should be one in this case.
745 * if it's not, correct it so that the port is shutdown.
746 */
747 DBGERR(("%s close: bad refcount; tty->count=1, "
748 "info->count=%d\n", info->device_name, info->count));
749 info->count = 1;
750 }
751
752 info->count--;
753
754 /* if at least one open remaining, leave hardware active */
755 if (info->count)
756 goto cleanup;
757
758 info->flags |= ASYNC_CLOSING;
759
760 /* set tty->closing to notify line discipline to
761 * only process XON/XOFF characters. Only the N_TTY
762 * discipline appears to use this (ppp does not).
763 */
764 tty->closing = 1;
765
766 /* wait for transmit data to clear all layers */
767
768 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
769 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
770 tty_wait_until_sent(tty, info->closing_wait);
771 }
772
773 if (info->flags & ASYNC_INITIALIZED)
774 wait_until_sent(tty, info->timeout);
775 if (tty->driver->flush_buffer)
776 tty->driver->flush_buffer(tty);
777 tty_ldisc_flush(tty);
778
779 shutdown(info);
780
781 tty->closing = 0;
782 info->tty = NULL;
783
784 if (info->blocked_open) {
785 if (info->close_delay) {
786 msleep_interruptible(jiffies_to_msecs(info->close_delay));
787 }
788 wake_up_interruptible(&info->open_wait);
789 }
790
791 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
792
793 wake_up_interruptible(&info->close_wait);
794
795cleanup:
796 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
797}
798
799static void hangup(struct tty_struct *tty)
800{
801 struct slgt_info *info = tty->driver_data;
802
803 if (sanity_check(info, tty->name, "hangup"))
804 return;
805 DBGINFO(("%s hangup\n", info->device_name));
806
807 flush_buffer(tty);
808 shutdown(info);
809
810 info->count = 0;
811 info->flags &= ~ASYNC_NORMAL_ACTIVE;
812 info->tty = NULL;
813
814 wake_up_interruptible(&info->open_wait);
815}
816
817static void set_termios(struct tty_struct *tty, struct termios *old_termios)
818{
819 struct slgt_info *info = tty->driver_data;
820 unsigned long flags;
821
822 DBGINFO(("%s set_termios\n", tty->driver->name));
823
824 /* just return if nothing has changed */
825 if ((tty->termios->c_cflag == old_termios->c_cflag)
826 && (RELEVANT_IFLAG(tty->termios->c_iflag)
827 == RELEVANT_IFLAG(old_termios->c_iflag)))
828 return;
829
830 change_params(info);
831
832 /* Handle transition to B0 status */
833 if (old_termios->c_cflag & CBAUD &&
834 !(tty->termios->c_cflag & CBAUD)) {
835 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
836 spin_lock_irqsave(&info->lock,flags);
837 set_signals(info);
838 spin_unlock_irqrestore(&info->lock,flags);
839 }
840
841 /* Handle transition away from B0 status */
842 if (!(old_termios->c_cflag & CBAUD) &&
843 tty->termios->c_cflag & CBAUD) {
844 info->signals |= SerialSignal_DTR;
845 if (!(tty->termios->c_cflag & CRTSCTS) ||
846 !test_bit(TTY_THROTTLED, &tty->flags)) {
847 info->signals |= SerialSignal_RTS;
848 }
849 spin_lock_irqsave(&info->lock,flags);
850 set_signals(info);
851 spin_unlock_irqrestore(&info->lock,flags);
852 }
853
854 /* Handle turning off CRTSCTS */
855 if (old_termios->c_cflag & CRTSCTS &&
856 !(tty->termios->c_cflag & CRTSCTS)) {
857 tty->hw_stopped = 0;
858 tx_release(tty);
859 }
860}
861
862static int write(struct tty_struct *tty,
863 const unsigned char *buf, int count)
864{
865 int ret = 0;
866 struct slgt_info *info = tty->driver_data;
867 unsigned long flags;
868
869 if (sanity_check(info, tty->name, "write"))
870 goto cleanup;
871 DBGINFO(("%s write count=%d\n", info->device_name, count));
872
873 if (!tty || !info->tx_buf)
874 goto cleanup;
875
876 if (count > info->max_frame_size) {
877 ret = -EIO;
878 goto cleanup;
879 }
880
881 if (!count)
882 goto cleanup;
883
884 if (info->params.mode == MGSL_MODE_RAW) {
885 unsigned int bufs_needed = (count/DMABUFSIZE);
886 unsigned int bufs_free = free_tbuf_count(info);
887 if (count % DMABUFSIZE)
888 ++bufs_needed;
889 if (bufs_needed > bufs_free)
890 goto cleanup;
891 } else {
892 if (info->tx_active)
893 goto cleanup;
894 if (info->tx_count) {
895 /* send accumulated data from send_char() calls */
896 /* as frame and wait before accepting more data. */
897 tx_load(info, info->tx_buf, info->tx_count);
898 goto start;
899 }
900 }
901
902 ret = info->tx_count = count;
903 tx_load(info, buf, count);
904 goto start;
905
906start:
907 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
908 spin_lock_irqsave(&info->lock,flags);
909 if (!info->tx_active)
910 tx_start(info);
911 spin_unlock_irqrestore(&info->lock,flags);
912 }
913
914cleanup:
915 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
916 return ret;
917}
918
919static void put_char(struct tty_struct *tty, unsigned char ch)
920{
921 struct slgt_info *info = tty->driver_data;
922 unsigned long flags;
923
924 if (sanity_check(info, tty->name, "put_char"))
925 return;
926 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
927 if (!tty || !info->tx_buf)
928 return;
929 spin_lock_irqsave(&info->lock,flags);
930 if (!info->tx_active && (info->tx_count < info->max_frame_size))
931 info->tx_buf[info->tx_count++] = ch;
932 spin_unlock_irqrestore(&info->lock,flags);
933}
934
935static void send_xchar(struct tty_struct *tty, char ch)
936{
937 struct slgt_info *info = tty->driver_data;
938 unsigned long flags;
939
940 if (sanity_check(info, tty->name, "send_xchar"))
941 return;
942 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
943 info->x_char = ch;
944 if (ch) {
945 spin_lock_irqsave(&info->lock,flags);
946 if (!info->tx_enabled)
947 tx_start(info);
948 spin_unlock_irqrestore(&info->lock,flags);
949 }
950}
951
952static void wait_until_sent(struct tty_struct *tty, int timeout)
953{
954 struct slgt_info *info = tty->driver_data;
955 unsigned long orig_jiffies, char_time;
956
957 if (!info )
958 return;
959 if (sanity_check(info, tty->name, "wait_until_sent"))
960 return;
961 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
962 if (!(info->flags & ASYNC_INITIALIZED))
963 goto exit;
964
965 orig_jiffies = jiffies;
966
967 /* Set check interval to 1/5 of estimated time to
968 * send a character, and make it at least 1. The check
969 * interval should also be less than the timeout.
970 * Note: use tight timings here to satisfy the NIST-PCTS.
971 */
972
973 if (info->params.data_rate) {
974 char_time = info->timeout/(32 * 5);
975 if (!char_time)
976 char_time++;
977 } else
978 char_time = 1;
979
980 if (timeout)
981 char_time = min_t(unsigned long, char_time, timeout);
982
983 while (info->tx_active) {
984 msleep_interruptible(jiffies_to_msecs(char_time));
985 if (signal_pending(current))
986 break;
987 if (timeout && time_after(jiffies, orig_jiffies + timeout))
988 break;
989 }
990
991exit:
992 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
993}
994
995static int write_room(struct tty_struct *tty)
996{
997 struct slgt_info *info = tty->driver_data;
998 int ret;
999
1000 if (sanity_check(info, tty->name, "write_room"))
1001 return 0;
1002 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1003 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
1004 return ret;
1005}
1006
1007static void flush_chars(struct tty_struct *tty)
1008{
1009 struct slgt_info *info = tty->driver_data;
1010 unsigned long flags;
1011
1012 if (sanity_check(info, tty->name, "flush_chars"))
1013 return;
1014 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1015
1016 if (info->tx_count <= 0 || tty->stopped ||
1017 tty->hw_stopped || !info->tx_buf)
1018 return;
1019
1020 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1021
1022 spin_lock_irqsave(&info->lock,flags);
1023 if (!info->tx_active && info->tx_count) {
1024 tx_load(info, info->tx_buf,info->tx_count);
1025 tx_start(info);
1026 }
1027 spin_unlock_irqrestore(&info->lock,flags);
1028}
1029
1030static void flush_buffer(struct tty_struct *tty)
1031{
1032 struct slgt_info *info = tty->driver_data;
1033 unsigned long flags;
1034
1035 if (sanity_check(info, tty->name, "flush_buffer"))
1036 return;
1037 DBGINFO(("%s flush_buffer\n", info->device_name));
1038
1039 spin_lock_irqsave(&info->lock,flags);
1040 if (!info->tx_active)
1041 info->tx_count = 0;
1042 spin_unlock_irqrestore(&info->lock,flags);
1043
1044 wake_up_interruptible(&tty->write_wait);
1045 tty_wakeup(tty);
1046}
1047
1048/*
1049 * throttle (stop) transmitter
1050 */
1051static void tx_hold(struct tty_struct *tty)
1052{
1053 struct slgt_info *info = tty->driver_data;
1054 unsigned long flags;
1055
1056 if (sanity_check(info, tty->name, "tx_hold"))
1057 return;
1058 DBGINFO(("%s tx_hold\n", info->device_name));
1059 spin_lock_irqsave(&info->lock,flags);
1060 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1061 tx_stop(info);
1062 spin_unlock_irqrestore(&info->lock,flags);
1063}
1064
1065/*
1066 * release (start) transmitter
1067 */
1068static void tx_release(struct tty_struct *tty)
1069{
1070 struct slgt_info *info = tty->driver_data;
1071 unsigned long flags;
1072
1073 if (sanity_check(info, tty->name, "tx_release"))
1074 return;
1075 DBGINFO(("%s tx_release\n", info->device_name));
1076 spin_lock_irqsave(&info->lock,flags);
1077 if (!info->tx_active && info->tx_count) {
1078 tx_load(info, info->tx_buf, info->tx_count);
1079 tx_start(info);
1080 }
1081 spin_unlock_irqrestore(&info->lock,flags);
1082}
1083
1084/*
1085 * Service an IOCTL request
1086 *
1087 * Arguments
1088 *
1089 * tty pointer to tty instance data
1090 * file pointer to associated file object for device
1091 * cmd IOCTL command code
1092 * arg command argument/context
1093 *
1094 * Return 0 if success, otherwise error code
1095 */
1096static int ioctl(struct tty_struct *tty, struct file *file,
1097 unsigned int cmd, unsigned long arg)
1098{
1099 struct slgt_info *info = tty->driver_data;
1100 struct mgsl_icount cnow; /* kernel counter temps */
1101 struct serial_icounter_struct __user *p_cuser; /* user space */
1102 unsigned long flags;
1103 void __user *argp = (void __user *)arg;
1104
1105 if (sanity_check(info, tty->name, "ioctl"))
1106 return -ENODEV;
1107 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1108
1109 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1110 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1111 if (tty->flags & (1 << TTY_IO_ERROR))
1112 return -EIO;
1113 }
1114
1115 switch (cmd) {
1116 case MGSL_IOCGPARAMS:
1117 return get_params(info, argp);
1118 case MGSL_IOCSPARAMS:
1119 return set_params(info, argp);
1120 case MGSL_IOCGTXIDLE:
1121 return get_txidle(info, argp);
1122 case MGSL_IOCSTXIDLE:
1123 return set_txidle(info, (int)arg);
1124 case MGSL_IOCTXENABLE:
1125 return tx_enable(info, (int)arg);
1126 case MGSL_IOCRXENABLE:
1127 return rx_enable(info, (int)arg);
1128 case MGSL_IOCTXABORT:
1129 return tx_abort(info);
1130 case MGSL_IOCGSTATS:
1131 return get_stats(info, argp);
1132 case MGSL_IOCWAITEVENT:
1133 return wait_mgsl_event(info, argp);
1134 case TIOCMIWAIT:
1135 return modem_input_wait(info,(int)arg);
1136 case MGSL_IOCGIF:
1137 return get_interface(info, argp);
1138 case MGSL_IOCSIF:
1139 return set_interface(info,(int)arg);
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame^]1140 case MGSL_IOCSGPIO:
1141 return set_gpio(info, argp);
1142 case MGSL_IOCGGPIO:
1143 return get_gpio(info, argp);
1144 case MGSL_IOCWAITGPIO:
1145 return wait_gpio(info, argp);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1146 case TIOCGICOUNT:
1147 spin_lock_irqsave(&info->lock,flags);
1148 cnow = info->icount;
1149 spin_unlock_irqrestore(&info->lock,flags);
1150 p_cuser = argp;
1151 if (put_user(cnow.cts, &p_cuser->cts) ||
1152 put_user(cnow.dsr, &p_cuser->dsr) ||
1153 put_user(cnow.rng, &p_cuser->rng) ||
1154 put_user(cnow.dcd, &p_cuser->dcd) ||
1155 put_user(cnow.rx, &p_cuser->rx) ||
1156 put_user(cnow.tx, &p_cuser->tx) ||
1157 put_user(cnow.frame, &p_cuser->frame) ||
1158 put_user(cnow.overrun, &p_cuser->overrun) ||
1159 put_user(cnow.parity, &p_cuser->parity) ||
1160 put_user(cnow.brk, &p_cuser->brk) ||
1161 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1162 return -EFAULT;
1163 return 0;
1164 default:
1165 return -ENOIOCTLCMD;
1166 }
1167 return 0;
1168}
1169
1170/*
1171 * proc fs support
1172 */
1173static inline int line_info(char *buf, struct slgt_info *info)
1174{
1175 char stat_buf[30];
1176 int ret;
1177 unsigned long flags;
1178
1179 ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1180 info->device_name, info->phys_reg_addr,
1181 info->irq_level, info->max_frame_size);
1182
1183 /* output current serial signal states */
1184 spin_lock_irqsave(&info->lock,flags);
1185 get_signals(info);
1186 spin_unlock_irqrestore(&info->lock,flags);
1187
1188 stat_buf[0] = 0;
1189 stat_buf[1] = 0;
1190 if (info->signals & SerialSignal_RTS)
1191 strcat(stat_buf, "|RTS");
1192 if (info->signals & SerialSignal_CTS)
1193 strcat(stat_buf, "|CTS");
1194 if (info->signals & SerialSignal_DTR)
1195 strcat(stat_buf, "|DTR");
1196 if (info->signals & SerialSignal_DSR)
1197 strcat(stat_buf, "|DSR");
1198 if (info->signals & SerialSignal_DCD)
1199 strcat(stat_buf, "|CD");
1200 if (info->signals & SerialSignal_RI)
1201 strcat(stat_buf, "|RI");
1202
1203 if (info->params.mode != MGSL_MODE_ASYNC) {
1204 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1205 info->icount.txok, info->icount.rxok);
1206 if (info->icount.txunder)
1207 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1208 if (info->icount.txabort)
1209 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1210 if (info->icount.rxshort)
1211 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1212 if (info->icount.rxlong)
1213 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1214 if (info->icount.rxover)
1215 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1216 if (info->icount.rxcrc)
1217 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1218 } else {
1219 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1220 info->icount.tx, info->icount.rx);
1221 if (info->icount.frame)
1222 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1223 if (info->icount.parity)
1224 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1225 if (info->icount.brk)
1226 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1227 if (info->icount.overrun)
1228 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1229 }
1230
1231 /* Append serial signal status to end */
1232 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1233
1234 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1235 info->tx_active,info->bh_requested,info->bh_running,
1236 info->pending_bh);
1237
1238 return ret;
1239}
1240
1241/* Called to print information about devices
1242 */
1243static int read_proc(char *page, char **start, off_t off, int count,
1244 int *eof, void *data)
1245{
1246 int len = 0, l;
1247 off_t begin = 0;
1248 struct slgt_info *info;
1249
1250 len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1251
1252 info = slgt_device_list;
1253 while( info ) {
1254 l = line_info(page + len, info);
1255 len += l;
1256 if (len+begin > off+count)
1257 goto done;
1258 if (len+begin < off) {
1259 begin += len;
1260 len = 0;
1261 }
1262 info = info->next_device;
1263 }
1264
1265 *eof = 1;
1266done:
1267 if (off >= len+begin)
1268 return 0;
1269 *start = page + (off-begin);
1270 return ((count < begin+len-off) ? count : begin+len-off);
1271}
1272
1273/*
1274 * return count of bytes in transmit buffer
1275 */
1276static int chars_in_buffer(struct tty_struct *tty)
1277{
1278 struct slgt_info *info = tty->driver_data;
1279 if (sanity_check(info, tty->name, "chars_in_buffer"))
1280 return 0;
1281 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1282 return info->tx_count;
1283}
1284
1285/*
1286 * signal remote device to throttle send data (our receive data)
1287 */
1288static void throttle(struct tty_struct * tty)
1289{
1290 struct slgt_info *info = tty->driver_data;
1291 unsigned long flags;
1292
1293 if (sanity_check(info, tty->name, "throttle"))
1294 return;
1295 DBGINFO(("%s throttle\n", info->device_name));
1296 if (I_IXOFF(tty))
1297 send_xchar(tty, STOP_CHAR(tty));
1298 if (tty->termios->c_cflag & CRTSCTS) {
1299 spin_lock_irqsave(&info->lock,flags);
1300 info->signals &= ~SerialSignal_RTS;
1301 set_signals(info);
1302 spin_unlock_irqrestore(&info->lock,flags);
1303 }
1304}
1305
1306/*
1307 * signal remote device to stop throttling send data (our receive data)
1308 */
1309static void unthrottle(struct tty_struct * tty)
1310{
1311 struct slgt_info *info = tty->driver_data;
1312 unsigned long flags;
1313
1314 if (sanity_check(info, tty->name, "unthrottle"))
1315 return;
1316 DBGINFO(("%s unthrottle\n", info->device_name));
1317 if (I_IXOFF(tty)) {
1318 if (info->x_char)
1319 info->x_char = 0;
1320 else
1321 send_xchar(tty, START_CHAR(tty));
1322 }
1323 if (tty->termios->c_cflag & CRTSCTS) {
1324 spin_lock_irqsave(&info->lock,flags);
1325 info->signals |= SerialSignal_RTS;
1326 set_signals(info);
1327 spin_unlock_irqrestore(&info->lock,flags);
1328 }
1329}
1330
1331/*
1332 * set or clear transmit break condition
1333 * break_state -1=set break condition, 0=clear
1334 */
1335static void set_break(struct tty_struct *tty, int break_state)
1336{
1337 struct slgt_info *info = tty->driver_data;
1338 unsigned short value;
1339 unsigned long flags;
1340
1341 if (sanity_check(info, tty->name, "set_break"))
1342 return;
1343 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1344
1345 spin_lock_irqsave(&info->lock,flags);
1346 value = rd_reg16(info, TCR);
1347 if (break_state == -1)
1348 value |= BIT6;
1349 else
1350 value &= ~BIT6;
1351 wr_reg16(info, TCR, value);
1352 spin_unlock_irqrestore(&info->lock,flags);
1353}
1354
1355#ifdef CONFIG_HDLC
1356
1357/**
1358 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1359 * set encoding and frame check sequence (FCS) options
1360 *
1361 * dev pointer to network device structure
1362 * encoding serial encoding setting
1363 * parity FCS setting
1364 *
1365 * returns 0 if success, otherwise error code
1366 */
1367static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1368 unsigned short parity)
1369{
1370 struct slgt_info *info = dev_to_port(dev);
1371 unsigned char new_encoding;
1372 unsigned short new_crctype;
1373
1374 /* return error if TTY interface open */
1375 if (info->count)
1376 return -EBUSY;
1377
1378 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1379
1380 switch (encoding)
1381 {
1382 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1383 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1384 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1385 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1386 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1387 default: return -EINVAL;
1388 }
1389
1390 switch (parity)
1391 {
1392 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1393 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1394 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1395 default: return -EINVAL;
1396 }
1397
1398 info->params.encoding = new_encoding;
Alexey Dobriyan53b35312006-03-24 03:16:13 -0800[diff] [blame]1399 info->params.crc_type = new_crctype;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1400
1401 /* if network interface up, reprogram hardware */
1402 if (info->netcount)
1403 program_hw(info);
1404
1405 return 0;
1406}
1407
1408/**
1409 * called by generic HDLC layer to send frame
1410 *
1411 * skb socket buffer containing HDLC frame
1412 * dev pointer to network device structure
1413 *
1414 * returns 0 if success, otherwise error code
1415 */
1416static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1417{
1418 struct slgt_info *info = dev_to_port(dev);
1419 struct net_device_stats *stats = hdlc_stats(dev);
1420 unsigned long flags;
1421
1422 DBGINFO(("%s hdlc_xmit\n", dev->name));
1423
1424 /* stop sending until this frame completes */
1425 netif_stop_queue(dev);
1426
1427 /* copy data to device buffers */
1428 info->tx_count = skb->len;
1429 tx_load(info, skb->data, skb->len);
1430
1431 /* update network statistics */
1432 stats->tx_packets++;
1433 stats->tx_bytes += skb->len;
1434
1435 /* done with socket buffer, so free it */
1436 dev_kfree_skb(skb);
1437
1438 /* save start time for transmit timeout detection */
1439 dev->trans_start = jiffies;
1440
1441 /* start hardware transmitter if necessary */
1442 spin_lock_irqsave(&info->lock,flags);
1443 if (!info->tx_active)
1444 tx_start(info);
1445 spin_unlock_irqrestore(&info->lock,flags);
1446
1447 return 0;
1448}
1449
1450/**
1451 * called by network layer when interface enabled
1452 * claim resources and initialize hardware
1453 *
1454 * dev pointer to network device structure
1455 *
1456 * returns 0 if success, otherwise error code
1457 */
1458static int hdlcdev_open(struct net_device *dev)
1459{
1460 struct slgt_info *info = dev_to_port(dev);
1461 int rc;
1462 unsigned long flags;
1463
1464 DBGINFO(("%s hdlcdev_open\n", dev->name));
1465
1466 /* generic HDLC layer open processing */
1467 if ((rc = hdlc_open(dev)))
1468 return rc;
1469
1470 /* arbitrate between network and tty opens */
1471 spin_lock_irqsave(&info->netlock, flags);
1472 if (info->count != 0 || info->netcount != 0) {
1473 DBGINFO(("%s hdlc_open busy\n", dev->name));
1474 spin_unlock_irqrestore(&info->netlock, flags);
1475 return -EBUSY;
1476 }
1477 info->netcount=1;
1478 spin_unlock_irqrestore(&info->netlock, flags);
1479
1480 /* claim resources and init adapter */
1481 if ((rc = startup(info)) != 0) {
1482 spin_lock_irqsave(&info->netlock, flags);
1483 info->netcount=0;
1484 spin_unlock_irqrestore(&info->netlock, flags);
1485 return rc;
1486 }
1487
1488 /* assert DTR and RTS, apply hardware settings */
1489 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1490 program_hw(info);
1491
1492 /* enable network layer transmit */
1493 dev->trans_start = jiffies;
1494 netif_start_queue(dev);
1495
1496 /* inform generic HDLC layer of current DCD status */
1497 spin_lock_irqsave(&info->lock, flags);
1498 get_signals(info);
1499 spin_unlock_irqrestore(&info->lock, flags);
1500 hdlc_set_carrier(info->signals & SerialSignal_DCD, dev);
1501
1502 return 0;
1503}
1504
1505/**
1506 * called by network layer when interface is disabled
1507 * shutdown hardware and release resources
1508 *
1509 * dev pointer to network device structure
1510 *
1511 * returns 0 if success, otherwise error code
1512 */
1513static int hdlcdev_close(struct net_device *dev)
1514{
1515 struct slgt_info *info = dev_to_port(dev);
1516 unsigned long flags;
1517
1518 DBGINFO(("%s hdlcdev_close\n", dev->name));
1519
1520 netif_stop_queue(dev);
1521
1522 /* shutdown adapter and release resources */
1523 shutdown(info);
1524
1525 hdlc_close(dev);
1526
1527 spin_lock_irqsave(&info->netlock, flags);
1528 info->netcount=0;
1529 spin_unlock_irqrestore(&info->netlock, flags);
1530
1531 return 0;
1532}
1533
1534/**
1535 * called by network layer to process IOCTL call to network device
1536 *
1537 * dev pointer to network device structure
1538 * ifr pointer to network interface request structure
1539 * cmd IOCTL command code
1540 *
1541 * returns 0 if success, otherwise error code
1542 */
1543static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1544{
1545 const size_t size = sizeof(sync_serial_settings);
1546 sync_serial_settings new_line;
1547 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1548 struct slgt_info *info = dev_to_port(dev);
1549 unsigned int flags;
1550
1551 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1552
1553 /* return error if TTY interface open */
1554 if (info->count)
1555 return -EBUSY;
1556
1557 if (cmd != SIOCWANDEV)
1558 return hdlc_ioctl(dev, ifr, cmd);
1559
1560 switch(ifr->ifr_settings.type) {
1561 case IF_GET_IFACE: /* return current sync_serial_settings */
1562
1563 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1564 if (ifr->ifr_settings.size < size) {
1565 ifr->ifr_settings.size = size; /* data size wanted */
1566 return -ENOBUFS;
1567 }
1568
1569 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1570 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1571 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1572 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1573
1574 switch (flags){
1575 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1576 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1577 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1578 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1579 default: new_line.clock_type = CLOCK_DEFAULT;
1580 }
1581
1582 new_line.clock_rate = info->params.clock_speed;
1583 new_line.loopback = info->params.loopback ? 1:0;
1584
1585 if (copy_to_user(line, &new_line, size))
1586 return -EFAULT;
1587 return 0;
1588
1589 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1590
1591 if(!capable(CAP_NET_ADMIN))
1592 return -EPERM;
1593 if (copy_from_user(&new_line, line, size))
1594 return -EFAULT;
1595
1596 switch (new_line.clock_type)
1597 {
1598 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1599 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1600 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1601 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1602 case CLOCK_DEFAULT: flags = info->params.flags &
1603 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1604 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1605 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1606 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1607 default: return -EINVAL;
1608 }
1609
1610 if (new_line.loopback != 0 && new_line.loopback != 1)
1611 return -EINVAL;
1612
1613 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1614 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1615 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1616 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1617 info->params.flags |= flags;
1618
1619 info->params.loopback = new_line.loopback;
1620
1621 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1622 info->params.clock_speed = new_line.clock_rate;
1623 else
1624 info->params.clock_speed = 0;
1625
1626 /* if network interface up, reprogram hardware */
1627 if (info->netcount)
1628 program_hw(info);
1629 return 0;
1630
1631 default:
1632 return hdlc_ioctl(dev, ifr, cmd);
1633 }
1634}
1635
1636/**
1637 * called by network layer when transmit timeout is detected
1638 *
1639 * dev pointer to network device structure
1640 */
1641static void hdlcdev_tx_timeout(struct net_device *dev)
1642{
1643 struct slgt_info *info = dev_to_port(dev);
1644 struct net_device_stats *stats = hdlc_stats(dev);
1645 unsigned long flags;
1646
1647 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1648
1649 stats->tx_errors++;
1650 stats->tx_aborted_errors++;
1651
1652 spin_lock_irqsave(&info->lock,flags);
1653 tx_stop(info);
1654 spin_unlock_irqrestore(&info->lock,flags);
1655
1656 netif_wake_queue(dev);
1657}
1658
1659/**
1660 * called by device driver when transmit completes
1661 * reenable network layer transmit if stopped
1662 *
1663 * info pointer to device instance information
1664 */
1665static void hdlcdev_tx_done(struct slgt_info *info)
1666{
1667 if (netif_queue_stopped(info->netdev))
1668 netif_wake_queue(info->netdev);
1669}
1670
1671/**
1672 * called by device driver when frame received
1673 * pass frame to network layer
1674 *
1675 * info pointer to device instance information
1676 * buf pointer to buffer contianing frame data
1677 * size count of data bytes in buf
1678 */
1679static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1680{
1681 struct sk_buff *skb = dev_alloc_skb(size);
1682 struct net_device *dev = info->netdev;
1683 struct net_device_stats *stats = hdlc_stats(dev);
1684
1685 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1686
1687 if (skb == NULL) {
1688 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1689 stats->rx_dropped++;
1690 return;
1691 }
1692
1693 memcpy(skb_put(skb, size),buf,size);
1694
1695 skb->protocol = hdlc_type_trans(skb, info->netdev);
1696
1697 stats->rx_packets++;
1698 stats->rx_bytes += size;
1699
1700 netif_rx(skb);
1701
1702 info->netdev->last_rx = jiffies;
1703}
1704
1705/**
1706 * called by device driver when adding device instance
1707 * do generic HDLC initialization
1708 *
1709 * info pointer to device instance information
1710 *
1711 * returns 0 if success, otherwise error code
1712 */
1713static int hdlcdev_init(struct slgt_info *info)
1714{
1715 int rc;
1716 struct net_device *dev;
1717 hdlc_device *hdlc;
1718
1719 /* allocate and initialize network and HDLC layer objects */
1720
1721 if (!(dev = alloc_hdlcdev(info))) {
1722 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1723 return -ENOMEM;
1724 }
1725
1726 /* for network layer reporting purposes only */
1727 dev->mem_start = info->phys_reg_addr;
1728 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1729 dev->irq = info->irq_level;
1730
1731 /* network layer callbacks and settings */
1732 dev->do_ioctl = hdlcdev_ioctl;
1733 dev->open = hdlcdev_open;
1734 dev->stop = hdlcdev_close;
1735 dev->tx_timeout = hdlcdev_tx_timeout;
1736 dev->watchdog_timeo = 10*HZ;
1737 dev->tx_queue_len = 50;
1738
1739 /* generic HDLC layer callbacks and settings */
1740 hdlc = dev_to_hdlc(dev);
1741 hdlc->attach = hdlcdev_attach;
1742 hdlc->xmit = hdlcdev_xmit;
1743
1744 /* register objects with HDLC layer */
1745 if ((rc = register_hdlc_device(dev))) {
1746 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1747 free_netdev(dev);
1748 return rc;
1749 }
1750
1751 info->netdev = dev;
1752 return 0;
1753}
1754
1755/**
1756 * called by device driver when removing device instance
1757 * do generic HDLC cleanup
1758 *
1759 * info pointer to device instance information
1760 */
1761static void hdlcdev_exit(struct slgt_info *info)
1762{
1763 unregister_hdlc_device(info->netdev);
1764 free_netdev(info->netdev);
1765 info->netdev = NULL;
1766}
1767
1768#endif /* ifdef CONFIG_HDLC */
1769
1770/*
1771 * get async data from rx DMA buffers
1772 */
1773static void rx_async(struct slgt_info *info)
1774{
1775 struct tty_struct *tty = info->tty;
1776 struct mgsl_icount *icount = &info->icount;
1777 unsigned int start, end;
1778 unsigned char *p;
1779 unsigned char status;
1780 struct slgt_desc *bufs = info->rbufs;
1781 int i, count;
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]1782 int chars = 0;
1783 int stat;
1784 unsigned char ch;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1785
1786 start = end = info->rbuf_current;
1787
1788 while(desc_complete(bufs[end])) {
1789 count = desc_count(bufs[end]) - info->rbuf_index;
1790 p = bufs[end].buf + info->rbuf_index;
1791
1792 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1793 DBGDATA(info, p, count, "rx");
1794
1795 for(i=0 ; i < count; i+=2, p+=2) {
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]1796 if (tty && chars) {
1797 tty_flip_buffer_push(tty);
1798 chars = 0;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1799 }
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]1800 ch = *p;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1801 icount->rx++;
1802
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]1803 stat = 0;
1804
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1805 if ((status = *(p+1) & (BIT9 + BIT8))) {
1806 if (status & BIT9)
1807 icount->parity++;
1808 else if (status & BIT8)
1809 icount->frame++;
1810 /* discard char if tty control flags say so */
1811 if (status & info->ignore_status_mask)
1812 continue;
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]1813 if (status & BIT9)
1814 stat = TTY_PARITY;
1815 else if (status & BIT8)
1816 stat = TTY_FRAME;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1817 }
1818 if (tty) {
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]1819 tty_insert_flip_char(tty, ch, stat);
1820 chars++;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1821 }
1822 }
1823
1824 if (i < count) {
1825 /* receive buffer not completed */
1826 info->rbuf_index += i;
1827 info->rx_timer.expires = jiffies + 1;
1828 add_timer(&info->rx_timer);
1829 break;
1830 }
1831
1832 info->rbuf_index = 0;
1833 free_rbufs(info, end, end);
1834
1835 if (++end == info->rbuf_count)
1836 end = 0;
1837
1838 /* if entire list searched then no frame available */
1839 if (end == start)
1840 break;
1841 }
1842
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]1843 if (tty && chars)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1844 tty_flip_buffer_push(tty);
1845}
1846
1847/*
1848 * return next bottom half action to perform
1849 */
1850static int bh_action(struct slgt_info *info)
1851{
1852 unsigned long flags;
1853 int rc;
1854
1855 spin_lock_irqsave(&info->lock,flags);
1856
1857 if (info->pending_bh & BH_RECEIVE) {
1858 info->pending_bh &= ~BH_RECEIVE;
1859 rc = BH_RECEIVE;
1860 } else if (info->pending_bh & BH_TRANSMIT) {
1861 info->pending_bh &= ~BH_TRANSMIT;
1862 rc = BH_TRANSMIT;
1863 } else if (info->pending_bh & BH_STATUS) {
1864 info->pending_bh &= ~BH_STATUS;
1865 rc = BH_STATUS;
1866 } else {
1867 /* Mark BH routine as complete */
1868 info->bh_running = 0;
1869 info->bh_requested = 0;
1870 rc = 0;
1871 }
1872
1873 spin_unlock_irqrestore(&info->lock,flags);
1874
1875 return rc;
1876}
1877
1878/*
1879 * perform bottom half processing
1880 */
1881static void bh_handler(void* context)
1882{
1883 struct slgt_info *info = context;
1884 int action;
1885
1886 if (!info)
1887 return;
1888 info->bh_running = 1;
1889
1890 while((action = bh_action(info))) {
1891 switch (action) {
1892 case BH_RECEIVE:
1893 DBGBH(("%s bh receive\n", info->device_name));
1894 switch(info->params.mode) {
1895 case MGSL_MODE_ASYNC:
1896 rx_async(info);
1897 break;
1898 case MGSL_MODE_HDLC:
1899 while(rx_get_frame(info));
1900 break;
1901 case MGSL_MODE_RAW:
1902 while(rx_get_buf(info));
1903 break;
1904 }
1905 /* restart receiver if rx DMA buffers exhausted */
1906 if (info->rx_restart)
1907 rx_start(info);
1908 break;
1909 case BH_TRANSMIT:
1910 bh_transmit(info);
1911 break;
1912 case BH_STATUS:
1913 DBGBH(("%s bh status\n", info->device_name));
1914 info->ri_chkcount = 0;
1915 info->dsr_chkcount = 0;
1916 info->dcd_chkcount = 0;
1917 info->cts_chkcount = 0;
1918 break;
1919 default:
1920 DBGBH(("%s unknown action\n", info->device_name));
1921 break;
1922 }
1923 }
1924 DBGBH(("%s bh_handler exit\n", info->device_name));
1925}
1926
1927static void bh_transmit(struct slgt_info *info)
1928{
1929 struct tty_struct *tty = info->tty;
1930
1931 DBGBH(("%s bh_transmit\n", info->device_name));
1932 if (tty) {
1933 tty_wakeup(tty);
1934 wake_up_interruptible(&tty->write_wait);
1935 }
1936}
1937
1938static void dsr_change(struct slgt_info *info)
1939{
1940 get_signals(info);
1941 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1942 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1943 slgt_irq_off(info, IRQ_DSR);
1944 return;
1945 }
1946 info->icount.dsr++;
1947 if (info->signals & SerialSignal_DSR)
1948 info->input_signal_events.dsr_up++;
1949 else
1950 info->input_signal_events.dsr_down++;
1951 wake_up_interruptible(&info->status_event_wait_q);
1952 wake_up_interruptible(&info->event_wait_q);
1953 info->pending_bh |= BH_STATUS;
1954}
1955
1956static void cts_change(struct slgt_info *info)
1957{
1958 get_signals(info);
1959 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1960 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1961 slgt_irq_off(info, IRQ_CTS);
1962 return;
1963 }
1964 info->icount.cts++;
1965 if (info->signals & SerialSignal_CTS)
1966 info->input_signal_events.cts_up++;
1967 else
1968 info->input_signal_events.cts_down++;
1969 wake_up_interruptible(&info->status_event_wait_q);
1970 wake_up_interruptible(&info->event_wait_q);
1971 info->pending_bh |= BH_STATUS;
1972
1973 if (info->flags & ASYNC_CTS_FLOW) {
1974 if (info->tty) {
1975 if (info->tty->hw_stopped) {
1976 if (info->signals & SerialSignal_CTS) {
1977 info->tty->hw_stopped = 0;
1978 info->pending_bh |= BH_TRANSMIT;
1979 return;
1980 }
1981 } else {
1982 if (!(info->signals & SerialSignal_CTS))
1983 info->tty->hw_stopped = 1;
1984 }
1985 }
1986 }
1987}
1988
1989static void dcd_change(struct slgt_info *info)
1990{
1991 get_signals(info);
1992 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1993 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1994 slgt_irq_off(info, IRQ_DCD);
1995 return;
1996 }
1997 info->icount.dcd++;
1998 if (info->signals & SerialSignal_DCD) {
1999 info->input_signal_events.dcd_up++;
2000 } else {
2001 info->input_signal_events.dcd_down++;
2002 }
2003#ifdef CONFIG_HDLC
2004 if (info->netcount)
2005 hdlc_set_carrier(info->signals & SerialSignal_DCD, info->netdev);
2006#endif
2007 wake_up_interruptible(&info->status_event_wait_q);
2008 wake_up_interruptible(&info->event_wait_q);
2009 info->pending_bh |= BH_STATUS;
2010
2011 if (info->flags & ASYNC_CHECK_CD) {
2012 if (info->signals & SerialSignal_DCD)
2013 wake_up_interruptible(&info->open_wait);
2014 else {
2015 if (info->tty)
2016 tty_hangup(info->tty);
2017 }
2018 }
2019}
2020
2021static void ri_change(struct slgt_info *info)
2022{
2023 get_signals(info);
2024 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2025 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2026 slgt_irq_off(info, IRQ_RI);
2027 return;
2028 }
2029 info->icount.dcd++;
2030 if (info->signals & SerialSignal_RI) {
2031 info->input_signal_events.ri_up++;
2032 } else {
2033 info->input_signal_events.ri_down++;
2034 }
2035 wake_up_interruptible(&info->status_event_wait_q);
2036 wake_up_interruptible(&info->event_wait_q);
2037 info->pending_bh |= BH_STATUS;
2038}
2039
2040static void isr_serial(struct slgt_info *info)
2041{
2042 unsigned short status = rd_reg16(info, SSR);
2043
2044 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2045
2046 wr_reg16(info, SSR, status); /* clear pending */
2047
2048 info->irq_occurred = 1;
2049
2050 if (info->params.mode == MGSL_MODE_ASYNC) {
2051 if (status & IRQ_TXIDLE) {
2052 if (info->tx_count)
2053 isr_txeom(info, status);
2054 }
2055 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2056 info->icount.brk++;
2057 /* process break detection if tty control allows */
2058 if (info->tty) {
2059 if (!(status & info->ignore_status_mask)) {
2060 if (info->read_status_mask & MASK_BREAK) {
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]2061 tty_insert_flip_char(info->tty, 0, TTY_BREAK);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2062 if (info->flags & ASYNC_SAK)
2063 do_SAK(info->tty);
2064 }
2065 }
2066 }
2067 }
2068 } else {
2069 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2070 isr_txeom(info, status);
2071
2072 if (status & IRQ_RXIDLE) {
2073 if (status & RXIDLE)
2074 info->icount.rxidle++;
2075 else
2076 info->icount.exithunt++;
2077 wake_up_interruptible(&info->event_wait_q);
2078 }
2079
2080 if (status & IRQ_RXOVER)
2081 rx_start(info);
2082 }
2083
2084 if (status & IRQ_DSR)
2085 dsr_change(info);
2086 if (status & IRQ_CTS)
2087 cts_change(info);
2088 if (status & IRQ_DCD)
2089 dcd_change(info);
2090 if (status & IRQ_RI)
2091 ri_change(info);
2092}
2093
2094static void isr_rdma(struct slgt_info *info)
2095{
2096 unsigned int status = rd_reg32(info, RDCSR);
2097
2098 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2099
2100 /* RDCSR (rx DMA control/status)
2101 *
2102 * 31..07 reserved
2103 * 06 save status byte to DMA buffer
2104 * 05 error
2105 * 04 eol (end of list)
2106 * 03 eob (end of buffer)
2107 * 02 IRQ enable
2108 * 01 reset
2109 * 00 enable
2110 */
2111 wr_reg32(info, RDCSR, status); /* clear pending */
2112
2113 if (status & (BIT5 + BIT4)) {
2114 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2115 info->rx_restart = 1;
2116 }
2117 info->pending_bh |= BH_RECEIVE;
2118}
2119
2120static void isr_tdma(struct slgt_info *info)
2121{
2122 unsigned int status = rd_reg32(info, TDCSR);
2123
2124 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2125
2126 /* TDCSR (tx DMA control/status)
2127 *
2128 * 31..06 reserved
2129 * 05 error
2130 * 04 eol (end of list)
2131 * 03 eob (end of buffer)
2132 * 02 IRQ enable
2133 * 01 reset
2134 * 00 enable
2135 */
2136 wr_reg32(info, TDCSR, status); /* clear pending */
2137
2138 if (status & (BIT5 + BIT4 + BIT3)) {
2139 // another transmit buffer has completed
2140 // run bottom half to get more send data from user
2141 info->pending_bh |= BH_TRANSMIT;
2142 }
2143}
2144
2145static void isr_txeom(struct slgt_info *info, unsigned short status)
2146{
2147 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2148
2149 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2150 tdma_reset(info);
2151 reset_tbufs(info);
2152 if (status & IRQ_TXUNDER) {
2153 unsigned short val = rd_reg16(info, TCR);
2154 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2155 wr_reg16(info, TCR, val); /* clear reset bit */
2156 }
2157
2158 if (info->tx_active) {
2159 if (info->params.mode != MGSL_MODE_ASYNC) {
2160 if (status & IRQ_TXUNDER)
2161 info->icount.txunder++;
2162 else if (status & IRQ_TXIDLE)
2163 info->icount.txok++;
2164 }
2165
2166 info->tx_active = 0;
2167 info->tx_count = 0;
2168
2169 del_timer(&info->tx_timer);
2170
2171 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2172 info->signals &= ~SerialSignal_RTS;
2173 info->drop_rts_on_tx_done = 0;
2174 set_signals(info);
2175 }
2176
2177#ifdef CONFIG_HDLC
2178 if (info->netcount)
2179 hdlcdev_tx_done(info);
2180 else
2181#endif
2182 {
2183 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2184 tx_stop(info);
2185 return;
2186 }
2187 info->pending_bh |= BH_TRANSMIT;
2188 }
2189 }
2190}
2191
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame^]2192static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2193{
2194 struct cond_wait *w, *prev;
2195
2196 /* wake processes waiting for specific transitions */
2197 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2198 if (w->data & changed) {
2199 w->data = state;
2200 wake_up_interruptible(&w->q);
2201 if (prev != NULL)
2202 prev->next = w->next;
2203 else
2204 info->gpio_wait_q = w->next;
2205 } else
2206 prev = w;
2207 }
2208}
2209
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2210/* interrupt service routine
2211 *
2212 * irq interrupt number
2213 * dev_id device ID supplied during interrupt registration
2214 * regs interrupted processor context
2215 */
2216static irqreturn_t slgt_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2217{
2218 struct slgt_info *info;
2219 unsigned int gsr;
2220 unsigned int i;
2221
2222 DBGISR(("slgt_interrupt irq=%d entry\n", irq));
2223
2224 info = dev_id;
2225 if (!info)
2226 return IRQ_NONE;
2227
2228 spin_lock(&info->lock);
2229
2230 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2231 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2232 info->irq_occurred = 1;
2233 for(i=0; i < info->port_count ; i++) {
2234 if (info->port_array[i] == NULL)
2235 continue;
2236 if (gsr & (BIT8 << i))
2237 isr_serial(info->port_array[i]);
2238 if (gsr & (BIT16 << (i*2)))
2239 isr_rdma(info->port_array[i]);
2240 if (gsr & (BIT17 << (i*2)))
2241 isr_tdma(info->port_array[i]);
2242 }
2243 }
2244
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame^]2245 if (info->gpio_present) {
2246 unsigned int state;
2247 unsigned int changed;
2248 while ((changed = rd_reg32(info, IOSR)) != 0) {
2249 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2250 /* read latched state of GPIO signals */
2251 state = rd_reg32(info, IOVR);
2252 /* clear pending GPIO interrupt bits */
2253 wr_reg32(info, IOSR, changed);
2254 for (i=0 ; i < info->port_count ; i++) {
2255 if (info->port_array[i] != NULL)
2256 isr_gpio(info->port_array[i], changed, state);
2257 }
2258 }
2259 }
2260
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2261 for(i=0; i < info->port_count ; i++) {
2262 struct slgt_info *port = info->port_array[i];
2263
2264 if (port && (port->count || port->netcount) &&
2265 port->pending_bh && !port->bh_running &&
2266 !port->bh_requested) {
2267 DBGISR(("%s bh queued\n", port->device_name));
2268 schedule_work(&port->task);
2269 port->bh_requested = 1;
2270 }
2271 }
2272
2273 spin_unlock(&info->lock);
2274
2275 DBGISR(("slgt_interrupt irq=%d exit\n", irq));
2276 return IRQ_HANDLED;
2277}
2278
2279static int startup(struct slgt_info *info)
2280{
2281 DBGINFO(("%s startup\n", info->device_name));
2282
2283 if (info->flags & ASYNC_INITIALIZED)
2284 return 0;
2285
2286 if (!info->tx_buf) {
2287 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2288 if (!info->tx_buf) {
2289 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2290 return -ENOMEM;
2291 }
2292 }
2293
2294 info->pending_bh = 0;
2295
2296 memset(&info->icount, 0, sizeof(info->icount));
2297
2298 /* program hardware for current parameters */
2299 change_params(info);
2300
2301 if (info->tty)
2302 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2303
2304 info->flags |= ASYNC_INITIALIZED;
2305
2306 return 0;
2307}
2308
2309/*
2310 * called by close() and hangup() to shutdown hardware
2311 */
2312static void shutdown(struct slgt_info *info)
2313{
2314 unsigned long flags;
2315
2316 if (!(info->flags & ASYNC_INITIALIZED))
2317 return;
2318
2319 DBGINFO(("%s shutdown\n", info->device_name));
2320
2321 /* clear status wait queue because status changes */
2322 /* can't happen after shutting down the hardware */
2323 wake_up_interruptible(&info->status_event_wait_q);
2324 wake_up_interruptible(&info->event_wait_q);
2325
2326 del_timer_sync(&info->tx_timer);
2327 del_timer_sync(&info->rx_timer);
2328
2329 kfree(info->tx_buf);
2330 info->tx_buf = NULL;
2331
2332 spin_lock_irqsave(&info->lock,flags);
2333
2334 tx_stop(info);
2335 rx_stop(info);
2336
2337 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2338
2339 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2340 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2341 set_signals(info);
2342 }
2343
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame^]2344 flush_cond_wait(&info->gpio_wait_q);
2345
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2346 spin_unlock_irqrestore(&info->lock,flags);
2347
2348 if (info->tty)
2349 set_bit(TTY_IO_ERROR, &info->tty->flags);
2350
2351 info->flags &= ~ASYNC_INITIALIZED;
2352}
2353
2354static void program_hw(struct slgt_info *info)
2355{
2356 unsigned long flags;
2357
2358 spin_lock_irqsave(&info->lock,flags);
2359
2360 rx_stop(info);
2361 tx_stop(info);
2362
2363 if (info->params.mode == MGSL_MODE_HDLC ||
2364 info->params.mode == MGSL_MODE_RAW ||
2365 info->netcount)
2366 hdlc_mode(info);
2367 else
2368 async_mode(info);
2369
2370 set_signals(info);
2371
2372 info->dcd_chkcount = 0;
2373 info->cts_chkcount = 0;
2374 info->ri_chkcount = 0;
2375 info->dsr_chkcount = 0;
2376
2377 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2378 get_signals(info);
2379
2380 if (info->netcount ||
2381 (info->tty && info->tty->termios->c_cflag & CREAD))
2382 rx_start(info);
2383
2384 spin_unlock_irqrestore(&info->lock,flags);
2385}
2386
2387/*
2388 * reconfigure adapter based on new parameters
2389 */
2390static void change_params(struct slgt_info *info)
2391{
2392 unsigned cflag;
2393 int bits_per_char;
2394
2395 if (!info->tty || !info->tty->termios)
2396 return;
2397 DBGINFO(("%s change_params\n", info->device_name));
2398
2399 cflag = info->tty->termios->c_cflag;
2400
2401 /* if B0 rate (hangup) specified then negate DTR and RTS */
2402 /* otherwise assert DTR and RTS */
2403 if (cflag & CBAUD)
2404 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2405 else
2406 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2407
2408 /* byte size and parity */
2409
2410 switch (cflag & CSIZE) {
2411 case CS5: info->params.data_bits = 5; break;
2412 case CS6: info->params.data_bits = 6; break;
2413 case CS7: info->params.data_bits = 7; break;
2414 case CS8: info->params.data_bits = 8; break;
2415 default: info->params.data_bits = 7; break;
2416 }
2417
2418 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2419
2420 if (cflag & PARENB)
2421 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2422 else
2423 info->params.parity = ASYNC_PARITY_NONE;
2424
2425 /* calculate number of jiffies to transmit a full
2426 * FIFO (32 bytes) at specified data rate
2427 */
2428 bits_per_char = info->params.data_bits +
2429 info->params.stop_bits + 1;
2430
2431 info->params.data_rate = tty_get_baud_rate(info->tty);
2432
2433 if (info->params.data_rate) {
2434 info->timeout = (32*HZ*bits_per_char) /
2435 info->params.data_rate;
2436 }
2437 info->timeout += HZ/50; /* Add .02 seconds of slop */
2438
2439 if (cflag & CRTSCTS)
2440 info->flags |= ASYNC_CTS_FLOW;
2441 else
2442 info->flags &= ~ASYNC_CTS_FLOW;
2443
2444 if (cflag & CLOCAL)
2445 info->flags &= ~ASYNC_CHECK_CD;
2446 else
2447 info->flags |= ASYNC_CHECK_CD;
2448
2449 /* process tty input control flags */
2450
2451 info->read_status_mask = IRQ_RXOVER;
2452 if (I_INPCK(info->tty))
2453 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2454 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2455 info->read_status_mask |= MASK_BREAK;
2456 if (I_IGNPAR(info->tty))
2457 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2458 if (I_IGNBRK(info->tty)) {
2459 info->ignore_status_mask |= MASK_BREAK;
2460 /* If ignoring parity and break indicators, ignore
2461 * overruns too. (For real raw support).
2462 */
2463 if (I_IGNPAR(info->tty))
2464 info->ignore_status_mask |= MASK_OVERRUN;
2465 }
2466
2467 program_hw(info);
2468}
2469
2470static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2471{
2472 DBGINFO(("%s get_stats\n", info->device_name));
2473 if (!user_icount) {
2474 memset(&info->icount, 0, sizeof(info->icount));
2475 } else {
2476 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2477 return -EFAULT;
2478 }
2479 return 0;
2480}
2481
2482static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2483{
2484 DBGINFO(("%s get_params\n", info->device_name));
2485 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2486 return -EFAULT;
2487 return 0;
2488}
2489
2490static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2491{
2492 unsigned long flags;
2493 MGSL_PARAMS tmp_params;
2494
2495 DBGINFO(("%s set_params\n", info->device_name));
2496 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2497 return -EFAULT;
2498
2499 spin_lock_irqsave(&info->lock, flags);
2500 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2501 spin_unlock_irqrestore(&info->lock, flags);
2502
2503 change_params(info);
2504
2505 return 0;
2506}
2507
2508static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2509{
2510 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2511 if (put_user(info->idle_mode, idle_mode))
2512 return -EFAULT;
2513 return 0;
2514}
2515
2516static int set_txidle(struct slgt_info *info, int idle_mode)
2517{
2518 unsigned long flags;
2519 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2520 spin_lock_irqsave(&info->lock,flags);
2521 info->idle_mode = idle_mode;
2522 tx_set_idle(info);
2523 spin_unlock_irqrestore(&info->lock,flags);
2524 return 0;
2525}
2526
2527static int tx_enable(struct slgt_info *info, int enable)
2528{
2529 unsigned long flags;
2530 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2531 spin_lock_irqsave(&info->lock,flags);
2532 if (enable) {
2533 if (!info->tx_enabled)
2534 tx_start(info);
2535 } else {
2536 if (info->tx_enabled)
2537 tx_stop(info);
2538 }
2539 spin_unlock_irqrestore(&info->lock,flags);
2540 return 0;
2541}
2542
2543/*
2544 * abort transmit HDLC frame
2545 */
2546static int tx_abort(struct slgt_info *info)
2547{
2548 unsigned long flags;
2549 DBGINFO(("%s tx_abort\n", info->device_name));
2550 spin_lock_irqsave(&info->lock,flags);
2551 tdma_reset(info);
2552 spin_unlock_irqrestore(&info->lock,flags);
2553 return 0;
2554}
2555
2556static int rx_enable(struct slgt_info *info, int enable)
2557{
2558 unsigned long flags;
2559 DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2560 spin_lock_irqsave(&info->lock,flags);
2561 if (enable) {
2562 if (!info->rx_enabled)
2563 rx_start(info);
2564 } else {
2565 if (info->rx_enabled)
2566 rx_stop(info);
2567 }
2568 spin_unlock_irqrestore(&info->lock,flags);
2569 return 0;
2570}
2571
2572/*
2573 * wait for specified event to occur
2574 */
2575static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2576{
2577 unsigned long flags;
2578 int s;
2579 int rc=0;
2580 struct mgsl_icount cprev, cnow;
2581 int events;
2582 int mask;
2583 struct _input_signal_events oldsigs, newsigs;
2584 DECLARE_WAITQUEUE(wait, current);
2585
2586 if (get_user(mask, mask_ptr))
2587 return -EFAULT;
2588
2589 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2590
2591 spin_lock_irqsave(&info->lock,flags);
2592
2593 /* return immediately if state matches requested events */
2594 get_signals(info);
2595 s = info->signals;
2596
2597 events = mask &
2598 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2599 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2600 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2601 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2602 if (events) {
2603 spin_unlock_irqrestore(&info->lock,flags);
2604 goto exit;
2605 }
2606
2607 /* save current irq counts */
2608 cprev = info->icount;
2609 oldsigs = info->input_signal_events;
2610
2611 /* enable hunt and idle irqs if needed */
2612 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2613 unsigned short val = rd_reg16(info, SCR);
2614 if (!(val & IRQ_RXIDLE))
2615 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2616 }
2617
2618 set_current_state(TASK_INTERRUPTIBLE);
2619 add_wait_queue(&info->event_wait_q, &wait);
2620
2621 spin_unlock_irqrestore(&info->lock,flags);
2622
2623 for(;;) {
2624 schedule();
2625 if (signal_pending(current)) {
2626 rc = -ERESTARTSYS;
2627 break;
2628 }
2629
2630 /* get current irq counts */
2631 spin_lock_irqsave(&info->lock,flags);
2632 cnow = info->icount;
2633 newsigs = info->input_signal_events;
2634 set_current_state(TASK_INTERRUPTIBLE);
2635 spin_unlock_irqrestore(&info->lock,flags);
2636
2637 /* if no change, wait aborted for some reason */
2638 if (newsigs.dsr_up == oldsigs.dsr_up &&
2639 newsigs.dsr_down == oldsigs.dsr_down &&
2640 newsigs.dcd_up == oldsigs.dcd_up &&
2641 newsigs.dcd_down == oldsigs.dcd_down &&
2642 newsigs.cts_up == oldsigs.cts_up &&
2643 newsigs.cts_down == oldsigs.cts_down &&
2644 newsigs.ri_up == oldsigs.ri_up &&
2645 newsigs.ri_down == oldsigs.ri_down &&
2646 cnow.exithunt == cprev.exithunt &&
2647 cnow.rxidle == cprev.rxidle) {
2648 rc = -EIO;
2649 break;
2650 }
2651
2652 events = mask &
2653 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2654 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2655 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2656 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2657 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2658 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2659 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2660 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2661 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2662 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2663 if (events)
2664 break;
2665
2666 cprev = cnow;
2667 oldsigs = newsigs;
2668 }
2669
2670 remove_wait_queue(&info->event_wait_q, &wait);
2671 set_current_state(TASK_RUNNING);
2672
2673
2674 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2675 spin_lock_irqsave(&info->lock,flags);
2676 if (!waitqueue_active(&info->event_wait_q)) {
2677 /* disable enable exit hunt mode/idle rcvd IRQs */
2678 wr_reg16(info, SCR,
2679 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2680 }
2681 spin_unlock_irqrestore(&info->lock,flags);
2682 }
2683exit:
2684 if (rc == 0)
2685 rc = put_user(events, mask_ptr);
2686 return rc;
2687}
2688
2689static int get_interface(struct slgt_info *info, int __user *if_mode)
2690{
2691 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2692 if (put_user(info->if_mode, if_mode))
2693 return -EFAULT;
2694 return 0;
2695}
2696
2697static int set_interface(struct slgt_info *info, int if_mode)
2698{
2699 unsigned long flags;
Paul Fulghum35fbd392006-01-18 17:42:24 -0800[diff] [blame]2700 unsigned short val;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2701
2702 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2703 spin_lock_irqsave(&info->lock,flags);
2704 info->if_mode = if_mode;
2705
2706 msc_set_vcr(info);
2707
2708 /* TCR (tx control) 07 1=RTS driver control */
2709 val = rd_reg16(info, TCR);
2710 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2711 val |= BIT7;
2712 else
2713 val &= ~BIT7;
2714 wr_reg16(info, TCR, val);
2715
2716 spin_unlock_irqrestore(&info->lock,flags);
2717 return 0;
2718}
2719
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame^]2720/*
2721 * set general purpose IO pin state and direction
2722 *
2723 * user_gpio fields:
2724 * state each bit indicates a pin state
2725 * smask set bit indicates pin state to set
2726 * dir each bit indicates a pin direction (0=input, 1=output)
2727 * dmask set bit indicates pin direction to set
2728 */
2729static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2730{
2731 unsigned long flags;
2732 struct gpio_desc gpio;
2733 __u32 data;
2734
2735 if (!info->gpio_present)
2736 return -EINVAL;
2737 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2738 return -EFAULT;
2739 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2740 info->device_name, gpio.state, gpio.smask,
2741 gpio.dir, gpio.dmask));
2742
2743 spin_lock_irqsave(&info->lock,flags);
2744 if (gpio.dmask) {
2745 data = rd_reg32(info, IODR);
2746 data |= gpio.dmask & gpio.dir;
2747 data &= ~(gpio.dmask & ~gpio.dir);
2748 wr_reg32(info, IODR, data);
2749 }
2750 if (gpio.smask) {
2751 data = rd_reg32(info, IOVR);
2752 data |= gpio.smask & gpio.state;
2753 data &= ~(gpio.smask & ~gpio.state);
2754 wr_reg32(info, IOVR, data);
2755 }
2756 spin_unlock_irqrestore(&info->lock,flags);
2757
2758 return 0;
2759}
2760
2761/*
2762 * get general purpose IO pin state and direction
2763 */
2764static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2765{
2766 struct gpio_desc gpio;
2767 if (!info->gpio_present)
2768 return -EINVAL;
2769 gpio.state = rd_reg32(info, IOVR);
2770 gpio.smask = 0xffffffff;
2771 gpio.dir = rd_reg32(info, IODR);
2772 gpio.dmask = 0xffffffff;
2773 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2774 return -EFAULT;
2775 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2776 info->device_name, gpio.state, gpio.dir));
2777 return 0;
2778}
2779
2780/*
2781 * conditional wait facility
2782 */
2783static void init_cond_wait(struct cond_wait *w, unsigned int data)
2784{
2785 init_waitqueue_head(&w->q);
2786 init_waitqueue_entry(&w->wait, current);
2787 w->data = data;
2788}
2789
2790static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2791{
2792 set_current_state(TASK_INTERRUPTIBLE);
2793 add_wait_queue(&w->q, &w->wait);
2794 w->next = *head;
2795 *head = w;
2796}
2797
2798static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2799{
2800 struct cond_wait *w, *prev;
2801 remove_wait_queue(&cw->q, &cw->wait);
2802 set_current_state(TASK_RUNNING);
2803 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2804 if (w == cw) {
2805 if (prev != NULL)
2806 prev->next = w->next;
2807 else
2808 *head = w->next;
2809 break;
2810 }
2811 }
2812}
2813
2814static void flush_cond_wait(struct cond_wait **head)
2815{
2816 while (*head != NULL) {
2817 wake_up_interruptible(&(*head)->q);
2818 *head = (*head)->next;
2819 }
2820}
2821
2822/*
2823 * wait for general purpose I/O pin(s) to enter specified state
2824 *
2825 * user_gpio fields:
2826 * state - bit indicates target pin state
2827 * smask - set bit indicates watched pin
2828 *
2829 * The wait ends when at least one watched pin enters the specified
2830 * state. When 0 (no error) is returned, user_gpio->state is set to the
2831 * state of all GPIO pins when the wait ends.
2832 *
2833 * Note: Each pin may be a dedicated input, dedicated output, or
2834 * configurable input/output. The number and configuration of pins
2835 * varies with the specific adapter model. Only input pins (dedicated
2836 * or configured) can be monitored with this function.
2837 */
2838static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2839{
2840 unsigned long flags;
2841 int rc = 0;
2842 struct gpio_desc gpio;
2843 struct cond_wait wait;
2844 u32 state;
2845
2846 if (!info->gpio_present)
2847 return -EINVAL;
2848 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2849 return -EFAULT;
2850 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2851 info->device_name, gpio.state, gpio.smask));
2852 /* ignore output pins identified by set IODR bit */
2853 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2854 return -EINVAL;
2855 init_cond_wait(&wait, gpio.smask);
2856
2857 spin_lock_irqsave(&info->lock, flags);
2858 /* enable interrupts for watched pins */
2859 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2860 /* get current pin states */
2861 state = rd_reg32(info, IOVR);
2862
2863 if (gpio.smask & ~(state ^ gpio.state)) {
2864 /* already in target state */
2865 gpio.state = state;
2866 } else {
2867 /* wait for target state */
2868 add_cond_wait(&info->gpio_wait_q, &wait);
2869 spin_unlock_irqrestore(&info->lock, flags);
2870 schedule();
2871 if (signal_pending(current))
2872 rc = -ERESTARTSYS;
2873 else
2874 gpio.state = wait.data;
2875 spin_lock_irqsave(&info->lock, flags);
2876 remove_cond_wait(&info->gpio_wait_q, &wait);
2877 }
2878
2879 /* disable all GPIO interrupts if no waiting processes */
2880 if (info->gpio_wait_q == NULL)
2881 wr_reg32(info, IOER, 0);
2882 spin_unlock_irqrestore(&info->lock,flags);
2883
2884 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2885 rc = -EFAULT;
2886 return rc;
2887}
2888
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2889static int modem_input_wait(struct slgt_info *info,int arg)
2890{
2891 unsigned long flags;
2892 int rc;
2893 struct mgsl_icount cprev, cnow;
2894 DECLARE_WAITQUEUE(wait, current);
2895
2896 /* save current irq counts */
2897 spin_lock_irqsave(&info->lock,flags);
2898 cprev = info->icount;
2899 add_wait_queue(&info->status_event_wait_q, &wait);
2900 set_current_state(TASK_INTERRUPTIBLE);
2901 spin_unlock_irqrestore(&info->lock,flags);
2902
2903 for(;;) {
2904 schedule();
2905 if (signal_pending(current)) {
2906 rc = -ERESTARTSYS;
2907 break;
2908 }
2909
2910 /* get new irq counts */
2911 spin_lock_irqsave(&info->lock,flags);
2912 cnow = info->icount;
2913 set_current_state(TASK_INTERRUPTIBLE);
2914 spin_unlock_irqrestore(&info->lock,flags);
2915
2916 /* if no change, wait aborted for some reason */
2917 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2918 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2919 rc = -EIO;
2920 break;
2921 }
2922
2923 /* check for change in caller specified modem input */
2924 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2925 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2926 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2927 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2928 rc = 0;
2929 break;
2930 }
2931
2932 cprev = cnow;
2933 }
2934 remove_wait_queue(&info->status_event_wait_q, &wait);
2935 set_current_state(TASK_RUNNING);
2936 return rc;
2937}
2938
2939/*
2940 * return state of serial control and status signals
2941 */
2942static int tiocmget(struct tty_struct *tty, struct file *file)
2943{
2944 struct slgt_info *info = tty->driver_data;
2945 unsigned int result;
2946 unsigned long flags;
2947
2948 spin_lock_irqsave(&info->lock,flags);
2949 get_signals(info);
2950 spin_unlock_irqrestore(&info->lock,flags);
2951
2952 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2953 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2954 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2955 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2956 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2957 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2958
2959 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
2960 return result;
2961}
2962
2963/*
2964 * set modem control signals (DTR/RTS)
2965 *
2966 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
2967 * TIOCMSET = set/clear signal values
2968 * value bit mask for command
2969 */
2970static int tiocmset(struct tty_struct *tty, struct file *file,
2971 unsigned int set, unsigned int clear)
2972{
2973 struct slgt_info *info = tty->driver_data;
2974 unsigned long flags;
2975
2976 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
2977
2978 if (set & TIOCM_RTS)
2979 info->signals |= SerialSignal_RTS;
2980 if (set & TIOCM_DTR)
2981 info->signals |= SerialSignal_DTR;
2982 if (clear & TIOCM_RTS)
2983 info->signals &= ~SerialSignal_RTS;
2984 if (clear & TIOCM_DTR)
2985 info->signals &= ~SerialSignal_DTR;
2986
2987 spin_lock_irqsave(&info->lock,flags);
2988 set_signals(info);
2989 spin_unlock_irqrestore(&info->lock,flags);
2990 return 0;
2991}
2992
2993/*
2994 * block current process until the device is ready to open
2995 */
2996static int block_til_ready(struct tty_struct *tty, struct file *filp,
2997 struct slgt_info *info)
2998{
2999 DECLARE_WAITQUEUE(wait, current);
3000 int retval;
3001 int do_clocal = 0, extra_count = 0;
3002 unsigned long flags;
3003
3004 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3005
3006 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3007 /* nonblock mode is set or port is not enabled */
3008 info->flags |= ASYNC_NORMAL_ACTIVE;
3009 return 0;
3010 }
3011
3012 if (tty->termios->c_cflag & CLOCAL)
3013 do_clocal = 1;
3014
3015 /* Wait for carrier detect and the line to become
3016 * free (i.e., not in use by the callout). While we are in
3017 * this loop, info->count is dropped by one, so that
3018 * close() knows when to free things. We restore it upon
3019 * exit, either normal or abnormal.
3020 */
3021
3022 retval = 0;
3023 add_wait_queue(&info->open_wait, &wait);
3024
3025 spin_lock_irqsave(&info->lock, flags);
3026 if (!tty_hung_up_p(filp)) {
3027 extra_count = 1;
3028 info->count--;
3029 }
3030 spin_unlock_irqrestore(&info->lock, flags);
3031 info->blocked_open++;
3032
3033 while (1) {
3034 if ((tty->termios->c_cflag & CBAUD)) {
3035 spin_lock_irqsave(&info->lock,flags);
3036 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3037 set_signals(info);
3038 spin_unlock_irqrestore(&info->lock,flags);
3039 }
3040
3041 set_current_state(TASK_INTERRUPTIBLE);
3042
3043 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3044 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3045 -EAGAIN : -ERESTARTSYS;
3046 break;
3047 }
3048
3049 spin_lock_irqsave(&info->lock,flags);
3050 get_signals(info);
3051 spin_unlock_irqrestore(&info->lock,flags);
3052
3053 if (!(info->flags & ASYNC_CLOSING) &&
3054 (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3055 break;
3056 }
3057
3058 if (signal_pending(current)) {
3059 retval = -ERESTARTSYS;
3060 break;
3061 }
3062
3063 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3064 schedule();
3065 }
3066
3067 set_current_state(TASK_RUNNING);
3068 remove_wait_queue(&info->open_wait, &wait);
3069
3070 if (extra_count)
3071 info->count++;
3072 info->blocked_open--;
3073
3074 if (!retval)
3075 info->flags |= ASYNC_NORMAL_ACTIVE;
3076
3077 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3078 return retval;
3079}
3080
3081static int alloc_tmp_rbuf(struct slgt_info *info)
3082{
3083 info->tmp_rbuf = kmalloc(info->max_frame_size, GFP_KERNEL);
3084 if (info->tmp_rbuf == NULL)
3085 return -ENOMEM;
3086 return 0;
3087}
3088
3089static void free_tmp_rbuf(struct slgt_info *info)
3090{
3091 kfree(info->tmp_rbuf);
3092 info->tmp_rbuf = NULL;
3093}
3094
3095/*
3096 * allocate DMA descriptor lists.
3097 */
3098static int alloc_desc(struct slgt_info *info)
3099{
3100 unsigned int i;
3101 unsigned int pbufs;
3102
3103 /* allocate memory to hold descriptor lists */
3104 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3105 if (info->bufs == NULL)
3106 return -ENOMEM;
3107
3108 memset(info->bufs, 0, DESC_LIST_SIZE);
3109
3110 info->rbufs = (struct slgt_desc*)info->bufs;
3111 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3112
3113 pbufs = (unsigned int)info->bufs_dma_addr;
3114
3115 /*
3116 * Build circular lists of descriptors
3117 */
3118
3119 for (i=0; i < info->rbuf_count; i++) {
3120 /* physical address of this descriptor */
3121 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3122
3123 /* physical address of next descriptor */
3124 if (i == info->rbuf_count - 1)
3125 info->rbufs[i].next = cpu_to_le32(pbufs);
3126 else
3127 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3128 set_desc_count(info->rbufs[i], DMABUFSIZE);
3129 }
3130
3131 for (i=0; i < info->tbuf_count; i++) {
3132 /* physical address of this descriptor */
3133 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3134
3135 /* physical address of next descriptor */
3136 if (i == info->tbuf_count - 1)
3137 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3138 else
3139 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3140 }
3141
3142 return 0;
3143}
3144
3145static void free_desc(struct slgt_info *info)
3146{
3147 if (info->bufs != NULL) {
3148 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3149 info->bufs = NULL;
3150 info->rbufs = NULL;
3151 info->tbufs = NULL;
3152 }
3153}
3154
3155static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3156{
3157 int i;
3158 for (i=0; i < count; i++) {
3159 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3160 return -ENOMEM;
3161 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3162 }
3163 return 0;
3164}
3165
3166static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3167{
3168 int i;
3169 for (i=0; i < count; i++) {
3170 if (bufs[i].buf == NULL)
3171 continue;
3172 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3173 bufs[i].buf = NULL;
3174 }
3175}
3176
3177static int alloc_dma_bufs(struct slgt_info *info)
3178{
3179 info->rbuf_count = 32;
3180 info->tbuf_count = 32;
3181
3182 if (alloc_desc(info) < 0 ||
3183 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3184 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3185 alloc_tmp_rbuf(info) < 0) {
3186 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3187 return -ENOMEM;
3188 }
3189 reset_rbufs(info);
3190 return 0;
3191}
3192
3193static void free_dma_bufs(struct slgt_info *info)
3194{
3195 if (info->bufs) {
3196 free_bufs(info, info->rbufs, info->rbuf_count);
3197 free_bufs(info, info->tbufs, info->tbuf_count);
3198 free_desc(info);
3199 }
3200 free_tmp_rbuf(info);
3201}
3202
3203static int claim_resources(struct slgt_info *info)
3204{
3205 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3206 DBGERR(("%s reg addr conflict, addr=%08X\n",
3207 info->device_name, info->phys_reg_addr));
3208 info->init_error = DiagStatus_AddressConflict;
3209 goto errout;
3210 }
3211 else
3212 info->reg_addr_requested = 1;
3213
Paul Fulghum0c8365e2006-01-11 12:17:39 -0800[diff] [blame]3214 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3215 if (!info->reg_addr) {
3216 DBGERR(("%s cant map device registers, addr=%08X\n",
3217 info->device_name, info->phys_reg_addr));
3218 info->init_error = DiagStatus_CantAssignPciResources;
3219 goto errout;
3220 }
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3221 return 0;
3222
3223errout:
3224 release_resources(info);
3225 return -ENODEV;
3226}
3227
3228static void release_resources(struct slgt_info *info)
3229{
3230 if (info->irq_requested) {
3231 free_irq(info->irq_level, info);
3232 info->irq_requested = 0;
3233 }
3234
3235 if (info->reg_addr_requested) {
3236 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3237 info->reg_addr_requested = 0;
3238 }
3239
3240 if (info->reg_addr) {
Paul Fulghum0c8365e2006-01-11 12:17:39 -0800[diff] [blame]3241 iounmap(info->reg_addr);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3242 info->reg_addr = NULL;
3243 }
3244}
3245
3246/* Add the specified device instance data structure to the
3247 * global linked list of devices and increment the device count.
3248 */
3249static void add_device(struct slgt_info *info)
3250{
3251 char *devstr;
3252
3253 info->next_device = NULL;
3254 info->line = slgt_device_count;
3255 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3256
3257 if (info->line < MAX_DEVICES) {
3258 if (maxframe[info->line])
3259 info->max_frame_size = maxframe[info->line];
3260 info->dosyncppp = dosyncppp[info->line];
3261 }
3262
3263 slgt_device_count++;
3264
3265 if (!slgt_device_list)
3266 slgt_device_list = info;
3267 else {
3268 struct slgt_info *current_dev = slgt_device_list;
3269 while(current_dev->next_device)
3270 current_dev = current_dev->next_device;
3271 current_dev->next_device = info;
3272 }
3273
3274 if (info->max_frame_size < 4096)
3275 info->max_frame_size = 4096;
3276 else if (info->max_frame_size > 65535)
3277 info->max_frame_size = 65535;
3278
3279 switch(info->pdev->device) {
3280 case SYNCLINK_GT_DEVICE_ID:
3281 devstr = "GT";
3282 break;
3283 case SYNCLINK_GT4_DEVICE_ID:
3284 devstr = "GT4";
3285 break;
3286 case SYNCLINK_AC_DEVICE_ID:
3287 devstr = "AC";
3288 info->params.mode = MGSL_MODE_ASYNC;
3289 break;
3290 default:
3291 devstr = "(unknown model)";
3292 }
3293 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3294 devstr, info->device_name, info->phys_reg_addr,
3295 info->irq_level, info->max_frame_size);
3296
3297#ifdef CONFIG_HDLC
3298 hdlcdev_init(info);
3299#endif
3300}
3301
3302/*
3303 * allocate device instance structure, return NULL on failure
3304 */
3305static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3306{
3307 struct slgt_info *info;
3308
3309 info = kmalloc(sizeof(struct slgt_info), GFP_KERNEL);
3310
3311 if (!info) {
3312 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3313 driver_name, adapter_num, port_num));
3314 } else {
3315 memset(info, 0, sizeof(struct slgt_info));
3316 info->magic = MGSL_MAGIC;
3317 INIT_WORK(&info->task, bh_handler, info);
3318 info->max_frame_size = 4096;
3319 info->raw_rx_size = DMABUFSIZE;
3320 info->close_delay = 5*HZ/10;
3321 info->closing_wait = 30*HZ;
3322 init_waitqueue_head(&info->open_wait);
3323 init_waitqueue_head(&info->close_wait);
3324 init_waitqueue_head(&info->status_event_wait_q);
3325 init_waitqueue_head(&info->event_wait_q);
3326 spin_lock_init(&info->netlock);
3327 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3328 info->idle_mode = HDLC_TXIDLE_FLAGS;
3329 info->adapter_num = adapter_num;
3330 info->port_num = port_num;
3331
3332 init_timer(&info->tx_timer);
3333 info->tx_timer.data = (unsigned long)info;
3334 info->tx_timer.function = tx_timeout;
3335
3336 init_timer(&info->rx_timer);
3337 info->rx_timer.data = (unsigned long)info;
3338 info->rx_timer.function = rx_timeout;
3339
3340 /* Copy configuration info to device instance data */
3341 info->pdev = pdev;
3342 info->irq_level = pdev->irq;
3343 info->phys_reg_addr = pci_resource_start(pdev,0);
3344
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3345 info->bus_type = MGSL_BUS_TYPE_PCI;
3346 info->irq_flags = SA_SHIRQ;
3347
3348 info->init_error = -1; /* assume error, set to 0 on successful init */
3349 }
3350
3351 return info;
3352}
3353
3354static void device_init(int adapter_num, struct pci_dev *pdev)
3355{
3356 struct slgt_info *port_array[SLGT_MAX_PORTS];
3357 int i;
3358 int port_count = 1;
3359
3360 if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3361 port_count = 4;
3362
3363 /* allocate device instances for all ports */
3364 for (i=0; i < port_count; ++i) {
3365 port_array[i] = alloc_dev(adapter_num, i, pdev);
3366 if (port_array[i] == NULL) {
3367 for (--i; i >= 0; --i)
3368 kfree(port_array[i]);
3369 return;
3370 }
3371 }
3372
3373 /* give copy of port_array to all ports and add to device list */
3374 for (i=0; i < port_count; ++i) {
3375 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3376 add_device(port_array[i]);
3377 port_array[i]->port_count = port_count;
3378 spin_lock_init(&port_array[i]->lock);
3379 }
3380
3381 /* Allocate and claim adapter resources */
3382 if (!claim_resources(port_array[0])) {
3383
3384 alloc_dma_bufs(port_array[0]);
3385
3386 /* copy resource information from first port to others */
3387 for (i = 1; i < port_count; ++i) {
3388 port_array[i]->lock = port_array[0]->lock;
3389 port_array[i]->irq_level = port_array[0]->irq_level;
3390 port_array[i]->reg_addr = port_array[0]->reg_addr;
3391 alloc_dma_bufs(port_array[i]);
3392 }
3393
3394 if (request_irq(port_array[0]->irq_level,
3395 slgt_interrupt,
3396 port_array[0]->irq_flags,
3397 port_array[0]->device_name,
3398 port_array[0]) < 0) {
3399 DBGERR(("%s request_irq failed IRQ=%d\n",
3400 port_array[0]->device_name,
3401 port_array[0]->irq_level));
3402 } else {
3403 port_array[0]->irq_requested = 1;
3404 adapter_test(port_array[0]);
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame^]3405 for (i=1 ; i < port_count ; i++) {
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3406 port_array[i]->init_error = port_array[0]->init_error;
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame^]3407 port_array[i]->gpio_present = port_array[0]->gpio_present;
3408 }
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3409 }
3410 }
3411}
3412
3413static int __devinit init_one(struct pci_dev *dev,
3414 const struct pci_device_id *ent)
3415{
3416 if (pci_enable_device(dev)) {
3417 printk("error enabling pci device %p\n", dev);
3418 return -EIO;
3419 }
3420 pci_set_master(dev);
3421 device_init(slgt_device_count, dev);
3422 return 0;
3423}
3424
3425static void __devexit remove_one(struct pci_dev *dev)
3426{
3427}
3428
3429static struct tty_operations ops = {
3430 .open = open,
3431 .close = close,
3432 .write = write,
3433 .put_char = put_char,
3434 .flush_chars = flush_chars,
3435 .write_room = write_room,
3436 .chars_in_buffer = chars_in_buffer,
3437 .flush_buffer = flush_buffer,
3438 .ioctl = ioctl,
3439 .throttle = throttle,
3440 .unthrottle = unthrottle,
3441 .send_xchar = send_xchar,
3442 .break_ctl = set_break,
3443 .wait_until_sent = wait_until_sent,
3444 .read_proc = read_proc,
3445 .set_termios = set_termios,
3446 .stop = tx_hold,
3447 .start = tx_release,
3448 .hangup = hangup,
3449 .tiocmget = tiocmget,
3450 .tiocmset = tiocmset,
3451};
3452
3453static void slgt_cleanup(void)
3454{
3455 int rc;
3456 struct slgt_info *info;
3457 struct slgt_info *tmp;
3458
3459 printk("unload %s %s\n", driver_name, driver_version);
3460
3461 if (serial_driver) {
3462 if ((rc = tty_unregister_driver(serial_driver)))
3463 DBGERR(("tty_unregister_driver error=%d\n", rc));
3464 put_tty_driver(serial_driver);
3465 }
3466
3467 /* reset devices */
3468 info = slgt_device_list;
3469 while(info) {
3470 reset_port(info);
3471 info = info->next_device;
3472 }
3473
3474 /* release devices */
3475 info = slgt_device_list;
3476 while(info) {
3477#ifdef CONFIG_HDLC
3478 hdlcdev_exit(info);
3479#endif
3480 free_dma_bufs(info);
3481 free_tmp_rbuf(info);
3482 if (info->port_num == 0)
3483 release_resources(info);
3484 tmp = info;
3485 info = info->next_device;
3486 kfree(tmp);
3487 }
3488
3489 if (pci_registered)
3490 pci_unregister_driver(&pci_driver);
3491}
3492
3493/*
3494 * Driver initialization entry point.
3495 */
3496static int __init slgt_init(void)
3497{
3498 int rc;
3499
3500 printk("%s %s\n", driver_name, driver_version);
3501
3502 slgt_device_count = 0;
3503 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3504 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3505 return rc;
3506 }
3507 pci_registered = 1;
3508
3509 if (!slgt_device_list) {
3510 printk("%s no devices found\n",driver_name);
3511 return -ENODEV;
3512 }
3513
3514 serial_driver = alloc_tty_driver(MAX_DEVICES);
3515 if (!serial_driver) {
3516 rc = -ENOMEM;
3517 goto error;
3518 }
3519
3520 /* Initialize the tty_driver structure */
3521
3522 serial_driver->owner = THIS_MODULE;
3523 serial_driver->driver_name = tty_driver_name;
3524 serial_driver->name = tty_dev_prefix;
3525 serial_driver->major = ttymajor;
3526 serial_driver->minor_start = 64;
3527 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3528 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3529 serial_driver->init_termios = tty_std_termios;
3530 serial_driver->init_termios.c_cflag =
3531 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3532 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3533 tty_set_operations(serial_driver, &ops);
3534 if ((rc = tty_register_driver(serial_driver)) < 0) {
3535 DBGERR(("%s can't register serial driver\n", driver_name));
3536 put_tty_driver(serial_driver);
3537 serial_driver = NULL;
3538 goto error;
3539 }
3540
3541 printk("%s %s, tty major#%d\n",
3542 driver_name, driver_version,
3543 serial_driver->major);
3544
3545 return 0;
3546
3547error:
3548 slgt_cleanup();
3549 return rc;
3550}
3551
3552static void __exit slgt_exit(void)
3553{
3554 slgt_cleanup();
3555}
3556
3557module_init(slgt_init);
3558module_exit(slgt_exit);
3559
3560/*
3561 * register access routines
3562 */
3563
3564#define CALC_REGADDR() \
3565 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3566 if (addr >= 0x80) \
3567 reg_addr += (info->port_num) * 32;
3568
3569static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3570{
3571 CALC_REGADDR();
3572 return readb((void __iomem *)reg_addr);
3573}
3574
3575static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3576{
3577 CALC_REGADDR();
3578 writeb(value, (void __iomem *)reg_addr);
3579}
3580
3581static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3582{
3583 CALC_REGADDR();
3584 return readw((void __iomem *)reg_addr);
3585}
3586
3587static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3588{
3589 CALC_REGADDR();
3590 writew(value, (void __iomem *)reg_addr);
3591}
3592
3593static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3594{
3595 CALC_REGADDR();
3596 return readl((void __iomem *)reg_addr);
3597}
3598
3599static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3600{
3601 CALC_REGADDR();
3602 writel(value, (void __iomem *)reg_addr);
3603}
3604
3605static void rdma_reset(struct slgt_info *info)
3606{
3607 unsigned int i;
3608
3609 /* set reset bit */
3610 wr_reg32(info, RDCSR, BIT1);
3611
3612 /* wait for enable bit cleared */
3613 for(i=0 ; i < 1000 ; i++)
3614 if (!(rd_reg32(info, RDCSR) & BIT0))
3615 break;
3616}
3617
3618static void tdma_reset(struct slgt_info *info)
3619{
3620 unsigned int i;
3621
3622 /* set reset bit */
3623 wr_reg32(info, TDCSR, BIT1);
3624
3625 /* wait for enable bit cleared */
3626 for(i=0 ; i < 1000 ; i++)
3627 if (!(rd_reg32(info, TDCSR) & BIT0))
3628 break;
3629}
3630
3631/*
3632 * enable internal loopback
3633 * TxCLK and RxCLK are generated from BRG
3634 * and TxD is looped back to RxD internally.
3635 */
3636static void enable_loopback(struct slgt_info *info)
3637{
3638 /* SCR (serial control) BIT2=looopback enable */
3639 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3640
3641 if (info->params.mode != MGSL_MODE_ASYNC) {
3642 /* CCR (clock control)
3643 * 07..05 tx clock source (010 = BRG)
3644 * 04..02 rx clock source (010 = BRG)
3645 * 01 auxclk enable (0 = disable)
3646 * 00 BRG enable (1 = enable)
3647 *
3648 * 0100 1001
3649 */
3650 wr_reg8(info, CCR, 0x49);
3651
3652 /* set speed if available, otherwise use default */
3653 if (info->params.clock_speed)
3654 set_rate(info, info->params.clock_speed);
3655 else
3656 set_rate(info, 3686400);
3657 }
3658}
3659
3660/*
3661 * set baud rate generator to specified rate
3662 */
3663static void set_rate(struct slgt_info *info, u32 rate)
3664{
3665 unsigned int div;
3666 static unsigned int osc = 14745600;
3667
3668 /* div = osc/rate - 1
3669 *
3670 * Round div up if osc/rate is not integer to
3671 * force to next slowest rate.
3672 */
3673
3674 if (rate) {
3675 div = osc/rate;
3676 if (!(osc % rate) && div)
3677 div--;
3678 wr_reg16(info, BDR, (unsigned short)div);
3679 }
3680}
3681
3682static void rx_stop(struct slgt_info *info)
3683{
3684 unsigned short val;
3685
3686 /* disable and reset receiver */
3687 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3688 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3689 wr_reg16(info, RCR, val); /* clear reset bit */
3690
3691 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3692
3693 /* clear pending rx interrupts */
3694 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3695
3696 rdma_reset(info);
3697
3698 info->rx_enabled = 0;
3699 info->rx_restart = 0;
3700}
3701
3702static void rx_start(struct slgt_info *info)
3703{
3704 unsigned short val;
3705
3706 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3707
3708 /* clear pending rx overrun IRQ */
3709 wr_reg16(info, SSR, IRQ_RXOVER);
3710
3711 /* reset and disable receiver */
3712 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3713 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3714 wr_reg16(info, RCR, val); /* clear reset bit */
3715
3716 rdma_reset(info);
3717 reset_rbufs(info);
3718
3719 /* set 1st descriptor address */
3720 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3721
3722 if (info->params.mode != MGSL_MODE_ASYNC) {
3723 /* enable rx DMA and DMA interrupt */
3724 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3725 } else {
3726 /* enable saving of rx status, rx DMA and DMA interrupt */
3727 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3728 }
3729
3730 slgt_irq_on(info, IRQ_RXOVER);
3731
3732 /* enable receiver */
3733 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3734
3735 info->rx_restart = 0;
3736 info->rx_enabled = 1;
3737}
3738
3739static void tx_start(struct slgt_info *info)
3740{
3741 if (!info->tx_enabled) {
3742 wr_reg16(info, TCR,
3743 (unsigned short)(rd_reg16(info, TCR) | BIT1));
3744 info->tx_enabled = TRUE;
3745 }
3746
3747 if (info->tx_count) {
3748 info->drop_rts_on_tx_done = 0;
3749
3750 if (info->params.mode != MGSL_MODE_ASYNC) {
3751 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3752 get_signals(info);
3753 if (!(info->signals & SerialSignal_RTS)) {
3754 info->signals |= SerialSignal_RTS;
3755 set_signals(info);
3756 info->drop_rts_on_tx_done = 1;
3757 }
3758 }
3759
3760 slgt_irq_off(info, IRQ_TXDATA);
3761 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3762 /* clear tx idle and underrun status bits */
3763 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3764
3765 if (!(rd_reg32(info, TDCSR) & BIT0)) {
3766 /* tx DMA stopped, restart tx DMA */
3767 tdma_reset(info);
3768 /* set 1st descriptor address */
3769 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3770 if (info->params.mode == MGSL_MODE_RAW)
3771 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3772 else
3773 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3774 }
3775
3776 if (info->params.mode != MGSL_MODE_RAW) {
3777 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
3778 add_timer(&info->tx_timer);
3779 }
3780 } else {
3781 tdma_reset(info);
3782 /* set 1st descriptor address */
3783 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3784
3785 slgt_irq_off(info, IRQ_TXDATA);
3786 slgt_irq_on(info, IRQ_TXIDLE);
3787 /* clear tx idle status bit */
3788 wr_reg16(info, SSR, IRQ_TXIDLE);
3789
3790 /* enable tx DMA */
3791 wr_reg32(info, TDCSR, BIT0);
3792 }
3793
3794 info->tx_active = 1;
3795 }
3796}
3797
3798static void tx_stop(struct slgt_info *info)
3799{
3800 unsigned short val;
3801
3802 del_timer(&info->tx_timer);
3803
3804 tdma_reset(info);
3805
3806 /* reset and disable transmitter */
3807 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3808 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3809 wr_reg16(info, TCR, val); /* clear reset */
3810
3811 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3812
3813 /* clear tx idle and underrun status bit */
3814 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3815
3816 reset_tbufs(info);
3817
3818 info->tx_enabled = 0;
3819 info->tx_active = 0;
3820}
3821
3822static void reset_port(struct slgt_info *info)
3823{
3824 if (!info->reg_addr)
3825 return;
3826
3827 tx_stop(info);
3828 rx_stop(info);
3829
3830 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3831 set_signals(info);
3832
3833 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3834}
3835
3836static void reset_adapter(struct slgt_info *info)
3837{
3838 int i;
3839 for (i=0; i < info->port_count; ++i) {
3840 if (info->port_array[i])
3841 reset_port(info->port_array[i]);
3842 }
3843}
3844
3845static void async_mode(struct slgt_info *info)
3846{
3847 unsigned short val;
3848
3849 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3850 tx_stop(info);
3851 rx_stop(info);
3852
3853 /* TCR (tx control)
3854 *
3855 * 15..13 mode, 010=async
3856 * 12..10 encoding, 000=NRZ
3857 * 09 parity enable
3858 * 08 1=odd parity, 0=even parity
3859 * 07 1=RTS driver control
3860 * 06 1=break enable
3861 * 05..04 character length
3862 * 00=5 bits
3863 * 01=6 bits
3864 * 10=7 bits
3865 * 11=8 bits
3866 * 03 0=1 stop bit, 1=2 stop bits
3867 * 02 reset
3868 * 01 enable
3869 * 00 auto-CTS enable
3870 */
3871 val = 0x4000;
3872
3873 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3874 val |= BIT7;
3875
3876 if (info->params.parity != ASYNC_PARITY_NONE) {
3877 val |= BIT9;
3878 if (info->params.parity == ASYNC_PARITY_ODD)
3879 val |= BIT8;
3880 }
3881
3882 switch (info->params.data_bits)
3883 {
3884 case 6: val |= BIT4; break;
3885 case 7: val |= BIT5; break;
3886 case 8: val |= BIT5 + BIT4; break;
3887 }
3888
3889 if (info->params.stop_bits != 1)
3890 val |= BIT3;
3891
3892 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3893 val |= BIT0;
3894
3895 wr_reg16(info, TCR, val);
3896
3897 /* RCR (rx control)
3898 *
3899 * 15..13 mode, 010=async
3900 * 12..10 encoding, 000=NRZ
3901 * 09 parity enable
3902 * 08 1=odd parity, 0=even parity
3903 * 07..06 reserved, must be 0
3904 * 05..04 character length
3905 * 00=5 bits
3906 * 01=6 bits
3907 * 10=7 bits
3908 * 11=8 bits
3909 * 03 reserved, must be zero
3910 * 02 reset
3911 * 01 enable
3912 * 00 auto-DCD enable
3913 */
3914 val = 0x4000;
3915
3916 if (info->params.parity != ASYNC_PARITY_NONE) {
3917 val |= BIT9;
3918 if (info->params.parity == ASYNC_PARITY_ODD)
3919 val |= BIT8;
3920 }
3921
3922 switch (info->params.data_bits)
3923 {
3924 case 6: val |= BIT4; break;
3925 case 7: val |= BIT5; break;
3926 case 8: val |= BIT5 + BIT4; break;
3927 }
3928
3929 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3930 val |= BIT0;
3931
3932 wr_reg16(info, RCR, val);
3933
3934 /* CCR (clock control)
3935 *
3936 * 07..05 011 = tx clock source is BRG/16
3937 * 04..02 010 = rx clock source is BRG
3938 * 01 0 = auxclk disabled
3939 * 00 1 = BRG enabled
3940 *
3941 * 0110 1001
3942 */
3943 wr_reg8(info, CCR, 0x69);
3944
3945 msc_set_vcr(info);
3946
3947 tx_set_idle(info);
3948
3949 /* SCR (serial control)
3950 *
3951 * 15 1=tx req on FIFO half empty
3952 * 14 1=rx req on FIFO half full
3953 * 13 tx data IRQ enable
3954 * 12 tx idle IRQ enable
3955 * 11 rx break on IRQ enable
3956 * 10 rx data IRQ enable
3957 * 09 rx break off IRQ enable
3958 * 08 overrun IRQ enable
3959 * 07 DSR IRQ enable
3960 * 06 CTS IRQ enable
3961 * 05 DCD IRQ enable
3962 * 04 RI IRQ enable
3963 * 03 reserved, must be zero
3964 * 02 1=txd->rxd internal loopback enable
3965 * 01 reserved, must be zero
3966 * 00 1=master IRQ enable
3967 */
3968 val = BIT15 + BIT14 + BIT0;
3969 wr_reg16(info, SCR, val);
3970
3971 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
3972
3973 set_rate(info, info->params.data_rate * 16);
3974
3975 if (info->params.loopback)
3976 enable_loopback(info);
3977}
3978
3979static void hdlc_mode(struct slgt_info *info)
3980{
3981 unsigned short val;
3982
3983 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3984 tx_stop(info);
3985 rx_stop(info);
3986
3987 /* TCR (tx control)
3988 *
3989 * 15..13 mode, 000=HDLC 001=raw sync
3990 * 12..10 encoding
3991 * 09 CRC enable
3992 * 08 CRC32
3993 * 07 1=RTS driver control
3994 * 06 preamble enable
3995 * 05..04 preamble length
3996 * 03 share open/close flag
3997 * 02 reset
3998 * 01 enable
3999 * 00 auto-CTS enable
4000 */
4001 val = 0;
4002
4003 if (info->params.mode == MGSL_MODE_RAW)
4004 val |= BIT13;
4005 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4006 val |= BIT7;
4007
4008 switch(info->params.encoding)
4009 {
4010 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4011 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4012 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4013 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4014 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4015 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4016 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4017 }
4018
4019 switch (info->params.crc_type)
4020 {
4021 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4022 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4023 }
4024
4025 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4026 val |= BIT6;
4027
4028 switch (info->params.preamble_length)
4029 {
4030 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4031 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4032 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4033 }
4034
4035 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4036 val |= BIT0;
4037
4038 wr_reg16(info, TCR, val);
4039
4040 /* TPR (transmit preamble) */
4041
4042 switch (info->params.preamble)
4043 {
4044 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4045 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4046 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4047 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4048 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4049 default: val = 0x7e; break;
4050 }
4051 wr_reg8(info, TPR, (unsigned char)val);
4052
4053 /* RCR (rx control)
4054 *
4055 * 15..13 mode, 000=HDLC 001=raw sync
4056 * 12..10 encoding
4057 * 09 CRC enable
4058 * 08 CRC32
4059 * 07..03 reserved, must be 0
4060 * 02 reset
4061 * 01 enable
4062 * 00 auto-DCD enable
4063 */
4064 val = 0;
4065
4066 if (info->params.mode == MGSL_MODE_RAW)
4067 val |= BIT13;
4068
4069 switch(info->params.encoding)
4070 {
4071 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4072 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4073 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4074 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4075 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4076 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4077 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4078 }
4079
4080 switch (info->params.crc_type)
4081 {
4082 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4083 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4084 }
4085
4086 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4087 val |= BIT0;
4088
4089 wr_reg16(info, RCR, val);
4090
4091 /* CCR (clock control)
4092 *
4093 * 07..05 tx clock source
4094 * 04..02 rx clock source
4095 * 01 auxclk enable
4096 * 00 BRG enable
4097 */
4098 val = 0;
4099
4100 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4101 {
4102 // when RxC source is DPLL, BRG generates 16X DPLL
4103 // reference clock, so take TxC from BRG/16 to get
4104 // transmit clock at actual data rate
4105 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4106 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4107 else
4108 val |= BIT6; /* 010, txclk = BRG */
4109 }
4110 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4111 val |= BIT7; /* 100, txclk = DPLL Input */
4112 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4113 val |= BIT5; /* 001, txclk = RXC Input */
4114
4115 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4116 val |= BIT3; /* 010, rxclk = BRG */
4117 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4118 val |= BIT4; /* 100, rxclk = DPLL */
4119 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4120 val |= BIT2; /* 001, rxclk = TXC Input */
4121
4122 if (info->params.clock_speed)
4123 val |= BIT1 + BIT0;
4124
4125 wr_reg8(info, CCR, (unsigned char)val);
4126
4127 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4128 {
4129 // program DPLL mode
4130 switch(info->params.encoding)
4131 {
4132 case HDLC_ENCODING_BIPHASE_MARK:
4133 case HDLC_ENCODING_BIPHASE_SPACE:
4134 val = BIT7; break;
4135 case HDLC_ENCODING_BIPHASE_LEVEL:
4136 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4137 val = BIT7 + BIT6; break;
4138 default: val = BIT6; // NRZ encodings
4139 }
4140 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4141
4142 // DPLL requires a 16X reference clock from BRG
4143 set_rate(info, info->params.clock_speed * 16);
4144 }
4145 else
4146 set_rate(info, info->params.clock_speed);
4147
4148 tx_set_idle(info);
4149
4150 msc_set_vcr(info);
4151
4152 /* SCR (serial control)
4153 *
4154 * 15 1=tx req on FIFO half empty
4155 * 14 1=rx req on FIFO half full
4156 * 13 tx data IRQ enable
4157 * 12 tx idle IRQ enable
4158 * 11 underrun IRQ enable
4159 * 10 rx data IRQ enable
4160 * 09 rx idle IRQ enable
4161 * 08 overrun IRQ enable
4162 * 07 DSR IRQ enable
4163 * 06 CTS IRQ enable
4164 * 05 DCD IRQ enable
4165 * 04 RI IRQ enable
4166 * 03 reserved, must be zero
4167 * 02 1=txd->rxd internal loopback enable
4168 * 01 reserved, must be zero
4169 * 00 1=master IRQ enable
4170 */
4171 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4172
4173 if (info->params.loopback)
4174 enable_loopback(info);
4175}
4176
4177/*
4178 * set transmit idle mode
4179 */
4180static void tx_set_idle(struct slgt_info *info)
4181{
4182 unsigned char val = 0xff;
4183
4184 switch(info->idle_mode)
4185 {
4186 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4187 case HDLC_TXIDLE_ALT_ZEROS_ONES: val = 0xaa; break;
4188 case HDLC_TXIDLE_ZEROS: val = 0x00; break;
4189 case HDLC_TXIDLE_ONES: val = 0xff; break;
4190 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4191 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4192 case HDLC_TXIDLE_MARK: val = 0xff; break;
4193 }
4194
4195 wr_reg8(info, TIR, val);
4196}
4197
4198/*
4199 * get state of V24 status (input) signals
4200 */
4201static void get_signals(struct slgt_info *info)
4202{
4203 unsigned short status = rd_reg16(info, SSR);
4204
4205 /* clear all serial signals except DTR and RTS */
4206 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4207
4208 if (status & BIT3)
4209 info->signals |= SerialSignal_DSR;
4210 if (status & BIT2)
4211 info->signals |= SerialSignal_CTS;
4212 if (status & BIT1)
4213 info->signals |= SerialSignal_DCD;
4214 if (status & BIT0)
4215 info->signals |= SerialSignal_RI;
4216}
4217
4218/*
4219 * set V.24 Control Register based on current configuration
4220 */
4221static void msc_set_vcr(struct slgt_info *info)
4222{
4223 unsigned char val = 0;
4224
4225 /* VCR (V.24 control)
4226 *
4227 * 07..04 serial IF select
4228 * 03 DTR
4229 * 02 RTS
4230 * 01 LL
4231 * 00 RL
4232 */
4233
4234 switch(info->if_mode & MGSL_INTERFACE_MASK)
4235 {
4236 case MGSL_INTERFACE_RS232:
4237 val |= BIT5; /* 0010 */
4238 break;
4239 case MGSL_INTERFACE_V35:
4240 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4241 break;
4242 case MGSL_INTERFACE_RS422:
4243 val |= BIT6; /* 0100 */
4244 break;
4245 }
4246
4247 if (info->signals & SerialSignal_DTR)
4248 val |= BIT3;
4249 if (info->signals & SerialSignal_RTS)
4250 val |= BIT2;
4251 if (info->if_mode & MGSL_INTERFACE_LL)
4252 val |= BIT1;
4253 if (info->if_mode & MGSL_INTERFACE_RL)
4254 val |= BIT0;
4255 wr_reg8(info, VCR, val);
4256}
4257
4258/*
4259 * set state of V24 control (output) signals
4260 */
4261static void set_signals(struct slgt_info *info)
4262{
4263 unsigned char val = rd_reg8(info, VCR);
4264 if (info->signals & SerialSignal_DTR)
4265 val |= BIT3;
4266 else
4267 val &= ~BIT3;
4268 if (info->signals & SerialSignal_RTS)
4269 val |= BIT2;
4270 else
4271 val &= ~BIT2;
4272 wr_reg8(info, VCR, val);
4273}
4274
4275/*
4276 * free range of receive DMA buffers (i to last)
4277 */
4278static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4279{
4280 int done = 0;
4281
4282 while(!done) {
4283 /* reset current buffer for reuse */
4284 info->rbufs[i].status = 0;
4285 if (info->params.mode == MGSL_MODE_RAW)
4286 set_desc_count(info->rbufs[i], info->raw_rx_size);
4287 else
4288 set_desc_count(info->rbufs[i], DMABUFSIZE);
4289
4290 if (i == last)
4291 done = 1;
4292 if (++i == info->rbuf_count)
4293 i = 0;
4294 }
4295 info->rbuf_current = i;
4296}
4297
4298/*
4299 * mark all receive DMA buffers as free
4300 */
4301static void reset_rbufs(struct slgt_info *info)
4302{
4303 free_rbufs(info, 0, info->rbuf_count - 1);
4304}
4305
4306/*
4307 * pass receive HDLC frame to upper layer
4308 *
4309 * return 1 if frame available, otherwise 0
4310 */
4311static int rx_get_frame(struct slgt_info *info)
4312{
4313 unsigned int start, end;
4314 unsigned short status;
4315 unsigned int framesize = 0;
4316 int rc = 0;
4317 unsigned long flags;
4318 struct tty_struct *tty = info->tty;
4319 unsigned char addr_field = 0xff;
4320
4321check_again:
4322
4323 framesize = 0;
4324 addr_field = 0xff;
4325 start = end = info->rbuf_current;
4326
4327 for (;;) {
4328 if (!desc_complete(info->rbufs[end]))
4329 goto cleanup;
4330
4331 if (framesize == 0 && info->params.addr_filter != 0xff)
4332 addr_field = info->rbufs[end].buf[0];
4333
4334 framesize += desc_count(info->rbufs[end]);
4335
4336 if (desc_eof(info->rbufs[end]))
4337 break;
4338
4339 if (++end == info->rbuf_count)
4340 end = 0;
4341
4342 if (end == info->rbuf_current) {
4343 if (info->rx_enabled){
4344 spin_lock_irqsave(&info->lock,flags);
4345 rx_start(info);
4346 spin_unlock_irqrestore(&info->lock,flags);
4347 }
4348 goto cleanup;
4349 }
4350 }
4351
4352 /* status
4353 *
4354 * 15 buffer complete
4355 * 14..06 reserved
4356 * 05..04 residue
4357 * 02 eof (end of frame)
4358 * 01 CRC error
4359 * 00 abort
4360 */
4361 status = desc_status(info->rbufs[end]);
4362
4363 /* ignore CRC bit if not using CRC (bit is undefined) */
4364 if (info->params.crc_type == HDLC_CRC_NONE)
4365 status &= ~BIT1;
4366
4367 if (framesize == 0 ||
4368 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4369 free_rbufs(info, start, end);
4370 goto check_again;
4371 }
4372
4373 if (framesize < 2 || status & (BIT1+BIT0)) {
4374 if (framesize < 2 || (status & BIT0))
4375 info->icount.rxshort++;
4376 else
4377 info->icount.rxcrc++;
4378 framesize = 0;
4379
4380#ifdef CONFIG_HDLC
4381 {
4382 struct net_device_stats *stats = hdlc_stats(info->netdev);
4383 stats->rx_errors++;
4384 stats->rx_frame_errors++;
4385 }
4386#endif
4387 } else {
4388 /* adjust frame size for CRC, if any */
4389 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4390 framesize -= 2;
4391 else if (info->params.crc_type == HDLC_CRC_32_CCITT)
4392 framesize -= 4;
4393 }
4394
4395 DBGBH(("%s rx frame status=%04X size=%d\n",
4396 info->device_name, status, framesize));
4397 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4398
4399 if (framesize) {
4400 if (framesize > info->max_frame_size)
4401 info->icount.rxlong++;
4402 else {
4403 /* copy dma buffer(s) to contiguous temp buffer */
4404 int copy_count = framesize;
4405 int i = start;
4406 unsigned char *p = info->tmp_rbuf;
4407 info->tmp_rbuf_count = framesize;
4408
4409 info->icount.rxok++;
4410
4411 while(copy_count) {
4412 int partial_count = min(copy_count, DMABUFSIZE);
4413 memcpy(p, info->rbufs[i].buf, partial_count);
4414 p += partial_count;
4415 copy_count -= partial_count;
4416 if (++i == info->rbuf_count)
4417 i = 0;
4418 }
4419
4420#ifdef CONFIG_HDLC
4421 if (info->netcount)
4422 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4423 else
4424#endif
4425 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4426 }
4427 }
4428 free_rbufs(info, start, end);
4429 rc = 1;
4430
4431cleanup:
4432 return rc;
4433}
4434
4435/*
4436 * pass receive buffer (RAW synchronous mode) to tty layer
4437 * return 1 if buffer available, otherwise 0
4438 */
4439static int rx_get_buf(struct slgt_info *info)
4440{
4441 unsigned int i = info->rbuf_current;
4442
4443 if (!desc_complete(info->rbufs[i]))
4444 return 0;
4445 DBGDATA(info, info->rbufs[i].buf, desc_count(info->rbufs[i]), "rx");
4446 DBGINFO(("rx_get_buf size=%d\n", desc_count(info->rbufs[i])));
4447 ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4448 info->flag_buf, desc_count(info->rbufs[i]));
4449 free_rbufs(info, i, i);
4450 return 1;
4451}
4452
4453static void reset_tbufs(struct slgt_info *info)
4454{
4455 unsigned int i;
4456 info->tbuf_current = 0;
4457 for (i=0 ; i < info->tbuf_count ; i++) {
4458 info->tbufs[i].status = 0;
4459 info->tbufs[i].count = 0;
4460 }
4461}
4462
4463/*
4464 * return number of free transmit DMA buffers
4465 */
4466static unsigned int free_tbuf_count(struct slgt_info *info)
4467{
4468 unsigned int count = 0;
4469 unsigned int i = info->tbuf_current;
4470
4471 do
4472 {
4473 if (desc_count(info->tbufs[i]))
4474 break; /* buffer in use */
4475 ++count;
4476 if (++i == info->tbuf_count)
4477 i=0;
4478 } while (i != info->tbuf_current);
4479
4480 /* last buffer with zero count may be in use, assume it is */
4481 if (count)
4482 --count;
4483
4484 return count;
4485}
4486
4487/*
4488 * load transmit DMA buffer(s) with data
4489 */
4490static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4491{
4492 unsigned short count;
4493 unsigned int i;
4494 struct slgt_desc *d;
4495
4496 if (size == 0)
4497 return;
4498
4499 DBGDATA(info, buf, size, "tx");
4500
4501 info->tbuf_start = i = info->tbuf_current;
4502
4503 while (size) {
4504 d = &info->tbufs[i];
4505 if (++i == info->tbuf_count)
4506 i = 0;
4507
4508 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4509 memcpy(d->buf, buf, count);
4510
4511 size -= count;
4512 buf += count;
4513
4514 if (!size && info->params.mode != MGSL_MODE_RAW)
4515 set_desc_eof(*d, 1); /* HDLC: set EOF of last desc */
4516 else
4517 set_desc_eof(*d, 0);
4518
4519 set_desc_count(*d, count);
4520 }
4521
4522 info->tbuf_current = i;
4523}
4524
4525static int register_test(struct slgt_info *info)
4526{
4527 static unsigned short patterns[] =
4528 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4529 static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4530 unsigned int i;
4531 int rc = 0;
4532
4533 for (i=0 ; i < count ; i++) {
4534 wr_reg16(info, TIR, patterns[i]);
4535 wr_reg16(info, BDR, patterns[(i+1)%count]);
4536 if ((rd_reg16(info, TIR) != patterns[i]) ||
4537 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4538 rc = -ENODEV;
4539 break;
4540 }
4541 }
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame^]4542 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4543 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4544 return rc;
4545}
4546
4547static int irq_test(struct slgt_info *info)
4548{
4549 unsigned long timeout;
4550 unsigned long flags;
4551 struct tty_struct *oldtty = info->tty;
4552 u32 speed = info->params.data_rate;
4553
4554 info->params.data_rate = 921600;
4555 info->tty = NULL;
4556
4557 spin_lock_irqsave(&info->lock, flags);
4558 async_mode(info);
4559 slgt_irq_on(info, IRQ_TXIDLE);
4560
4561 /* enable transmitter */
4562 wr_reg16(info, TCR,
4563 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4564
4565 /* write one byte and wait for tx idle */
4566 wr_reg16(info, TDR, 0);
4567
4568 /* assume failure */
4569 info->init_error = DiagStatus_IrqFailure;
4570 info->irq_occurred = FALSE;
4571
4572 spin_unlock_irqrestore(&info->lock, flags);
4573
4574 timeout=100;
4575 while(timeout-- && !info->irq_occurred)
4576 msleep_interruptible(10);
4577
4578 spin_lock_irqsave(&info->lock,flags);
4579 reset_port(info);
4580 spin_unlock_irqrestore(&info->lock,flags);
4581
4582 info->params.data_rate = speed;
4583 info->tty = oldtty;
4584
4585 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4586 return info->irq_occurred ? 0 : -ENODEV;
4587}
4588
4589static int loopback_test_rx(struct slgt_info *info)
4590{
4591 unsigned char *src, *dest;
4592 int count;
4593
4594 if (desc_complete(info->rbufs[0])) {
4595 count = desc_count(info->rbufs[0]);
4596 src = info->rbufs[0].buf;
4597 dest = info->tmp_rbuf;
4598
4599 for( ; count ; count-=2, src+=2) {
4600 /* src=data byte (src+1)=status byte */
4601 if (!(*(src+1) & (BIT9 + BIT8))) {
4602 *dest = *src;
4603 dest++;
4604 info->tmp_rbuf_count++;
4605 }
4606 }
4607 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4608 return 1;
4609 }
4610 return 0;
4611}
4612
4613static int loopback_test(struct slgt_info *info)
4614{
4615#define TESTFRAMESIZE 20
4616
4617 unsigned long timeout;
4618 u16 count = TESTFRAMESIZE;
4619 unsigned char buf[TESTFRAMESIZE];
4620 int rc = -ENODEV;
4621 unsigned long flags;
4622
4623 struct tty_struct *oldtty = info->tty;
4624 MGSL_PARAMS params;
4625
4626 memcpy(&params, &info->params, sizeof(params));
4627
4628 info->params.mode = MGSL_MODE_ASYNC;
4629 info->params.data_rate = 921600;
4630 info->params.loopback = 1;
4631 info->tty = NULL;
4632
4633 /* build and send transmit frame */
4634 for (count = 0; count < TESTFRAMESIZE; ++count)
4635 buf[count] = (unsigned char)count;
4636
4637 info->tmp_rbuf_count = 0;
4638 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4639
4640 /* program hardware for HDLC and enabled receiver */
4641 spin_lock_irqsave(&info->lock,flags);
4642 async_mode(info);
4643 rx_start(info);
4644 info->tx_count = count;
4645 tx_load(info, buf, count);
4646 tx_start(info);
4647 spin_unlock_irqrestore(&info->lock, flags);
4648
4649 /* wait for receive complete */
4650 for (timeout = 100; timeout; --timeout) {
4651 msleep_interruptible(10);
4652 if (loopback_test_rx(info)) {
4653 rc = 0;
4654 break;
4655 }
4656 }
4657
4658 /* verify received frame length and contents */
4659 if (!rc && (info->tmp_rbuf_count != count ||
4660 memcmp(buf, info->tmp_rbuf, count))) {
4661 rc = -ENODEV;
4662 }
4663
4664 spin_lock_irqsave(&info->lock,flags);
4665 reset_adapter(info);
4666 spin_unlock_irqrestore(&info->lock,flags);
4667
4668 memcpy(&info->params, &params, sizeof(info->params));
4669 info->tty = oldtty;
4670
4671 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4672 return rc;
4673}
4674
4675static int adapter_test(struct slgt_info *info)
4676{
4677 DBGINFO(("testing %s\n", info->device_name));
4678 if ((info->init_error = register_test(info)) < 0) {
4679 printk("register test failure %s addr=%08X\n",
4680 info->device_name, info->phys_reg_addr);
4681 } else if ((info->init_error = irq_test(info)) < 0) {
4682 printk("IRQ test failure %s IRQ=%d\n",
4683 info->device_name, info->irq_level);
4684 } else if ((info->init_error = loopback_test(info)) < 0) {
4685 printk("loopback test failure %s\n", info->device_name);
4686 }
4687 return info->init_error;
4688}
4689
4690/*
4691 * transmit timeout handler
4692 */
4693static void tx_timeout(unsigned long context)
4694{
4695 struct slgt_info *info = (struct slgt_info*)context;
4696 unsigned long flags;
4697
4698 DBGINFO(("%s tx_timeout\n", info->device_name));
4699 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4700 info->icount.txtimeout++;
4701 }
4702 spin_lock_irqsave(&info->lock,flags);
4703 info->tx_active = 0;
4704 info->tx_count = 0;
4705 spin_unlock_irqrestore(&info->lock,flags);
4706
4707#ifdef CONFIG_HDLC
4708 if (info->netcount)
4709 hdlcdev_tx_done(info);
4710 else
4711#endif
4712 bh_transmit(info);
4713}
4714
4715/*
4716 * receive buffer polling timer
4717 */
4718static void rx_timeout(unsigned long context)
4719{
4720 struct slgt_info *info = (struct slgt_info*)context;
4721 unsigned long flags;
4722
4723 DBGINFO(("%s rx_timeout\n", info->device_name));
4724 spin_lock_irqsave(&info->lock, flags);
4725 info->pending_bh |= BH_RECEIVE;
4726 spin_unlock_irqrestore(&info->lock, flags);
4727 bh_handler(info);
4728}
4729