Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
Mike Frysinger | b03f203 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 2 | * dma.h - Blackfin DMA defines/structures/etc... |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 3 | * |
Mike Frysinger | b03f203 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 4 | * Copyright 2004-2008 Analog Devices Inc. |
| 5 | * Licensed under the GPL-2 or later. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _BLACKFIN_DMA_H_ |
| 9 | #define _BLACKFIN_DMA_H_ |
| 10 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 11 | #include <linux/interrupt.h> |
Mike Frysinger | 4c1ed6a | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 12 | #include <mach/dma.h> |
Mike Frysinger | d2e015d | 2009-10-09 22:18:12 +0000 | [diff] [blame] | 13 | #include <asm/atomic.h> |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 14 | #include <asm/blackfin.h> |
Mike Frysinger | 4c1ed6a | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 15 | #include <asm/page.h> |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 16 | |
| 17 | #define MAX_DMA_ADDRESS PAGE_OFFSET |
| 18 | |
Mike Frysinger | 00d2460 | 2009-10-20 17:20:21 +0000 | [diff] [blame^] | 19 | /* DMA_CONFIG Masks */ |
| 20 | #define DMAEN 0x0001 /* DMA Channel Enable */ |
| 21 | #define WNR 0x0002 /* Channel Direction (W/R*) */ |
| 22 | #define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ |
| 23 | #define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ |
| 24 | #define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ |
| 25 | #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ |
| 26 | #define RESTART 0x0020 /* DMA Buffer Clear */ |
| 27 | #define DI_SEL 0x0040 /* Data Interrupt Timing Select */ |
| 28 | #define DI_EN 0x0080 /* Data Interrupt Enable */ |
| 29 | #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ |
| 30 | #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ |
| 31 | #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ |
| 32 | #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ |
| 33 | #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ |
| 34 | #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ |
| 35 | #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ |
| 36 | #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ |
| 37 | #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ |
| 38 | #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ |
| 39 | #define NDSIZE 0x0f00 /* Next Descriptor Size */ |
| 40 | #define DMAFLOW 0x7000 /* Flow Control */ |
| 41 | #define DMAFLOW_STOP 0x0000 /* Stop Mode */ |
| 42 | #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ |
| 43 | #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ |
| 44 | #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ |
| 45 | #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ |
| 46 | |
| 47 | /* DMA_IRQ_STATUS Masks */ |
| 48 | #define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ |
| 49 | #define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ |
| 50 | #define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ |
| 51 | #define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 52 | |
| 53 | /*------------------------- |
| 54 | * config reg bits value |
| 55 | *-------------------------*/ |
Mike Frysinger | 00d2460 | 2009-10-20 17:20:21 +0000 | [diff] [blame^] | 56 | #define DATA_SIZE_8 0 |
| 57 | #define DATA_SIZE_16 1 |
| 58 | #define DATA_SIZE_32 2 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 59 | |
Mike Frysinger | 00d2460 | 2009-10-20 17:20:21 +0000 | [diff] [blame^] | 60 | #define DMA_FLOW_STOP 0 |
| 61 | #define DMA_FLOW_AUTO 1 |
| 62 | #define DMA_FLOW_ARRAY 4 |
| 63 | #define DMA_FLOW_SMALL 6 |
| 64 | #define DMA_FLOW_LARGE 7 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 65 | |
Mike Frysinger | 00d2460 | 2009-10-20 17:20:21 +0000 | [diff] [blame^] | 66 | #define DIMENSION_LINEAR 0 |
| 67 | #define DIMENSION_2D 1 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 68 | |
Mike Frysinger | 00d2460 | 2009-10-20 17:20:21 +0000 | [diff] [blame^] | 69 | #define DIR_READ 0 |
| 70 | #define DIR_WRITE 1 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 71 | |
Mike Frysinger | 00d2460 | 2009-10-20 17:20:21 +0000 | [diff] [blame^] | 72 | #define INTR_DISABLE 0 |
| 73 | #define INTR_ON_BUF 2 |
| 74 | #define INTR_ON_ROW 3 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 75 | |
Michael Hennerich | 2047e40 | 2008-01-22 15:29:18 +0800 | [diff] [blame] | 76 | #define DMA_NOSYNC_KEEP_DMA_BUF 0 |
Mike Frysinger | 00d2460 | 2009-10-20 17:20:21 +0000 | [diff] [blame^] | 77 | #define DMA_SYNC_RESTART 1 |
Michael Hennerich | 2047e40 | 2008-01-22 15:29:18 +0800 | [diff] [blame] | 78 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 79 | struct dmasg { |
Mike Frysinger | 6ab729d | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 80 | void *next_desc_addr; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 81 | unsigned long start_addr; |
| 82 | unsigned short cfg; |
| 83 | unsigned short x_count; |
| 84 | short x_modify; |
| 85 | unsigned short y_count; |
| 86 | short y_modify; |
| 87 | } __attribute__((packed)); |
| 88 | |
| 89 | struct dma_register { |
Mike Frysinger | 6ab729d | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 90 | void *next_desc_ptr; /* DMA Next Descriptor Pointer register */ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 91 | unsigned long start_addr; /* DMA Start address register */ |
| 92 | |
| 93 | unsigned short cfg; /* DMA Configuration register */ |
| 94 | unsigned short dummy1; /* DMA Configuration register */ |
| 95 | |
| 96 | unsigned long reserved; |
| 97 | |
| 98 | unsigned short x_count; /* DMA x_count register */ |
| 99 | unsigned short dummy2; |
| 100 | |
| 101 | short x_modify; /* DMA x_modify register */ |
| 102 | unsigned short dummy3; |
| 103 | |
| 104 | unsigned short y_count; /* DMA y_count register */ |
| 105 | unsigned short dummy4; |
| 106 | |
| 107 | short y_modify; /* DMA y_modify register */ |
| 108 | unsigned short dummy5; |
| 109 | |
Mike Frysinger | 6ab729d | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 110 | void *curr_desc_ptr; /* DMA Current Descriptor Pointer |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 111 | register */ |
Bryan Wu | 452af71 | 2007-10-22 00:02:14 +0800 | [diff] [blame] | 112 | unsigned long curr_addr_ptr; /* DMA Current Address Pointer |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 113 | register */ |
| 114 | unsigned short irq_status; /* DMA irq status register */ |
| 115 | unsigned short dummy6; |
| 116 | |
| 117 | unsigned short peripheral_map; /* DMA peripheral map register */ |
| 118 | unsigned short dummy7; |
| 119 | |
| 120 | unsigned short curr_x_count; /* DMA Current x-count register */ |
| 121 | unsigned short dummy8; |
| 122 | |
| 123 | unsigned long reserved2; |
| 124 | |
| 125 | unsigned short curr_y_count; /* DMA Current y-count register */ |
| 126 | unsigned short dummy9; |
| 127 | |
| 128 | unsigned long reserved3; |
| 129 | |
| 130 | }; |
| 131 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 132 | struct dma_channel { |
Michael McTernan | 99532fd | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 133 | const char *device_id; |
Mike Frysinger | d2e015d | 2009-10-09 22:18:12 +0000 | [diff] [blame] | 134 | atomic_t chan_status; |
Mike Frysinger | 4ce1873 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 135 | volatile struct dma_register *regs; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 136 | struct dmasg *sg; /* large mode descriptor */ |
Michael Hennerich | a2ba8b1 | 2008-10-28 18:19:29 +0800 | [diff] [blame] | 137 | unsigned int irq; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 138 | void *data; |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 139 | #ifdef CONFIG_PM |
| 140 | unsigned short saved_peripheral_map; |
| 141 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 142 | }; |
| 143 | |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 144 | #ifdef CONFIG_PM |
| 145 | int blackfin_dma_suspend(void); |
| 146 | void blackfin_dma_resume(void); |
| 147 | #endif |
| 148 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 149 | /******************************************************************************* |
| 150 | * DMA API's |
| 151 | *******************************************************************************/ |
Mike Frysinger | 9c417a4 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 152 | extern struct dma_channel dma_ch[MAX_DMA_CHANNELS]; |
| 153 | extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS]; |
| 154 | extern int channel2irq(unsigned int channel); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 155 | |
Mike Frysinger | 9c417a4 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 156 | static inline void set_dma_start_addr(unsigned int channel, unsigned long addr) |
| 157 | { |
| 158 | dma_ch[channel].regs->start_addr = addr; |
| 159 | } |
Mike Frysinger | 6ab729d | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 160 | static inline void set_dma_next_desc_addr(unsigned int channel, void *addr) |
Mike Frysinger | 9c417a4 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 161 | { |
| 162 | dma_ch[channel].regs->next_desc_ptr = addr; |
| 163 | } |
Mike Frysinger | 6ab729d | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 164 | static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr) |
Mike Frysinger | 9c417a4 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 165 | { |
| 166 | dma_ch[channel].regs->curr_desc_ptr = addr; |
| 167 | } |
| 168 | static inline void set_dma_x_count(unsigned int channel, unsigned short x_count) |
| 169 | { |
| 170 | dma_ch[channel].regs->x_count = x_count; |
| 171 | } |
| 172 | static inline void set_dma_y_count(unsigned int channel, unsigned short y_count) |
| 173 | { |
| 174 | dma_ch[channel].regs->y_count = y_count; |
| 175 | } |
| 176 | static inline void set_dma_x_modify(unsigned int channel, short x_modify) |
| 177 | { |
| 178 | dma_ch[channel].regs->x_modify = x_modify; |
| 179 | } |
| 180 | static inline void set_dma_y_modify(unsigned int channel, short y_modify) |
| 181 | { |
| 182 | dma_ch[channel].regs->y_modify = y_modify; |
| 183 | } |
| 184 | static inline void set_dma_config(unsigned int channel, unsigned short config) |
| 185 | { |
| 186 | dma_ch[channel].regs->cfg = config; |
| 187 | } |
| 188 | static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr) |
| 189 | { |
| 190 | dma_ch[channel].regs->curr_addr_ptr = addr; |
| 191 | } |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 192 | |
Mike Frysinger | 9c417a4 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 193 | static inline unsigned short |
| 194 | set_bfin_dma_config(char direction, char flow_mode, |
| 195 | char intr_mode, char dma_mode, char width, char syncmode) |
| 196 | { |
| 197 | return (direction << 1) | (width << 2) | (dma_mode << 4) | |
| 198 | (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5); |
| 199 | } |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 200 | |
Mike Frysinger | 9c417a4 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 201 | static inline unsigned short get_dma_curr_irqstat(unsigned int channel) |
| 202 | { |
| 203 | return dma_ch[channel].regs->irq_status; |
| 204 | } |
| 205 | static inline unsigned short get_dma_curr_xcount(unsigned int channel) |
| 206 | { |
| 207 | return dma_ch[channel].regs->curr_x_count; |
| 208 | } |
| 209 | static inline unsigned short get_dma_curr_ycount(unsigned int channel) |
| 210 | { |
| 211 | return dma_ch[channel].regs->curr_y_count; |
| 212 | } |
Mike Frysinger | 6ab729d | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 213 | static inline void *get_dma_next_desc_ptr(unsigned int channel) |
Mike Frysinger | 9c417a4 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 214 | { |
| 215 | return dma_ch[channel].regs->next_desc_ptr; |
| 216 | } |
Mike Frysinger | 6ab729d | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 217 | static inline void *get_dma_curr_desc_ptr(unsigned int channel) |
Mike Frysinger | 9c417a4 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 218 | { |
| 219 | return dma_ch[channel].regs->curr_desc_ptr; |
| 220 | } |
Mike Frysinger | 71f5ca3 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 221 | static inline unsigned short get_dma_config(unsigned int channel) |
| 222 | { |
| 223 | return dma_ch[channel].regs->cfg; |
| 224 | } |
Mike Frysinger | 9c417a4 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 225 | static inline unsigned long get_dma_curr_addr(unsigned int channel) |
| 226 | { |
| 227 | return dma_ch[channel].regs->curr_addr_ptr; |
| 228 | } |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 229 | |
Mike Frysinger | 9c417a4 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 230 | static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize) |
| 231 | { |
Sonic Zhang | ea8538a | 2009-06-01 00:49:32 -0400 | [diff] [blame] | 232 | /* Make sure the internal data buffers in the core are drained |
| 233 | * so that the DMA descriptors are completely written when the |
| 234 | * DMA engine goes to fetch them below. |
| 235 | */ |
| 236 | SSYNC(); |
| 237 | |
| 238 | dma_ch[channel].regs->next_desc_ptr = sg; |
Mike Frysinger | d41e800 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 239 | dma_ch[channel].regs->cfg = |
| 240 | (dma_ch[channel].regs->cfg & ~(0xf << 8)) | |
| 241 | ((ndsize & 0xf) << 8); |
Mike Frysinger | 9c417a4 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 242 | } |
| 243 | |
| 244 | static inline int dma_channel_active(unsigned int channel) |
| 245 | { |
Mike Frysinger | d2e015d | 2009-10-09 22:18:12 +0000 | [diff] [blame] | 246 | return atomic_read(&dma_ch[channel].chan_status); |
Mike Frysinger | 9c417a4 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 247 | } |
| 248 | |
| 249 | static inline void disable_dma(unsigned int channel) |
| 250 | { |
| 251 | dma_ch[channel].regs->cfg &= ~DMAEN; |
| 252 | SSYNC(); |
Mike Frysinger | 9c417a4 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 253 | } |
| 254 | static inline void enable_dma(unsigned int channel) |
| 255 | { |
| 256 | dma_ch[channel].regs->curr_x_count = 0; |
| 257 | dma_ch[channel].regs->curr_y_count = 0; |
| 258 | dma_ch[channel].regs->cfg |= DMAEN; |
Mike Frysinger | 9c417a4 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 259 | } |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 260 | void free_dma(unsigned int channel); |
Michael McTernan | 99532fd | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 261 | int request_dma(unsigned int channel, const char *device_id); |
Mike Frysinger | 9c417a4 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 262 | int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data); |
| 263 | |
| 264 | static inline void dma_disable_irq(unsigned int channel) |
| 265 | { |
| 266 | disable_irq(dma_ch[channel].irq); |
| 267 | } |
| 268 | static inline void dma_enable_irq(unsigned int channel) |
| 269 | { |
| 270 | enable_irq(dma_ch[channel].irq); |
| 271 | } |
| 272 | static inline void clear_dma_irqstat(unsigned int channel) |
| 273 | { |
| 274 | dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR; |
| 275 | } |
| 276 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 277 | void *dma_memcpy(void *dest, const void *src, size_t count); |
| 278 | void *safe_dma_memcpy(void *dest, const void *src, size_t count); |
Mike Frysinger | dd3dd38 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 279 | void blackfin_dma_early_init(void); |
Robin Getz | fecbd73 | 2009-04-23 20:49:43 +0000 | [diff] [blame] | 280 | void early_dma_memcpy(void *dest, const void *src, size_t count); |
| 281 | void early_dma_memcpy_done(void); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 282 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 283 | #endif |