blob: 2c024523c6222bb2100ed2c34eff39ba300c1912 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001 /***************************************************************************\
2|* *|
3|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
4|* *|
5|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6|* international laws. Users and possessors of this source code are *|
7|* hereby granted a nonexclusive, royalty-free copyright license to *|
8|* use this code in individual and commercial software. *|
9|* *|
10|* Any use of this source code must include, in the user documenta- *|
11|* tion and internal comments to the code, notices to the end user *|
12|* as follows: *|
13|* *|
14|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
15|* *|
16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. This source code is a "commercial *|
29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial *|
31|* computer software documentation," as such terms are used in *|
32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35|* all U.S. Government End Users acquire the source code with only *|
36|* those rights set forth herein. *|
37|* *|
38 \***************************************************************************/
39
40/*
41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43 * where the source code is provided "as is" without warranty of any kind.
44 * The only usage restriction is for the copyright notices to be retained
45 * whenever code is used.
46 *
47 * Antonino Daplas <adaplas@pol.net> 2005-03-11
48 */
49
50#include <video/vga.h>
51#include <linux/delay.h>
52#include <linux/pci.h>
53#include "nv_type.h"
54#include "nv_local.h"
55#include "nv_proto.h"
56/*
57 * Override VGA I/O routines.
58 */
59void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value)
60{
61 VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
62 VGA_WR08(par->PCIO, par->IOBase + 0x05, value);
63}
64u8 NVReadCrtc(struct nvidia_par *par, u8 index)
65{
66 VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
67 return (VGA_RD08(par->PCIO, par->IOBase + 0x05));
68}
69void NVWriteGr(struct nvidia_par *par, u8 index, u8 value)
70{
71 VGA_WR08(par->PVIO, VGA_GFX_I, index);
72 VGA_WR08(par->PVIO, VGA_GFX_D, value);
73}
74u8 NVReadGr(struct nvidia_par *par, u8 index)
75{
76 VGA_WR08(par->PVIO, VGA_GFX_I, index);
77 return (VGA_RD08(par->PVIO, VGA_GFX_D));
78}
79void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value)
80{
81 VGA_WR08(par->PVIO, VGA_SEQ_I, index);
82 VGA_WR08(par->PVIO, VGA_SEQ_D, value);
83}
84u8 NVReadSeq(struct nvidia_par *par, u8 index)
85{
86 VGA_WR08(par->PVIO, VGA_SEQ_I, index);
87 return (VGA_RD08(par->PVIO, VGA_SEQ_D));
88}
89void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value)
90{
91 volatile u8 tmp;
92
93 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
94 if (par->paletteEnabled)
95 index &= ~0x20;
96 else
97 index |= 0x20;
98 VGA_WR08(par->PCIO, VGA_ATT_IW, index);
99 VGA_WR08(par->PCIO, VGA_ATT_W, value);
100}
101u8 NVReadAttr(struct nvidia_par *par, u8 index)
102{
103 volatile u8 tmp;
104
105 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
106 if (par->paletteEnabled)
107 index &= ~0x20;
108 else
109 index |= 0x20;
110 VGA_WR08(par->PCIO, VGA_ATT_IW, index);
111 return (VGA_RD08(par->PCIO, VGA_ATT_R));
112}
113void NVWriteMiscOut(struct nvidia_par *par, u8 value)
114{
115 VGA_WR08(par->PVIO, VGA_MIS_W, value);
116}
117u8 NVReadMiscOut(struct nvidia_par *par)
118{
119 return (VGA_RD08(par->PVIO, VGA_MIS_R));
120}
121#if 0
122void NVEnablePalette(struct nvidia_par *par)
123{
124 volatile u8 tmp;
125
126 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
127 VGA_WR08(par->PCIO, VGA_ATT_IW, 0x00);
128 par->paletteEnabled = 1;
129}
130void NVDisablePalette(struct nvidia_par *par)
131{
132 volatile u8 tmp;
133
134 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
135 VGA_WR08(par->PCIO, VGA_ATT_IW, 0x20);
136 par->paletteEnabled = 0;
137}
138#endif /* 0 */
139void NVWriteDacMask(struct nvidia_par *par, u8 value)
140{
141 VGA_WR08(par->PDIO, VGA_PEL_MSK, value);
142}
143#if 0
144u8 NVReadDacMask(struct nvidia_par *par)
145{
146 return (VGA_RD08(par->PDIO, VGA_PEL_MSK));
147}
148#endif /* 0 */
149void NVWriteDacReadAddr(struct nvidia_par *par, u8 value)
150{
151 VGA_WR08(par->PDIO, VGA_PEL_IR, value);
152}
153void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value)
154{
155 VGA_WR08(par->PDIO, VGA_PEL_IW, value);
156}
157void NVWriteDacData(struct nvidia_par *par, u8 value)
158{
159 VGA_WR08(par->PDIO, VGA_PEL_D, value);
160}
161u8 NVReadDacData(struct nvidia_par *par)
162{
163 return (VGA_RD08(par->PDIO, VGA_PEL_D));
164}
165
166static int NVIsConnected(struct nvidia_par *par, int output)
167{
168 volatile u32 __iomem *PRAMDAC = par->PRAMDAC0;
169 u32 reg52C, reg608;
170 int present;
171
172 if (output)
173 PRAMDAC += 0x800;
174
175 reg52C = NV_RD32(PRAMDAC, 0x052C);
176 reg608 = NV_RD32(PRAMDAC, 0x0608);
177
178 NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
179
180 NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
181 msleep(1);
182 NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
183
184 NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140);
185 NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
186 0x00001000);
187
188 msleep(1);
189
190 present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0;
191
192 if (present)
Benjamin Herrenschmidt85f15032005-11-07 01:00:30 -0800193 printk("nvidiafb: CRTC%i analog found\n", output);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 else
Benjamin Herrenschmidt85f15032005-11-07 01:00:30 -0800195 printk("nvidiafb: CRTC%i analog not found\n", output);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196
197 NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) &
198 0x0000EFFF);
199
200 NV_WR32(PRAMDAC, 0x052C, reg52C);
201 NV_WR32(PRAMDAC, 0x0608, reg608);
202
203 return present;
204}
205
206static void NVSelectHeadRegisters(struct nvidia_par *par, int head)
207{
208 if (head) {
209 par->PCIO = par->PCIO0 + 0x2000;
210 par->PCRTC = par->PCRTC0 + 0x800;
211 par->PRAMDAC = par->PRAMDAC0 + 0x800;
212 par->PDIO = par->PDIO0 + 0x2000;
213 } else {
214 par->PCIO = par->PCIO0;
215 par->PCRTC = par->PCRTC0;
216 par->PRAMDAC = par->PRAMDAC0;
217 par->PDIO = par->PDIO0;
218 }
219}
220
221static void nv4GetConfig(struct nvidia_par *par)
222{
223 if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
224 par->RamAmountKBytes =
225 ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
226 1024 * 2;
227 } else {
228 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) {
229 case 0:
230 par->RamAmountKBytes = 1024 * 32;
231 break;
232 case 1:
233 par->RamAmountKBytes = 1024 * 4;
234 break;
235 case 2:
236 par->RamAmountKBytes = 1024 * 8;
237 break;
238 case 3:
239 default:
240 par->RamAmountKBytes = 1024 * 16;
241 break;
242 }
243 }
244 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ?
245 14318 : 13500;
246 par->CURSOR = &par->PRAMIN[0x1E00];
247 par->MinVClockFreqKHz = 12000;
248 par->MaxVClockFreqKHz = 350000;
249}
250
251static void nv10GetConfig(struct nvidia_par *par)
252{
253 struct pci_dev *dev;
254 u32 implementation = par->Chipset & 0x0ff0;
255
256#ifdef __BIG_ENDIAN
257 /* turn on big endian register access */
258 if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) {
259 NV_WR32(par->PMC, 0x0004, 0x01000001);
260 mb();
261 }
262#endif
263
264 dev = pci_find_slot(0, 1);
265 if ((par->Chipset && 0xffff) == 0x01a0) {
266 int amt = 0;
267
268 pci_read_config_dword(dev, 0x7c, &amt);
269 par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
270 } else if ((par->Chipset & 0xffff) == 0x01f0) {
271 int amt = 0;
272
273 pci_read_config_dword(dev, 0x84, &amt);
274 par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
275 } else {
276 par->RamAmountKBytes =
277 (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10;
278 }
279
280 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ?
281 14318 : 13500;
282
283 if (par->twoHeads && (implementation != 0x0110)) {
284 if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22))
285 par->CrystalFreqKHz = 27000;
286 }
287
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288 par->CURSOR = NULL; /* can't set this here */
289 par->MinVClockFreqKHz = 12000;
290 par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000;
291}
292
293void NVCommonSetup(struct fb_info *info)
294{
295 struct nvidia_par *par = info->par;
296 struct fb_var_screeninfo var;
297 u16 implementation = par->Chipset & 0x0ff0;
298 u8 *edidA = NULL, *edidB = NULL;
299 struct fb_monspecs monitorA, monitorB;
300 struct fb_monspecs *monA = NULL, *monB = NULL;
301 int mobile = 0;
302 int tvA = 0;
303 int tvB = 0;
304 int FlatPanel = -1; /* really means the CRTC is slaved */
305 int Television = 0;
306
Benjamin Herrenschmidt85f15032005-11-07 01:00:30 -0800307 memset(&monitorA, 0, sizeof(struct fb_monspecs));
308 memset(&monitorB, 0, sizeof(struct fb_monspecs));
309
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310 par->PRAMIN = par->REGS + (0x00710000 / 4);
311 par->PCRTC0 = par->REGS + (0x00600000 / 4);
312 par->PRAMDAC0 = par->REGS + (0x00680000 / 4);
313 par->PFB = par->REGS + (0x00100000 / 4);
314 par->PFIFO = par->REGS + (0x00002000 / 4);
315 par->PGRAPH = par->REGS + (0x00400000 / 4);
316 par->PEXTDEV = par->REGS + (0x00101000 / 4);
317 par->PTIMER = par->REGS + (0x00009000 / 4);
318 par->PMC = par->REGS + (0x00000000 / 4);
319 par->FIFO = par->REGS + (0x00800000 / 4);
320
321 /* 8 bit registers */
322 par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000;
323 par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000;
324 par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000;
325
326 par->twoHeads = (par->Architecture >= NV_ARCH_10) &&
327 (implementation != 0x0100) &&
328 (implementation != 0x0150) &&
329 (implementation != 0x01A0) && (implementation != 0x0200);
330
331 par->fpScaler = (par->FpScale && par->twoHeads &&
332 (implementation != 0x0110));
333
334 par->twoStagePLL = (implementation == 0x0310) ||
335 (implementation == 0x0340) || (par->Architecture >= NV_ARCH_40);
336
337 par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) &&
338 (implementation != 0x0100);
339
340 par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020);
341
342 /* look for known laptop chips */
343 switch (par->Chipset & 0xffff) {
344 case 0x0112:
345 case 0x0174:
346 case 0x0175:
347 case 0x0176:
348 case 0x0177:
349 case 0x0179:
350 case 0x017C:
351 case 0x017D:
352 case 0x0186:
353 case 0x0187:
354 case 0x018D:
355 case 0x0286:
356 case 0x028C:
357 case 0x0316:
358 case 0x0317:
359 case 0x031A:
360 case 0x031B:
361 case 0x031C:
362 case 0x031D:
363 case 0x031E:
364 case 0x031F:
365 case 0x0324:
366 case 0x0325:
367 case 0x0328:
368 case 0x0329:
369 case 0x032C:
370 case 0x032D:
371 case 0x0347:
372 case 0x0348:
373 case 0x0349:
374 case 0x034B:
375 case 0x034C:
376 case 0x0160:
377 case 0x0166:
378 case 0x00C8:
379 case 0x00CC:
380 case 0x0144:
381 case 0x0146:
382 case 0x0147:
383 case 0x0148:
Benjamin Herrenschmidt0137ecf2006-01-09 20:51:27 -0800384 case 0x0098:
385 case 0x0099:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386 mobile = 1;
387 break;
388 default:
389 break;
390 }
391
392 if (par->Architecture == NV_ARCH_04)
393 nv4GetConfig(par);
394 else
395 nv10GetConfig(par);
396
397 NVSelectHeadRegisters(par, 0);
398
399 NVLockUnlock(par, 0);
400
401 par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0;
402
403 par->Television = 0;
404
405 nvidia_create_i2c_busses(par);
406 if (!par->twoHeads) {
407 par->CRTCnumber = 0;
Benjamin Herrenschmidt85f15032005-11-07 01:00:30 -0800408 if (nvidia_probe_i2c_connector(info, 1, &edidA))
409 nvidia_probe_of_connector(info, 1, &edidA);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410 if (edidA && !fb_parse_edid(edidA, &var)) {
411 printk("nvidiafb: EDID found from BUS1\n");
412 monA = &monitorA;
413 fb_edid_to_monspecs(edidA, monA);
414 FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
415
416 /* NV4 doesn't support FlatPanels */
417 if ((par->Chipset & 0x0fff) <= 0x0020)
418 FlatPanel = 0;
419 } else {
420 VGA_WR08(par->PCIO, 0x03D4, 0x28);
421 if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) {
422 VGA_WR08(par->PCIO, 0x03D4, 0x33);
423 if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01))
424 Television = 1;
425 FlatPanel = 1;
426 } else {
427 FlatPanel = 0;
428 }
429 printk("nvidiafb: HW is currently programmed for %s\n",
430 FlatPanel ? (Television ? "TV" : "DFP") :
431 "CRT");
432 }
433
434 if (par->FlatPanel == -1) {
435 par->FlatPanel = FlatPanel;
436 par->Television = Television;
437 } else {
438 printk("nvidiafb: Forcing display type to %s as "
439 "specified\n", par->FlatPanel ? "DFP" : "CRT");
440 }
441 } else {
442 u8 outputAfromCRTC, outputBfromCRTC;
443 int CRTCnumber = -1;
444 u8 slaved_on_A, slaved_on_B;
445 int analog_on_A, analog_on_B;
446 u32 oldhead;
447 u8 cr44;
448
449 if (implementation != 0x0110) {
450 if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100)
451 outputAfromCRTC = 1;
452 else
453 outputAfromCRTC = 0;
454 if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100)
455 outputBfromCRTC = 1;
456 else
457 outputBfromCRTC = 0;
458 analog_on_A = NVIsConnected(par, 0);
459 analog_on_B = NVIsConnected(par, 1);
460 } else {
461 outputAfromCRTC = 0;
462 outputBfromCRTC = 1;
463 analog_on_A = 0;
464 analog_on_B = 0;
465 }
466
467 VGA_WR08(par->PCIO, 0x03D4, 0x44);
468 cr44 = VGA_RD08(par->PCIO, 0x03D5);
469
470 VGA_WR08(par->PCIO, 0x03D5, 3);
471 NVSelectHeadRegisters(par, 1);
472 NVLockUnlock(par, 0);
473
474 VGA_WR08(par->PCIO, 0x03D4, 0x28);
475 slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
476 if (slaved_on_B) {
477 VGA_WR08(par->PCIO, 0x03D4, 0x33);
478 tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
479 }
480
481 VGA_WR08(par->PCIO, 0x03D4, 0x44);
482 VGA_WR08(par->PCIO, 0x03D5, 0);
483 NVSelectHeadRegisters(par, 0);
484 NVLockUnlock(par, 0);
485
486 VGA_WR08(par->PCIO, 0x03D4, 0x28);
487 slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
488 if (slaved_on_A) {
489 VGA_WR08(par->PCIO, 0x03D4, 0x33);
490 tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
491 }
492
493 oldhead = NV_RD32(par->PCRTC0, 0x00000860);
494 NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010);
495
Benjamin Herrenschmidt85f15032005-11-07 01:00:30 -0800496 if (nvidia_probe_i2c_connector(info, 1, &edidA))
497 nvidia_probe_of_connector(info, 1, &edidA);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498 if (edidA && !fb_parse_edid(edidA, &var)) {
499 printk("nvidiafb: EDID found from BUS1\n");
500 monA = &monitorA;
501 fb_edid_to_monspecs(edidA, monA);
502 }
503
Benjamin Herrenschmidt85f15032005-11-07 01:00:30 -0800504 if (nvidia_probe_i2c_connector(info, 2, &edidB))
505 nvidia_probe_of_connector(info, 2, &edidB);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506 if (edidB && !fb_parse_edid(edidB, &var)) {
507 printk("nvidiafb: EDID found from BUS2\n");
508 monB = &monitorB;
509 fb_edid_to_monspecs(edidB, monB);
510 }
511
512 if (slaved_on_A && !tvA) {
513 CRTCnumber = 0;
514 FlatPanel = 1;
515 printk("nvidiafb: CRTC 0 is currently programmed for "
516 "DFP\n");
517 } else if (slaved_on_B && !tvB) {
518 CRTCnumber = 1;
519 FlatPanel = 1;
520 printk("nvidiafb: CRTC 1 is currently programmed "
521 "for DFP\n");
522 } else if (analog_on_A) {
523 CRTCnumber = outputAfromCRTC;
524 FlatPanel = 0;
525 printk("nvidiafb: CRTC %i appears to have a "
526 "CRT attached\n", CRTCnumber);
527 } else if (analog_on_B) {
528 CRTCnumber = outputBfromCRTC;
529 FlatPanel = 0;
530 printk("nvidiafb: CRTC %i"
531 "appears to have a "
532 "CRT attached\n", CRTCnumber);
533 } else if (slaved_on_A) {
534 CRTCnumber = 0;
535 FlatPanel = 1;
536 Television = 1;
537 printk("nvidiafb: CRTC 0 is currently programmed "
538 "for TV\n");
539 } else if (slaved_on_B) {
540 CRTCnumber = 1;
541 FlatPanel = 1;
542 Television = 1;
543 printk("nvidiafb: CRTC 1 is currently programmed for "
544 "TV\n");
545 } else if (monA) {
546 FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
547 } else if (monB) {
548 FlatPanel = (monB->input & FB_DISP_DDI) ? 1 : 0;
549 }
550
551 if (par->FlatPanel == -1) {
552 if (FlatPanel != -1) {
553 par->FlatPanel = FlatPanel;
554 par->Television = Television;
555 } else {
556 printk("nvidiafb: Unable to detect display "
557 "type...\n");
558 if (mobile) {
559 printk("...On a laptop, assuming "
560 "DFP\n");
561 par->FlatPanel = 1;
562 } else {
563 printk("...Using default of CRT\n");
564 par->FlatPanel = 0;
565 }
566 }
567 } else {
568 printk("nvidiafb: Forcing display type to %s as "
569 "specified\n", par->FlatPanel ? "DFP" : "CRT");
570 }
571
572 if (par->CRTCnumber == -1) {
573 if (CRTCnumber != -1)
574 par->CRTCnumber = CRTCnumber;
575 else {
576 printk("nvidiafb: Unable to detect which "
577 "CRTCNumber...\n");
578 if (par->FlatPanel)
579 par->CRTCnumber = 1;
580 else
581 par->CRTCnumber = 0;
582 printk("...Defaulting to CRTCNumber %i\n",
583 par->CRTCnumber);
584 }
585 } else {
586 printk("nvidiafb: Forcing CRTCNumber %i as "
587 "specified\n", par->CRTCnumber);
588 }
589
590 if (monA) {
591 if (((monA->input & FB_DISP_DDI) &&
592 par->FlatPanel) ||
593 ((!(monA->input & FB_DISP_DDI)) &&
594 !par->FlatPanel)) {
595 if (monB) {
596 fb_destroy_modedb(monB->modedb);
597 monB = NULL;
598 }
599 } else {
600 fb_destroy_modedb(monA->modedb);
601 monA = NULL;
602 }
603 }
604
605 if (monB) {
606 if (((monB->input & FB_DISP_DDI) &&
607 !par->FlatPanel) ||
608 ((!(monB->input & FB_DISP_DDI)) &&
609 par->FlatPanel)) {
610 fb_destroy_modedb(monB->modedb);
611 monB = NULL;
612 } else
613 monA = monB;
614 }
615
616 if (implementation == 0x0110)
617 cr44 = par->CRTCnumber * 0x3;
618
619 NV_WR32(par->PCRTC0, 0x00000860, oldhead);
620
621 VGA_WR08(par->PCIO, 0x03D4, 0x44);
622 VGA_WR08(par->PCIO, 0x03D5, cr44);
623 NVSelectHeadRegisters(par, par->CRTCnumber);
624 }
625
626 printk("nvidiafb: Using %s on CRTC %i\n",
627 par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT",
628 par->CRTCnumber);
629
630 if (par->FlatPanel && !par->Television) {
631 par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1;
632 par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1;
633 par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033;
634
635 printk("Panel size is %i x %i\n", par->fpWidth, par->fpHeight);
636 }
637
638 if (monA)
639 info->monspecs = *monA;
640
641 kfree(edidA);
642 kfree(edidB);
643}