blob: 93cddab73072cc716b07c0353ec79bdbaec3757a [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001/* SPDX-License-Identifier: GPL-2.0 */
Russell King6ebbf2c2014-06-30 16:29:12 +01002#include <asm/assembler.h>
Will Deaconc36ef4b2011-11-23 11:28:25 +01003#include <asm/unwind.h>
4
Russell King6323f0c2011-01-16 18:02:17 +00005#if __LINUX_ARM_ARCH__ >= 6
Will Deaconc36ef4b2011-11-23 11:28:25 +01006 .macro bitop, name, instr
7ENTRY( \name )
8UNWIND( .fnstart )
Russell Kinga16ede32011-01-16 17:59:44 +00009 ands ip, r1, #3
10 strneb r1, [ip] @ assert word-aligned
Russell King54ea06f2005-07-16 15:21:51 +010011 mov r2, #1
Russell King6323f0c2011-01-16 18:02:17 +000012 and r3, r0, #31 @ Get bit offset
13 mov r0, r0, lsr #5
14 add r1, r1, r0, lsl #2 @ Get word offset
Will Deaconb7ec6992013-11-19 15:46:11 +010015#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
Will Deacond779c072013-06-27 12:01:51 +010016 .arch_extension mp
17 ALT_SMP(W(pldw) [r1])
18 ALT_UP(W(nop))
19#endif
Russell King54ea06f2005-07-16 15:21:51 +010020 mov r3, r2, lsl r3
Russell King6323f0c2011-01-16 18:02:17 +0000211: ldrex r2, [r1]
Russell King54ea06f2005-07-16 15:21:51 +010022 \instr r2, r2, r3
Russell King6323f0c2011-01-16 18:02:17 +000023 strex r0, r2, [r1]
Russell Kinge7ec0292005-07-28 20:36:26 +010024 cmp r0, #0
Russell King54ea06f2005-07-16 15:21:51 +010025 bne 1b
Dave Martin3ba6e692011-02-08 12:09:52 +010026 bx lr
Will Deaconc36ef4b2011-11-23 11:28:25 +010027UNWIND( .fnend )
28ENDPROC(\name )
Russell King54ea06f2005-07-16 15:21:51 +010029 .endm
30
Will Deaconc36ef4b2011-11-23 11:28:25 +010031 .macro testop, name, instr, store
32ENTRY( \name )
33UNWIND( .fnstart )
Russell Kinga16ede32011-01-16 17:59:44 +000034 ands ip, r1, #3
35 strneb r1, [ip] @ assert word-aligned
Russell King54ea06f2005-07-16 15:21:51 +010036 mov r2, #1
Russell King6323f0c2011-01-16 18:02:17 +000037 and r3, r0, #31 @ Get bit offset
38 mov r0, r0, lsr #5
39 add r1, r1, r0, lsl #2 @ Get word offset
Russell King54ea06f2005-07-16 15:21:51 +010040 mov r3, r2, lsl r3 @ create mask
Russell Kingbac4e962009-05-25 20:58:00 +010041 smp_dmb
Will Deaconc32ffce2014-02-21 17:01:48 +010042#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
43 .arch_extension mp
44 ALT_SMP(W(pldw) [r1])
45 ALT_UP(W(nop))
46#endif
Russell King6323f0c2011-01-16 18:02:17 +0000471: ldrex r2, [r1]
Russell King54ea06f2005-07-16 15:21:51 +010048 ands r0, r2, r3 @ save old value of bit
Russell King6323f0c2011-01-16 18:02:17 +000049 \instr r2, r2, r3 @ toggle bit
50 strex ip, r2, [r1]
Russell King614d73e2005-07-27 23:00:05 +010051 cmp ip, #0
Russell King54ea06f2005-07-16 15:21:51 +010052 bne 1b
Russell Kingbac4e962009-05-25 20:58:00 +010053 smp_dmb
Russell King54ea06f2005-07-16 15:21:51 +010054 cmp r0, #0
55 movne r0, #1
Dave Martin3ba6e692011-02-08 12:09:52 +0100562: bx lr
Will Deaconc36ef4b2011-11-23 11:28:25 +010057UNWIND( .fnend )
58ENDPROC(\name )
Russell King54ea06f2005-07-16 15:21:51 +010059 .endm
60#else
Will Deaconc36ef4b2011-11-23 11:28:25 +010061 .macro bitop, name, instr
62ENTRY( \name )
63UNWIND( .fnstart )
Russell Kinga16ede32011-01-16 17:59:44 +000064 ands ip, r1, #3
65 strneb r1, [ip] @ assert word-aligned
Russell King6323f0c2011-01-16 18:02:17 +000066 and r2, r0, #31
67 mov r0, r0, lsr #5
Russell King7a55fd02005-04-18 22:50:01 +010068 mov r3, #1
69 mov r3, r3, lsl r2
Russell King59d1ff32005-11-09 15:04:22 +000070 save_and_disable_irqs ip
Russell King6323f0c2011-01-16 18:02:17 +000071 ldr r2, [r1, r0, lsl #2]
Russell King7a55fd02005-04-18 22:50:01 +010072 \instr r2, r2, r3
Russell King6323f0c2011-01-16 18:02:17 +000073 str r2, [r1, r0, lsl #2]
Russell King7a55fd02005-04-18 22:50:01 +010074 restore_irqs ip
Russell King6ebbf2c2014-06-30 16:29:12 +010075 ret lr
Will Deaconc36ef4b2011-11-23 11:28:25 +010076UNWIND( .fnend )
77ENDPROC(\name )
Russell King7a55fd02005-04-18 22:50:01 +010078 .endm
79
80/**
81 * testop - implement a test_and_xxx_bit operation.
82 * @instr: operational instruction
83 * @store: store instruction
84 *
85 * Note: we can trivially conditionalise the store instruction
Simon Arlott6cbdc8c2007-05-11 20:40:30 +010086 * to avoid dirtying the data cache.
Russell King7a55fd02005-04-18 22:50:01 +010087 */
Will Deaconc36ef4b2011-11-23 11:28:25 +010088 .macro testop, name, instr, store
89ENTRY( \name )
90UNWIND( .fnstart )
Russell Kinga16ede32011-01-16 17:59:44 +000091 ands ip, r1, #3
92 strneb r1, [ip] @ assert word-aligned
Russell King6323f0c2011-01-16 18:02:17 +000093 and r3, r0, #31
94 mov r0, r0, lsr #5
Russell King59d1ff32005-11-09 15:04:22 +000095 save_and_disable_irqs ip
Russell King6323f0c2011-01-16 18:02:17 +000096 ldr r2, [r1, r0, lsl #2]!
97 mov r0, #1
Russell King7a55fd02005-04-18 22:50:01 +010098 tst r2, r0, lsl r3
99 \instr r2, r2, r0, lsl r3
100 \store r2, [r1]
Russell King7a55fd02005-04-18 22:50:01 +0100101 moveq r0, #0
Uwe Kleine-König0d928b02009-08-13 20:38:17 +0200102 restore_irqs ip
Russell King6ebbf2c2014-06-30 16:29:12 +0100103 ret lr
Will Deaconc36ef4b2011-11-23 11:28:25 +0100104UNWIND( .fnend )
105ENDPROC(\name )
Russell King7a55fd02005-04-18 22:50:01 +0100106 .endm
Russell King54ea06f2005-07-16 15:21:51 +0100107#endif