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gerrit-public.fairphone.software / kernel / msm-4.19 / 02e3814e193ff798676793016851bc222366dc6a / . / include / asm-blackfin / mach-bf561 / irq.h
blob: 6698389c556451c51306b9dba7ed2f029af73416 [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]1
2/*
3 * File: include/asm-blackfin/mach-bf561/irq.h
4 * Based on:
5 * Author:
6 *
7 * Created:
8 * Description:
9 *
10 * Rev:
11 *
12 * Modified:
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _BF561_IRQ_H_
33#define _BF561_IRQ_H_
34
35/***********************************************************************
36 * Interrupt source definitions:
37 Event Source Core Event Name IRQ No
38 (highest priority)
39 Emulation Events EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47 PLL Wakeup Interrupt IVG7 7
48 DMA1 Error (generic) IVG7 8
49 DMA2 Error (generic) IVG7 9
50 IMDMA Error (generic) IVG7 10
51 PPI1 Error Interrupt IVG7 11
52 PPI2 Error Interrupt IVG7 12
53 SPORT0 Error Interrupt IVG7 13
54 SPORT1 Error Interrupt IVG7 14
55 SPI Error Interrupt IVG7 15
56 UART Error Interrupt IVG7 16
57 Reserved Interrupt IVG7 17
58
59 DMA1 0 Interrupt(PPI1) IVG8 18
60 DMA1 1 Interrupt(PPI2) IVG8 19
61 DMA1 2 Interrupt IVG8 20
62 DMA1 3 Interrupt IVG8 21
63 DMA1 4 Interrupt IVG8 22
64 DMA1 5 Interrupt IVG8 23
65 DMA1 6 Interrupt IVG8 24
66 DMA1 7 Interrupt IVG8 25
67 DMA1 8 Interrupt IVG8 26
68 DMA1 9 Interrupt IVG8 27
69 DMA1 10 Interrupt IVG8 28
70 DMA1 11 Interrupt IVG8 29
71
72 DMA2 0 (SPORT0 RX) IVG9 30
73 DMA2 1 (SPORT0 TX) IVG9 31
74 DMA2 2 (SPORT1 RX) IVG9 32
75 DMA2 3 (SPORT2 TX) IVG9 33
76 DMA2 4 (SPI) IVG9 34
77 DMA2 5 (UART RX) IVG9 35
78 DMA2 6 (UART TX) IVG9 36
79 DMA2 7 Interrupt IVG9 37
80 DMA2 8 Interrupt IVG9 38
81 DMA2 9 Interrupt IVG9 39
82 DMA2 10 Interrupt IVG9 40
83 DMA2 11 Interrupt IVG9 41
84
85 TIMER 0 Interrupt IVG10 42
86 TIMER 1 Interrupt IVG10 43
87 TIMER 2 Interrupt IVG10 44
88 TIMER 3 Interrupt IVG10 45
89 TIMER 4 Interrupt IVG10 46
90 TIMER 5 Interrupt IVG10 47
91 TIMER 6 Interrupt IVG10 48
92 TIMER 7 Interrupt IVG10 49
93 TIMER 8 Interrupt IVG10 50
94 TIMER 9 Interrupt IVG10 51
95 TIMER 10 Interrupt IVG10 52
96 TIMER 11 Interrupt IVG10 53
97
98 Programmable Flags0 A (8) IVG11 54
99 Programmable Flags0 B (8) IVG11 55
100 Programmable Flags1 A (8) IVG11 56
101 Programmable Flags1 B (8) IVG11 57
102 Programmable Flags2 A (8) IVG11 58
103 Programmable Flags2 B (8) IVG11 59
104
105 MDMA1 0 write/read INT IVG8 60
106 MDMA1 1 write/read INT IVG8 61
107
108 MDMA2 0 write/read INT IVG9 62
109 MDMA2 1 write/read INT IVG9 63
110
111 IMDMA 0 write/read INT IVG12 64
112 IMDMA 1 write/read INT IVG12 65
113
114 Watch Dog Timer IVG13 66
115
116 Reserved interrupt IVG7 67
117 Reserved interrupt IVG7 68
118 Supplemental interrupt 0 IVG7 69
119 supplemental interrupt 1 IVG7 70
120
Michael Hennerich56f87712008-05-10 00:11:59 +0800[diff] [blame]121 Softirq IVG14
122 System Call --
123 (lowest priority) IVG15
124
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]125 **********************************************************************/
126
Michael Hennerich56f87712008-05-10 00:11:59 +0800[diff] [blame]127#define SYS_IRQS 71
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]128#define NR_PERI_INTS 64
129
130/*
131 * The ABSTRACT IRQ definitions
132 * the first seven of the following are fixed,
133 * the rest you change if you need to.
134 */
135/* IVG 0-6*/
136#define IRQ_EMU 0 /* Emulation */
137#define IRQ_RST 1 /* Reset */
138#define IRQ_NMI 2 /* Non Maskable Interrupt */
139#define IRQ_EVX 3 /* Exception */
140#define IRQ_UNUSED 4 /* Reserved interrupt */
141#define IRQ_HWERR 5 /* Hardware Error */
142#define IRQ_CORETMR 6 /* Core timer */
143
144#define IVG_BASE 7
145/* IVG 7 */
146#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */
147#define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */
148#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
149#define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */
150#define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */
151#define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */
152#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
153#define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */
154#define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */
155#define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */
156#define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */
157#define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */
158#define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */
159/* IVG 8 */
160#define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */
161#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
162#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
163#define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */
164#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
165#define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */
166#define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */
167#define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */
168#define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */
169#define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */
170#define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */
171#define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */
172#define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */
173#define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */
174#define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */
175/* IVG 9 */
176#define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */
177#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
178#define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */
179#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
180#define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */
181#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
182#define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */
183#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
184#define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */
185#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
186#define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */
187#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
188#define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */
189#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
190#define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */
191#define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */
192#define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */
193#define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */
194#define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */
195/* IVG 10 */
196#define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */
197#define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */
198#define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */
199#define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */
200#define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */
201#define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */
202#define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */
203#define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */
204#define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */
205#define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */
206#define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */
207#define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */
208/* IVG 11 */
209#define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */
210#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
211#define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */
212#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
213#define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */
214#define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */
215#define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */
216#define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */
217/* IVG 8 */
218#define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */
219#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
220#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
221#define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */
222#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
223#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
224/* IVG 9 */
225#define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */
226#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
227#define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */
228#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
229/* IVG 12 */
230#define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */
231#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
232#define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */
233#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
234/* IVG 13 */
235#define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */
236/* IVG 7 */
237#define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */
238#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
239#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */
240#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */
Michael Hennerich56f87712008-05-10 00:11:59 +0800[diff] [blame]241
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]242#define IRQ_PF0 73
243#define IRQ_PF1 74
244#define IRQ_PF2 75
245#define IRQ_PF3 76
246#define IRQ_PF4 77
247#define IRQ_PF5 78
248#define IRQ_PF6 79
249#define IRQ_PF7 80
250#define IRQ_PF8 81
251#define IRQ_PF9 82
252#define IRQ_PF10 83
253#define IRQ_PF11 84
254#define IRQ_PF12 85
255#define IRQ_PF13 86
256#define IRQ_PF14 87
257#define IRQ_PF15 88
258#define IRQ_PF16 89
259#define IRQ_PF17 90
260#define IRQ_PF18 91
261#define IRQ_PF19 92
262#define IRQ_PF20 93
263#define IRQ_PF21 94
264#define IRQ_PF22 95
265#define IRQ_PF23 96
266#define IRQ_PF24 97
267#define IRQ_PF25 98
268#define IRQ_PF26 99
269#define IRQ_PF27 100
270#define IRQ_PF28 101
271#define IRQ_PF29 102
272#define IRQ_PF30 103
273#define IRQ_PF31 104
274#define IRQ_PF32 105
275#define IRQ_PF33 106
276#define IRQ_PF34 107
277#define IRQ_PF35 108
278#define IRQ_PF36 109
279#define IRQ_PF37 110
280#define IRQ_PF38 111
281#define IRQ_PF39 112
282#define IRQ_PF40 113
283#define IRQ_PF41 114
284#define IRQ_PF42 115
285#define IRQ_PF43 116
286#define IRQ_PF44 117
287#define IRQ_PF45 118
288#define IRQ_PF46 119
289#define IRQ_PF47 120
290
Michael Hennerich301af292007-07-24 15:35:53 +0800[diff] [blame]291#define GPIO_IRQ_BASE IRQ_PF0
292
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]293#define NR_IRQS (IRQ_PF47 + 1)
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]294
295#define IVG7 7
296#define IVG8 8
297#define IVG9 9
298#define IVG10 10
299#define IVG11 11
300#define IVG12 12
301#define IVG13 13
302#define IVG14 14
303#define IVG15 15
304
305/*
306 * DEFAULT PRIORITIES:
307 */
308
309#define CONFIG_DEF_PLL_WAKEUP 7
310#define CONFIG_DEF_DMA1_ERROR 7
311#define CONFIG_DEF_DMA2_ERROR 7
312#define CONFIG_DEF_IMDMA_ERROR 7
313#define CONFIG_DEF_PPI1_ERROR 7
314#define CONFIG_DEF_PPI2_ERROR 7
315#define CONFIG_DEF_SPORT0_ERROR 7
316#define CONFIG_DEF_SPORT1_ERROR 7
317#define CONFIG_DEF_SPI_ERROR 7
318#define CONFIG_DEF_UART_ERROR 7
319#define CONFIG_DEF_RESERVED_ERROR 7
320#define CONFIG_DEF_DMA1_0 8
321#define CONFIG_DEF_DMA1_1 8
322#define CONFIG_DEF_DMA1_2 8
323#define CONFIG_DEF_DMA1_3 8
324#define CONFIG_DEF_DMA1_4 8
325#define CONFIG_DEF_DMA1_5 8
326#define CONFIG_DEF_DMA1_6 8
327#define CONFIG_DEF_DMA1_7 8
328#define CONFIG_DEF_DMA1_8 8
329#define CONFIG_DEF_DMA1_9 8
330#define CONFIG_DEF_DMA1_10 8
331#define CONFIG_DEF_DMA1_11 8
332#define CONFIG_DEF_DMA2_0 9
333#define CONFIG_DEF_DMA2_1 9
334#define CONFIG_DEF_DMA2_2 9
335#define CONFIG_DEF_DMA2_3 9
336#define CONFIG_DEF_DMA2_4 9
337#define CONFIG_DEF_DMA2_5 9
338#define CONFIG_DEF_DMA2_6 9
339#define CONFIG_DEF_DMA2_7 9
340#define CONFIG_DEF_DMA2_8 9
341#define CONFIG_DEF_DMA2_9 9
342#define CONFIG_DEF_DMA2_10 9
343#define CONFIG_DEF_DMA2_11 9
344#define CONFIG_DEF_TIMER0 10
345#define CONFIG_DEF_TIMER1 10
346#define CONFIG_DEF_TIMER2 10
347#define CONFIG_DEF_TIMER3 10
348#define CONFIG_DEF_TIMER4 10
349#define CONFIG_DEF_TIMER5 10
350#define CONFIG_DEF_TIMER6 10
351#define CONFIG_DEF_TIMER7 10
352#define CONFIG_DEF_TIMER8 10
353#define CONFIG_DEF_TIMER9 10
354#define CONFIG_DEF_TIMER10 10
355#define CONFIG_DEF_TIMER11 10
356#define CONFIG_DEF_PROG0_INTA 11
357#define CONFIG_DEF_PROG0_INTB 11
358#define CONFIG_DEF_PROG1_INTA 11
359#define CONFIG_DEF_PROG1_INTB 11
360#define CONFIG_DEF_PROG2_INTA 11
361#define CONFIG_DEF_PROG2_INTB 11
362#define CONFIG_DEF_DMA1_WRRD0 8
363#define CONFIG_DEF_DMA1_WRRD1 8
364#define CONFIG_DEF_DMA2_WRRD0 9
365#define CONFIG_DEF_DMA2_WRRD1 9
366#define CONFIG_DEF_IMDMA_WRRD0 12
367#define CONFIG_DEF_IMDMA_WRRD1 12
368#define CONFIG_DEF_WATCH 13
369#define CONFIG_DEF_RESERVED_1 7
370#define CONFIG_DEF_RESERVED_2 7
371#define CONFIG_DEF_SUPPLE_0 7
372#define CONFIG_DEF_SUPPLE_1 7
373
374/* IAR0 BIT FIELDS */
375#define IRQ_PLL_WAKEUP_POS 0
376#define IRQ_DMA1_ERROR_POS 4
377#define IRQ_DMA2_ERROR_POS 8
378#define IRQ_IMDMA_ERROR_POS 12
379#define IRQ_PPI0_ERROR_POS 16
380#define IRQ_PPI1_ERROR_POS 20
381#define IRQ_SPORT0_ERROR_POS 24
382#define IRQ_SPORT1_ERROR_POS 28
383/* IAR1 BIT FIELDS */
384#define IRQ_SPI_ERROR_POS 0
385#define IRQ_UART_ERROR_POS 4
386#define IRQ_RESERVED_ERROR_POS 8
387#define IRQ_DMA1_0_POS 12
388#define IRQ_DMA1_1_POS 16
389#define IRQ_DMA1_2_POS 20
390#define IRQ_DMA1_3_POS 24
391#define IRQ_DMA1_4_POS 28
392/* IAR2 BIT FIELDS */
393#define IRQ_DMA1_5_POS 0
394#define IRQ_DMA1_6_POS 4
395#define IRQ_DMA1_7_POS 8
396#define IRQ_DMA1_8_POS 12
397#define IRQ_DMA1_9_POS 16
398#define IRQ_DMA1_10_POS 20
399#define IRQ_DMA1_11_POS 24
400#define IRQ_DMA2_0_POS 28
401/* IAR3 BIT FIELDS */
402#define IRQ_DMA2_1_POS 0
403#define IRQ_DMA2_2_POS 4
404#define IRQ_DMA2_3_POS 8
405#define IRQ_DMA2_4_POS 12
406#define IRQ_DMA2_5_POS 16
407#define IRQ_DMA2_6_POS 20
408#define IRQ_DMA2_7_POS 24
409#define IRQ_DMA2_8_POS 28
410/* IAR4 BIT FIELDS */
411#define IRQ_DMA2_9_POS 0
412#define IRQ_DMA2_10_POS 4
413#define IRQ_DMA2_11_POS 8
414#define IRQ_TIMER0_POS 12
415#define IRQ_TIMER1_POS 16
416#define IRQ_TIMER2_POS 20
417#define IRQ_TIMER3_POS 24
418#define IRQ_TIMER4_POS 28
419/* IAR5 BIT FIELDS */
420#define IRQ_TIMER5_POS 0
421#define IRQ_TIMER6_POS 4
422#define IRQ_TIMER7_POS 8
423#define IRQ_TIMER8_POS 12
424#define IRQ_TIMER9_POS 16
425#define IRQ_TIMER10_POS 20
426#define IRQ_TIMER11_POS 24
427#define IRQ_PROG0_INTA_POS 28
428/* IAR6 BIT FIELDS */
429#define IRQ_PROG0_INTB_POS 0
430#define IRQ_PROG1_INTA_POS 4
431#define IRQ_PROG1_INTB_POS 8
432#define IRQ_PROG2_INTA_POS 12
433#define IRQ_PROG2_INTB_POS 16
434#define IRQ_DMA1_WRRD0_POS 20
435#define IRQ_DMA1_WRRD1_POS 24
436#define IRQ_DMA2_WRRD0_POS 28
437/* IAR7 BIT FIELDS */
438#define IRQ_DMA2_WRRD1_POS 0
439#define IRQ_IMDMA_WRRD0_POS 4
440#define IRQ_IMDMA_WRRD1_POS 8
441#define IRQ_WDTIMER_POS 12
442#define IRQ_RESERVED_1_POS 16
443#define IRQ_RESERVED_2_POS 20
444#define IRQ_SUPPLE_0_POS 24
445#define IRQ_SUPPLE_1_POS 28
446
447#endif /* _BF561_IRQ_H_ */