| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Memory MAP |
| 3 | * Common header file for blackfin BF561 of processors. |
| 4 | */ |
| 5 | |
| 6 | #ifndef _MEM_MAP_561_H_ |
| 7 | #define _MEM_MAP_561_H_ |
| 8 | |
| 9 | #define COREMMR_BASE 0xFFE00000 /* Core MMRs */ |
| 10 | #define SYSMMR_BASE 0xFFC00000 /* System MMRs */ |
| 11 | |
| 12 | /* Async Memory Banks */ |
| 13 | #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ |
| 14 | #define ASYNC_BANK3_SIZE 0x04000000 /* 64M */ |
| 15 | #define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */ |
| 16 | #define ASYNC_BANK2_SIZE 0x04000000 /* 64M */ |
| 17 | #define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */ |
| 18 | #define ASYNC_BANK1_SIZE 0x04000000 /* 64M */ |
| 19 | #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ |
| 20 | #define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ |
| 21 | |
| Mike Frysinger | c3a9f43 | 2007-11-21 16:12:12 +0800 | [diff] [blame] | 22 | /* Boot ROM Memory */ |
| 23 | |
| 24 | #define BOOT_ROM_START 0xEF000000 |
| 25 | #define BOOT_ROM_LENGTH 0x800 |
| 26 | |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 27 | /* Level 1 Memory */ |
| 28 | |
| Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 29 | #ifdef CONFIG_BFIN_ICACHE |
| 30 | #define BFIN_ICACHESIZE (16*1024) |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 31 | #else |
| Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 32 | #define BFIN_ICACHESIZE (0*1024) |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 33 | #endif |
| 34 | |
| 35 | /* Memory Map for ADSP-BF561 processors */ |
| 36 | |
| 37 | #ifdef CONFIG_BF561 |
| 38 | #define L1_CODE_START 0xFFA00000 |
| 39 | #define L1_DATA_A_START 0xFF800000 |
| 40 | #define L1_DATA_B_START 0xFF900000 |
| 41 | |
| 42 | #define L1_CODE_LENGTH 0x4000 |
| 43 | |
| Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 44 | #ifdef CONFIG_BFIN_DCACHE |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 45 | |
| Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 46 | #ifdef CONFIG_BFIN_DCACHE_BANKA |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 47 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) |
| 48 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) |
| 49 | #define L1_DATA_B_LENGTH 0x8000 |
| Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 50 | #define BFIN_DCACHESIZE (16*1024) |
| 51 | #define BFIN_DSUPBANKS 1 |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 52 | #else |
| 53 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) |
| 54 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) |
| 55 | #define L1_DATA_B_LENGTH (0x8000 - 0x4000) |
| Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 56 | #define BFIN_DCACHESIZE (32*1024) |
| 57 | #define BFIN_DSUPBANKS 2 |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 58 | #endif |
| 59 | |
| 60 | #else |
| 61 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) |
| 62 | #define L1_DATA_A_LENGTH 0x8000 |
| 63 | #define L1_DATA_B_LENGTH 0x8000 |
| Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 64 | #define BFIN_DCACHESIZE (0*1024) |
| 65 | #define BFIN_DSUPBANKS 0 |
| 66 | #endif /*CONFIG_BFIN_DCACHE*/ |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 67 | #endif |
| 68 | |
| 69 | /* Level 2 Memory */ |
| 70 | #define L2_START 0xFEB00000 |
| 71 | #define L2_LENGTH 0x20000 |
| 72 | |
| 73 | /* Scratch Pad Memory */ |
| 74 | |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 75 | #define L1_SCRATCH_START 0xFFB00000 |
| 76 | #define L1_SCRATCH_LENGTH 0x1000 |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 77 | |
| 78 | #endif /* _MEM_MAP_533_H_ */ |