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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020043#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050044#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050046#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <linux/libata.h>
48#include <asm/io.h>
49
50#define DRV_NAME "ahci"
Jeff Garzikead5de92005-05-31 11:53:57 -040051#define DRV_VERSION "1.01"
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
53
54enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
60 AHCI_RX_FIS_SZ = 256,
61 AHCI_CMD_TBL_HDR = 0x80,
Jeff Garzika0ea7322005-06-04 01:13:15 -040062 AHCI_CMD_TBL_CDB = 0x40,
Linus Torvalds1da177e2005-04-16 15:20:36 -070063 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
65 AHCI_RX_FIS_SZ,
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
69
70 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
71
72 board_ahci = 0,
73
74 /* global controller registers */
75 HOST_CAP = 0x00, /* host capabilities */
76 HOST_CTL = 0x04, /* global host control */
77 HOST_IRQ_STAT = 0x08, /* interrupt status */
78 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
79 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
80
81 /* HOST_CTL bits */
82 HOST_RESET = (1 << 0), /* reset controller; self-clear */
83 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
84 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
85
86 /* HOST_CAP bits */
87 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
88
89 /* registers for each SATA port */
90 PORT_LST_ADDR = 0x00, /* command list DMA addr */
91 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
92 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
93 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
94 PORT_IRQ_STAT = 0x10, /* interrupt status */
95 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
96 PORT_CMD = 0x18, /* port command */
97 PORT_TFDATA = 0x20, /* taskfile data */
98 PORT_SIG = 0x24, /* device TF signature */
99 PORT_CMD_ISSUE = 0x38, /* command issue */
100 PORT_SCR = 0x28, /* SATA phy register block */
101 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
102 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
103 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
104 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
105
106 /* PORT_IRQ_{STAT,MASK} bits */
107 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
108 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
109 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
110 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
111 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
112 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
113 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
114 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
115
116 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
117 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
118 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
119 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
120 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
121 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
122 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
123 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
124 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
125
126 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
127 PORT_IRQ_HBUS_ERR |
128 PORT_IRQ_HBUS_DATA_ERR |
129 PORT_IRQ_IF_ERR,
130 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
131 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
132 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
133 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
134 PORT_IRQ_D2H_REG_FIS,
135
136 /* PORT_CMD bits */
Jeff Garzik02eaa662005-11-12 01:32:19 -0500137 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
139 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
140 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
141 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
142 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
143 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
144
145 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
146 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
147 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400148
149 /* hpriv->flags bits */
150 AHCI_FLAG_MSI = (1 << 0),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151};
152
153struct ahci_cmd_hdr {
154 u32 opts;
155 u32 status;
156 u32 tbl_addr;
157 u32 tbl_addr_hi;
158 u32 reserved[4];
159};
160
161struct ahci_sg {
162 u32 addr;
163 u32 addr_hi;
164 u32 reserved;
165 u32 flags_size;
166};
167
168struct ahci_host_priv {
169 unsigned long flags;
170 u32 cap; /* cache of HOST_CAP register */
171 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
172};
173
174struct ahci_port_priv {
175 struct ahci_cmd_hdr *cmd_slot;
176 dma_addr_t cmd_slot_dma;
177 void *cmd_tbl;
178 dma_addr_t cmd_tbl_dma;
179 struct ahci_sg *cmd_tbl_sg;
180 void *rx_fis;
181 dma_addr_t rx_fis_dma;
182};
183
184static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
185static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
186static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
187static int ahci_qc_issue(struct ata_queued_cmd *qc);
188static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
189static void ahci_phy_reset(struct ata_port *ap);
190static void ahci_irq_clear(struct ata_port *ap);
191static void ahci_eng_timeout(struct ata_port *ap);
192static int ahci_port_start(struct ata_port *ap);
193static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
195static void ahci_qc_prep(struct ata_queued_cmd *qc);
196static u8 ahci_check_status(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
Jeff Garzik907f4672005-05-12 15:03:42 -0400198static void ahci_remove_one (struct pci_dev *pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199
Jeff Garzik193515d2005-11-07 00:59:37 -0500200static struct scsi_host_template ahci_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 .module = THIS_MODULE,
202 .name = DRV_NAME,
203 .ioctl = ata_scsi_ioctl,
204 .queuecommand = ata_scsi_queuecmd,
205 .eh_strategy_handler = ata_scsi_error,
206 .can_queue = ATA_DEF_QUEUE,
207 .this_id = ATA_SHT_THIS_ID,
208 .sg_tablesize = AHCI_MAX_SG,
209 .max_sectors = ATA_MAX_SECTORS,
210 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
211 .emulated = ATA_SHT_EMULATED,
212 .use_clustering = AHCI_USE_CLUSTERING,
213 .proc_name = DRV_NAME,
214 .dma_boundary = AHCI_DMA_BOUNDARY,
215 .slave_configure = ata_scsi_slave_config,
216 .bios_param = ata_std_bios_param,
217 .ordered_flush = 1,
218};
219
Jeff Garzik057ace52005-10-22 14:27:05 -0400220static const struct ata_port_operations ahci_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221 .port_disable = ata_port_disable,
222
223 .check_status = ahci_check_status,
224 .check_altstatus = ahci_check_status,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225 .dev_select = ata_noop_dev_select,
226
227 .tf_read = ahci_tf_read,
228
229 .phy_reset = ahci_phy_reset,
230
231 .qc_prep = ahci_qc_prep,
232 .qc_issue = ahci_qc_issue,
233
234 .eng_timeout = ahci_eng_timeout,
235
236 .irq_handler = ahci_interrupt,
237 .irq_clear = ahci_irq_clear,
238
239 .scr_read = ahci_scr_read,
240 .scr_write = ahci_scr_write,
241
242 .port_start = ahci_port_start,
243 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244};
245
246static struct ata_port_info ahci_port_info[] = {
247 /* board_ahci */
248 {
249 .sht = &ahci_sht,
250 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
251 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
252 ATA_FLAG_PIO_DMA,
Brett Russ7da79312005-09-01 21:53:34 -0400253 .pio_mask = 0x1f, /* pio0-4 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
255 .port_ops = &ahci_ops,
256 },
257};
258
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500259static const struct pci_device_id ahci_pci_tbl[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 board_ahci }, /* ICH6 */
262 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_ahci }, /* ICH6M */
264 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ICH7 */
266 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_ahci }, /* ICH7M */
268 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 board_ahci }, /* ICH7R */
270 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 board_ahci }, /* ULi M5288 */
Jason Gaston680d3232005-04-16 15:24:45 -0700272 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 board_ahci }, /* ESB2 */
274 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
275 board_ahci }, /* ESB2 */
276 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
277 board_ahci }, /* ESB2 */
Jason Gaston3db368f2005-08-10 06:18:43 -0700278 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
279 board_ahci }, /* ICH7-M DH */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280 { } /* terminate list */
281};
282
283
284static struct pci_driver ahci_pci_driver = {
285 .name = DRV_NAME,
286 .id_table = ahci_pci_tbl,
287 .probe = ahci_init_one,
Jeff Garzik907f4672005-05-12 15:03:42 -0400288 .remove = ahci_remove_one,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289};
290
291
292static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
293{
294 return base + 0x100 + (port * 0x80);
295}
296
Jeff Garzikea6ba102005-08-30 05:18:18 -0400297static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298{
Jeff Garzikea6ba102005-08-30 05:18:18 -0400299 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300}
301
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302static int ahci_port_start(struct ata_port *ap)
303{
304 struct device *dev = ap->host_set->dev;
305 struct ahci_host_priv *hpriv = ap->host_set->private_data;
306 struct ahci_port_priv *pp;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400307 void __iomem *mmio = ap->host_set->mmio_base;
308 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
309 void *mem;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310 dma_addr_t mem_dma;
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500311 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
Tejun Heo0a139e72005-06-26 23:52:50 +0900314 if (!pp)
315 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316 memset(pp, 0, sizeof(*pp));
317
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500318 rc = ata_pad_alloc(ap, dev);
319 if (rc) {
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400320 kfree(pp);
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500321 return rc;
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400322 }
323
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
325 if (!mem) {
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500326 ata_pad_free(ap, dev);
Tejun Heo0a139e72005-06-26 23:52:50 +0900327 kfree(pp);
328 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329 }
330 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
331
332 /*
333 * First item in chunk of DMA memory: 32-slot command table,
334 * 32 bytes each in size
335 */
336 pp->cmd_slot = mem;
337 pp->cmd_slot_dma = mem_dma;
338
339 mem += AHCI_CMD_SLOT_SZ;
340 mem_dma += AHCI_CMD_SLOT_SZ;
341
342 /*
343 * Second item: Received-FIS area
344 */
345 pp->rx_fis = mem;
346 pp->rx_fis_dma = mem_dma;
347
348 mem += AHCI_RX_FIS_SZ;
349 mem_dma += AHCI_RX_FIS_SZ;
350
351 /*
352 * Third item: data area for storing a single command
353 * and its scatter-gather table
354 */
355 pp->cmd_tbl = mem;
356 pp->cmd_tbl_dma = mem_dma;
357
358 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
359
360 ap->private_data = pp;
361
362 if (hpriv->cap & HOST_CAP_64)
363 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
364 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
365 readl(port_mmio + PORT_LST_ADDR); /* flush */
366
367 if (hpriv->cap & HOST_CAP_64)
368 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
369 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
370 readl(port_mmio + PORT_FIS_ADDR); /* flush */
371
372 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
373 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
374 PORT_CMD_START, port_mmio + PORT_CMD);
375 readl(port_mmio + PORT_CMD); /* flush */
376
377 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378}
379
380
381static void ahci_port_stop(struct ata_port *ap)
382{
383 struct device *dev = ap->host_set->dev;
384 struct ahci_port_priv *pp = ap->private_data;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400385 void __iomem *mmio = ap->host_set->mmio_base;
386 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387 u32 tmp;
388
389 tmp = readl(port_mmio + PORT_CMD);
390 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
391 writel(tmp, port_mmio + PORT_CMD);
392 readl(port_mmio + PORT_CMD); /* flush */
393
394 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
395 * this is slightly incorrect.
396 */
397 msleep(500);
398
399 ap->private_data = NULL;
400 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
401 pp->cmd_slot, pp->cmd_slot_dma);
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500402 ata_pad_free(ap, dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403 kfree(pp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404}
405
406static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
407{
408 unsigned int sc_reg;
409
410 switch (sc_reg_in) {
411 case SCR_STATUS: sc_reg = 0; break;
412 case SCR_CONTROL: sc_reg = 1; break;
413 case SCR_ERROR: sc_reg = 2; break;
414 case SCR_ACTIVE: sc_reg = 3; break;
415 default:
416 return 0xffffffffU;
417 }
418
Al Viro1e4f2a92005-10-21 06:46:02 +0100419 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420}
421
422
423static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
424 u32 val)
425{
426 unsigned int sc_reg;
427
428 switch (sc_reg_in) {
429 case SCR_STATUS: sc_reg = 0; break;
430 case SCR_CONTROL: sc_reg = 1; break;
431 case SCR_ERROR: sc_reg = 2; break;
432 case SCR_ACTIVE: sc_reg = 3; break;
433 default:
434 return;
435 }
436
Al Viro1e4f2a92005-10-21 06:46:02 +0100437 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438}
439
440static void ahci_phy_reset(struct ata_port *ap)
441{
442 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
443 struct ata_taskfile tf;
444 struct ata_device *dev = &ap->device[0];
Jeff Garzik02eaa662005-11-12 01:32:19 -0500445 u32 new_tmp, tmp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446
447 __sata_phy_reset(ap);
448
449 if (ap->flags & ATA_FLAG_PORT_DISABLED)
450 return;
451
452 tmp = readl(port_mmio + PORT_SIG);
453 tf.lbah = (tmp >> 24) & 0xff;
454 tf.lbam = (tmp >> 16) & 0xff;
455 tf.lbal = (tmp >> 8) & 0xff;
456 tf.nsect = (tmp) & 0xff;
457
458 dev->class = ata_dev_classify(&tf);
Jeff Garzik02eaa662005-11-12 01:32:19 -0500459 if (!ata_dev_present(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460 ata_port_disable(ap);
Jeff Garzik02eaa662005-11-12 01:32:19 -0500461 return;
462 }
463
464 /* Make sure port's ATAPI bit is set appropriately */
465 new_tmp = tmp = readl(port_mmio + PORT_CMD);
466 if (dev->class == ATA_DEV_ATAPI)
467 new_tmp |= PORT_CMD_ATAPI;
468 else
469 new_tmp &= ~PORT_CMD_ATAPI;
470 if (new_tmp != tmp) {
471 writel(new_tmp, port_mmio + PORT_CMD);
472 readl(port_mmio + PORT_CMD); /* flush */
473 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474}
475
476static u8 ahci_check_status(struct ata_port *ap)
477{
Al Viro1e4f2a92005-10-21 06:46:02 +0100478 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479
480 return readl(mmio + PORT_TFDATA) & 0xFF;
481}
482
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
484{
485 struct ahci_port_priv *pp = ap->private_data;
486 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
487
488 ata_tf_from_fis(d2h_fis, tf);
489}
490
Jeff Garzik828d09d2005-11-12 01:27:07 -0500491static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492{
493 struct ahci_port_priv *pp = qc->ap->private_data;
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400494 struct scatterlist *sg;
495 struct ahci_sg *ahci_sg;
Jeff Garzik828d09d2005-11-12 01:27:07 -0500496 unsigned int n_sg = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497
498 VPRINTK("ENTER\n");
499
500 /*
501 * Next, the S/G list.
502 */
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400503 ahci_sg = pp->cmd_tbl_sg;
504 ata_for_each_sg(sg, qc) {
505 dma_addr_t addr = sg_dma_address(sg);
506 u32 sg_len = sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400508 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
509 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
510 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
Jeff Garzik828d09d2005-11-12 01:27:07 -0500511
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400512 ahci_sg++;
Jeff Garzik828d09d2005-11-12 01:27:07 -0500513 n_sg++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514 }
Jeff Garzik828d09d2005-11-12 01:27:07 -0500515
516 return n_sg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517}
518
519static void ahci_qc_prep(struct ata_queued_cmd *qc)
520{
Jeff Garzika0ea7322005-06-04 01:13:15 -0400521 struct ata_port *ap = qc->ap;
522 struct ahci_port_priv *pp = ap->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523 u32 opts;
524 const u32 cmd_fis_len = 5; /* five dwords */
Jeff Garzik828d09d2005-11-12 01:27:07 -0500525 unsigned int n_elem;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526
527 /*
528 * Fill in command slot information (currently only one slot,
529 * slot 0, is currently since we don't do queueing)
530 */
531
Jeff Garzik828d09d2005-11-12 01:27:07 -0500532 opts = cmd_fis_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533 if (qc->tf.flags & ATA_TFLAG_WRITE)
534 opts |= AHCI_CMD_WRITE;
Jeff Garzika0ea7322005-06-04 01:13:15 -0400535 if (is_atapi_taskfile(&qc->tf))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536 opts |= AHCI_CMD_ATAPI;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537
538 pp->cmd_slot[0].opts = cpu_to_le32(opts);
539 pp->cmd_slot[0].status = 0;
540 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
541 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
542
543 /*
544 * Fill in command table information. First, the header,
545 * a SATA Register - Host to Device command FIS.
546 */
547 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
Jeff Garzika0ea7322005-06-04 01:13:15 -0400548 if (opts & AHCI_CMD_ATAPI) {
549 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
550 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
551 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552
553 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
554 return;
555
Jeff Garzik828d09d2005-11-12 01:27:07 -0500556 n_elem = ahci_fill_sg(qc);
557
558 pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559}
560
561static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
562{
Jeff Garzikea6ba102005-08-30 05:18:18 -0400563 void __iomem *mmio = ap->host_set->mmio_base;
564 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 u32 tmp;
566 int work;
567
568 /* stop DMA */
569 tmp = readl(port_mmio + PORT_CMD);
570 tmp &= ~PORT_CMD_START;
571 writel(tmp, port_mmio + PORT_CMD);
572
573 /* wait for engine to stop. TODO: this could be
574 * as long as 500 msec
575 */
576 work = 1000;
577 while (work-- > 0) {
578 tmp = readl(port_mmio + PORT_CMD);
579 if ((tmp & PORT_CMD_LIST_ON) == 0)
580 break;
581 udelay(10);
582 }
583
584 /* clear SATA phy error, if any */
585 tmp = readl(port_mmio + PORT_SCR_ERR);
586 writel(tmp, port_mmio + PORT_SCR_ERR);
587
588 /* if DRQ/BSY is set, device needs to be reset.
589 * if so, issue COMRESET
590 */
591 tmp = readl(port_mmio + PORT_TFDATA);
592 if (tmp & (ATA_BUSY | ATA_DRQ)) {
593 writel(0x301, port_mmio + PORT_SCR_CTL);
594 readl(port_mmio + PORT_SCR_CTL); /* flush */
595 udelay(10);
596 writel(0x300, port_mmio + PORT_SCR_CTL);
597 readl(port_mmio + PORT_SCR_CTL); /* flush */
598 }
599
600 /* re-start DMA */
601 tmp = readl(port_mmio + PORT_CMD);
602 tmp |= PORT_CMD_START;
603 writel(tmp, port_mmio + PORT_CMD);
604 readl(port_mmio + PORT_CMD); /* flush */
605
606 printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id);
607}
608
609static void ahci_eng_timeout(struct ata_port *ap)
610{
Jeff Garzikb8f61532005-08-25 22:01:20 -0400611 struct ata_host_set *host_set = ap->host_set;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400612 void __iomem *mmio = host_set->mmio_base;
613 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614 struct ata_queued_cmd *qc;
Jeff Garzikb8f61532005-08-25 22:01:20 -0400615 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616
617 DPRINTK("ENTER\n");
618
Jeff Garzikb8f61532005-08-25 22:01:20 -0400619 spin_lock_irqsave(&host_set->lock, flags);
620
Linus Torvalds1da177e2005-04-16 15:20:36 -0700621 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
622
623 qc = ata_qc_from_tag(ap, ap->active_tag);
624 if (!qc) {
625 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
626 ap->id);
627 } else {
628 /* hack alert! We cannot use the supplied completion
629 * function from inside the ->eh_strategy_handler() thread.
630 * libata is the only user of ->eh_strategy_handler() in
631 * any kernel, so the default scsi_done() assumes it is
632 * not being called from the SCSI EH.
633 */
634 qc->scsidone = scsi_finish_command;
Jeff Garzika7dac442005-10-30 04:44:42 -0500635 ata_qc_complete(qc, AC_ERR_OTHER);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636 }
637
Jeff Garzikb8f61532005-08-25 22:01:20 -0400638 spin_unlock_irqrestore(&host_set->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639}
640
641static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
642{
Jeff Garzikea6ba102005-08-30 05:18:18 -0400643 void __iomem *mmio = ap->host_set->mmio_base;
644 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645 u32 status, serr, ci;
646
647 serr = readl(port_mmio + PORT_SCR_ERR);
648 writel(serr, port_mmio + PORT_SCR_ERR);
649
650 status = readl(port_mmio + PORT_IRQ_STAT);
651 writel(status, port_mmio + PORT_IRQ_STAT);
652
653 ci = readl(port_mmio + PORT_CMD_ISSUE);
654 if (likely((ci & 0x1) == 0)) {
655 if (qc) {
656 ata_qc_complete(qc, 0);
657 qc = NULL;
658 }
659 }
660
661 if (status & PORT_IRQ_FATAL) {
662 ahci_intr_error(ap, status);
663 if (qc)
Jeff Garzika7dac442005-10-30 04:44:42 -0500664 ata_qc_complete(qc, AC_ERR_OTHER);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665 }
666
667 return 1;
668}
669
670static void ahci_irq_clear(struct ata_port *ap)
671{
672 /* TODO */
673}
674
675static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
676{
677 struct ata_host_set *host_set = dev_instance;
678 struct ahci_host_priv *hpriv;
679 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400680 void __iomem *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681 u32 irq_stat, irq_ack = 0;
682
683 VPRINTK("ENTER\n");
684
685 hpriv = host_set->private_data;
686 mmio = host_set->mmio_base;
687
688 /* sigh. 0xffffffff is a valid return from h/w */
689 irq_stat = readl(mmio + HOST_IRQ_STAT);
690 irq_stat &= hpriv->port_map;
691 if (!irq_stat)
692 return IRQ_NONE;
693
694 spin_lock(&host_set->lock);
695
696 for (i = 0; i < host_set->n_ports; i++) {
697 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700698
Jeff Garzik67846b32005-10-05 02:58:32 -0400699 if (!(irq_stat & (1 << i)))
700 continue;
701
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702 ap = host_set->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -0400703 if (ap) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704 struct ata_queued_cmd *qc;
705 qc = ata_qc_from_tag(ap, ap->active_tag);
Jeff Garzik67846b32005-10-05 02:58:32 -0400706 if (!ahci_host_intr(ap, qc))
707 if (ata_ratelimit()) {
708 struct pci_dev *pdev =
Jeff Garzika9524a72005-10-30 14:39:11 -0500709 to_pci_dev(ap->host_set->dev);
710 dev_printk(KERN_WARNING, &pdev->dev,
711 "unhandled interrupt on port %u\n",
712 i);
Jeff Garzik67846b32005-10-05 02:58:32 -0400713 }
714
715 VPRINTK("port %u\n", i);
716 } else {
717 VPRINTK("port %u (no irq)\n", i);
718 if (ata_ratelimit()) {
719 struct pci_dev *pdev =
Jeff Garzika9524a72005-10-30 14:39:11 -0500720 to_pci_dev(ap->host_set->dev);
721 dev_printk(KERN_WARNING, &pdev->dev,
722 "interrupt on disabled port %u\n", i);
Jeff Garzik67846b32005-10-05 02:58:32 -0400723 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700724 }
Jeff Garzik67846b32005-10-05 02:58:32 -0400725
726 irq_ack |= (1 << i);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727 }
728
729 if (irq_ack) {
730 writel(irq_ack, mmio + HOST_IRQ_STAT);
731 handled = 1;
732 }
733
734 spin_unlock(&host_set->lock);
735
736 VPRINTK("EXIT\n");
737
738 return IRQ_RETVAL(handled);
739}
740
741static int ahci_qc_issue(struct ata_queued_cmd *qc)
742{
743 struct ata_port *ap = qc->ap;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400744 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746 writel(1, port_mmio + PORT_CMD_ISSUE);
747 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
748
749 return 0;
750}
751
752static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
753 unsigned int port_idx)
754{
755 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
756 base = ahci_port_base_ul(base, port_idx);
757 VPRINTK("base now==0x%lx\n", base);
758
759 port->cmd_addr = base;
760 port->scr_addr = base + PORT_SCR;
761
762 VPRINTK("EXIT\n");
763}
764
765static int ahci_host_init(struct ata_probe_ent *probe_ent)
766{
767 struct ahci_host_priv *hpriv = probe_ent->private_data;
768 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
769 void __iomem *mmio = probe_ent->mmio_base;
770 u32 tmp, cap_save;
771 u16 tmp16;
772 unsigned int i, j, using_dac;
773 int rc;
774 void __iomem *port_mmio;
775
776 cap_save = readl(mmio + HOST_CAP);
777 cap_save &= ( (1<<28) | (1<<17) );
778 cap_save |= (1 << 27);
779
780 /* global controller reset */
781 tmp = readl(mmio + HOST_CTL);
782 if ((tmp & HOST_RESET) == 0) {
783 writel(tmp | HOST_RESET, mmio + HOST_CTL);
784 readl(mmio + HOST_CTL); /* flush */
785 }
786
787 /* reset must complete within 1 second, or
788 * the hardware should be considered fried.
789 */
790 ssleep(1);
791
792 tmp = readl(mmio + HOST_CTL);
793 if (tmp & HOST_RESET) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500794 dev_printk(KERN_ERR, &pdev->dev,
795 "controller reset failed (0x%x)\n", tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796 return -EIO;
797 }
798
799 writel(HOST_AHCI_EN, mmio + HOST_CTL);
800 (void) readl(mmio + HOST_CTL); /* flush */
801 writel(cap_save, mmio + HOST_CAP);
802 writel(0xf, mmio + HOST_PORTS_IMPL);
803 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
804
805 pci_read_config_word(pdev, 0x92, &tmp16);
806 tmp16 |= 0xf;
807 pci_write_config_word(pdev, 0x92, tmp16);
808
809 hpriv->cap = readl(mmio + HOST_CAP);
810 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
811 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
812
813 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
814 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
815
816 using_dac = hpriv->cap & HOST_CAP_64;
817 if (using_dac &&
818 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
819 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
820 if (rc) {
821 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
822 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500823 dev_printk(KERN_ERR, &pdev->dev,
824 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825 return rc;
826 }
827 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700828 } else {
829 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
830 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500831 dev_printk(KERN_ERR, &pdev->dev,
832 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833 return rc;
834 }
835 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
836 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500837 dev_printk(KERN_ERR, &pdev->dev,
838 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839 return rc;
840 }
841 }
842
843 for (i = 0; i < probe_ent->n_ports; i++) {
844#if 0 /* BIOSen initialize this incorrectly */
845 if (!(hpriv->port_map & (1 << i)))
846 continue;
847#endif
848
849 port_mmio = ahci_port_base(mmio, i);
850 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
851
852 ahci_setup_port(&probe_ent->port[i],
853 (unsigned long) mmio, i);
854
855 /* make sure port is not active */
856 tmp = readl(port_mmio + PORT_CMD);
857 VPRINTK("PORT_CMD 0x%x\n", tmp);
858 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
859 PORT_CMD_FIS_RX | PORT_CMD_START)) {
860 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
861 PORT_CMD_FIS_RX | PORT_CMD_START);
862 writel(tmp, port_mmio + PORT_CMD);
863 readl(port_mmio + PORT_CMD); /* flush */
864
865 /* spec says 500 msecs for each bit, so
866 * this is slightly incorrect.
867 */
868 msleep(500);
869 }
870
871 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
872
873 j = 0;
874 while (j < 100) {
875 msleep(10);
876 tmp = readl(port_mmio + PORT_SCR_STAT);
877 if ((tmp & 0xf) == 0x3)
878 break;
879 j++;
880 }
881
882 tmp = readl(port_mmio + PORT_SCR_ERR);
883 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
884 writel(tmp, port_mmio + PORT_SCR_ERR);
885
886 /* ack any pending irq events for this port */
887 tmp = readl(port_mmio + PORT_IRQ_STAT);
888 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
889 if (tmp)
890 writel(tmp, port_mmio + PORT_IRQ_STAT);
891
892 writel(1 << i, mmio + HOST_IRQ_STAT);
893
894 /* set irq mask (enables interrupts) */
895 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
896 }
897
898 tmp = readl(mmio + HOST_CTL);
899 VPRINTK("HOST_CTL 0x%x\n", tmp);
900 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
901 tmp = readl(mmio + HOST_CTL);
902 VPRINTK("HOST_CTL 0x%x\n", tmp);
903
904 pci_set_master(pdev);
905
906 return 0;
907}
908
Linus Torvalds1da177e2005-04-16 15:20:36 -0700909static void ahci_print_info(struct ata_probe_ent *probe_ent)
910{
911 struct ahci_host_priv *hpriv = probe_ent->private_data;
912 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
Jeff Garzikea6ba102005-08-30 05:18:18 -0400913 void __iomem *mmio = probe_ent->mmio_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914 u32 vers, cap, impl, speed;
915 const char *speed_s;
916 u16 cc;
917 const char *scc_s;
918
919 vers = readl(mmio + HOST_VERSION);
920 cap = hpriv->cap;
921 impl = hpriv->port_map;
922
923 speed = (cap >> 20) & 0xf;
924 if (speed == 1)
925 speed_s = "1.5";
926 else if (speed == 2)
927 speed_s = "3";
928 else
929 speed_s = "?";
930
931 pci_read_config_word(pdev, 0x0a, &cc);
932 if (cc == 0x0101)
933 scc_s = "IDE";
934 else if (cc == 0x0106)
935 scc_s = "SATA";
936 else if (cc == 0x0104)
937 scc_s = "RAID";
938 else
939 scc_s = "unknown";
940
Jeff Garzika9524a72005-10-30 14:39:11 -0500941 dev_printk(KERN_INFO, &pdev->dev,
942 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -0700943 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
944 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700945
946 (vers >> 24) & 0xff,
947 (vers >> 16) & 0xff,
948 (vers >> 8) & 0xff,
949 vers & 0xff,
950
951 ((cap >> 8) & 0x1f) + 1,
952 (cap & 0x1f) + 1,
953 speed_s,
954 impl,
955 scc_s);
956
Jeff Garzika9524a72005-10-30 14:39:11 -0500957 dev_printk(KERN_INFO, &pdev->dev,
958 "flags: "
Linus Torvalds1da177e2005-04-16 15:20:36 -0700959 "%s%s%s%s%s%s"
960 "%s%s%s%s%s%s%s\n"
961 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700962
963 cap & (1 << 31) ? "64bit " : "",
964 cap & (1 << 30) ? "ncq " : "",
965 cap & (1 << 28) ? "ilck " : "",
966 cap & (1 << 27) ? "stag " : "",
967 cap & (1 << 26) ? "pm " : "",
968 cap & (1 << 25) ? "led " : "",
969
970 cap & (1 << 24) ? "clo " : "",
971 cap & (1 << 19) ? "nz " : "",
972 cap & (1 << 18) ? "only " : "",
973 cap & (1 << 17) ? "pmp " : "",
974 cap & (1 << 15) ? "pio " : "",
975 cap & (1 << 14) ? "slum " : "",
976 cap & (1 << 13) ? "part " : ""
977 );
978}
979
980static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
981{
982 static int printed_version;
983 struct ata_probe_ent *probe_ent = NULL;
984 struct ahci_host_priv *hpriv;
985 unsigned long base;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400986 void __iomem *mmio_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700987 unsigned int board_idx = (unsigned int) ent->driver_data;
Jeff Garzik907f4672005-05-12 15:03:42 -0400988 int have_msi, pci_dev_busy = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700989 int rc;
990
991 VPRINTK("ENTER\n");
992
993 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -0500994 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700995
996 rc = pci_enable_device(pdev);
997 if (rc)
998 return rc;
999
1000 rc = pci_request_regions(pdev, DRV_NAME);
1001 if (rc) {
1002 pci_dev_busy = 1;
1003 goto err_out;
1004 }
1005
Jeff Garzik907f4672005-05-12 15:03:42 -04001006 if (pci_enable_msi(pdev) == 0)
1007 have_msi = 1;
1008 else {
1009 pci_intx(pdev, 1);
1010 have_msi = 0;
1011 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001012
1013 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1014 if (probe_ent == NULL) {
1015 rc = -ENOMEM;
Jeff Garzik907f4672005-05-12 15:03:42 -04001016 goto err_out_msi;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001017 }
1018
1019 memset(probe_ent, 0, sizeof(*probe_ent));
1020 probe_ent->dev = pci_dev_to_dev(pdev);
1021 INIT_LIST_HEAD(&probe_ent->node);
1022
Jeff Garzik374b1872005-08-30 05:42:52 -04001023 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024 if (mmio_base == NULL) {
1025 rc = -ENOMEM;
1026 goto err_out_free_ent;
1027 }
1028 base = (unsigned long) mmio_base;
1029
1030 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1031 if (!hpriv) {
1032 rc = -ENOMEM;
1033 goto err_out_iounmap;
1034 }
1035 memset(hpriv, 0, sizeof(*hpriv));
1036
1037 probe_ent->sht = ahci_port_info[board_idx].sht;
1038 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1039 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1040 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1041 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1042
1043 probe_ent->irq = pdev->irq;
1044 probe_ent->irq_flags = SA_SHIRQ;
1045 probe_ent->mmio_base = mmio_base;
1046 probe_ent->private_data = hpriv;
1047
Jeff Garzik4b0060f2005-06-04 00:50:22 -04001048 if (have_msi)
1049 hpriv->flags |= AHCI_FLAG_MSI;
Jeff Garzik907f4672005-05-12 15:03:42 -04001050
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051 /* initialize adapter */
1052 rc = ahci_host_init(probe_ent);
1053 if (rc)
1054 goto err_out_hpriv;
1055
1056 ahci_print_info(probe_ent);
1057
1058 /* FIXME: check ata_device_add return value */
1059 ata_device_add(probe_ent);
1060 kfree(probe_ent);
1061
1062 return 0;
1063
1064err_out_hpriv:
1065 kfree(hpriv);
1066err_out_iounmap:
Jeff Garzik374b1872005-08-30 05:42:52 -04001067 pci_iounmap(pdev, mmio_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001068err_out_free_ent:
1069 kfree(probe_ent);
Jeff Garzik907f4672005-05-12 15:03:42 -04001070err_out_msi:
1071 if (have_msi)
1072 pci_disable_msi(pdev);
1073 else
1074 pci_intx(pdev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001075 pci_release_regions(pdev);
1076err_out:
1077 if (!pci_dev_busy)
1078 pci_disable_device(pdev);
1079 return rc;
1080}
1081
Jeff Garzik907f4672005-05-12 15:03:42 -04001082static void ahci_remove_one (struct pci_dev *pdev)
1083{
1084 struct device *dev = pci_dev_to_dev(pdev);
1085 struct ata_host_set *host_set = dev_get_drvdata(dev);
1086 struct ahci_host_priv *hpriv = host_set->private_data;
1087 struct ata_port *ap;
1088 unsigned int i;
1089 int have_msi;
1090
1091 for (i = 0; i < host_set->n_ports; i++) {
1092 ap = host_set->ports[i];
1093
1094 scsi_remove_host(ap->host);
1095 }
1096
Jeff Garzik4b0060f2005-06-04 00:50:22 -04001097 have_msi = hpriv->flags & AHCI_FLAG_MSI;
Jeff Garzik907f4672005-05-12 15:03:42 -04001098 free_irq(host_set->irq, host_set);
Jeff Garzik907f4672005-05-12 15:03:42 -04001099
1100 for (i = 0; i < host_set->n_ports; i++) {
1101 ap = host_set->ports[i];
1102
1103 ata_scsi_release(ap->host);
1104 scsi_host_put(ap->host);
1105 }
1106
Jeff Garzike005f012005-08-30 04:18:28 -04001107 kfree(hpriv);
Jeff Garzik374b1872005-08-30 05:42:52 -04001108 pci_iounmap(pdev, host_set->mmio_base);
Jeff Garzikead5de92005-05-31 11:53:57 -04001109 kfree(host_set);
1110
Jeff Garzik907f4672005-05-12 15:03:42 -04001111 if (have_msi)
1112 pci_disable_msi(pdev);
1113 else
1114 pci_intx(pdev, 0);
1115 pci_release_regions(pdev);
Jeff Garzik907f4672005-05-12 15:03:42 -04001116 pci_disable_device(pdev);
1117 dev_set_drvdata(dev, NULL);
1118}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001119
1120static int __init ahci_init(void)
1121{
1122 return pci_module_init(&ahci_pci_driver);
1123}
1124
Linus Torvalds1da177e2005-04-16 15:20:36 -07001125static void __exit ahci_exit(void)
1126{
1127 pci_unregister_driver(&ahci_pci_driver);
1128}
1129
1130
1131MODULE_AUTHOR("Jeff Garzik");
1132MODULE_DESCRIPTION("AHCI SATA low-level driver");
1133MODULE_LICENSE("GPL");
1134MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04001135MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001136
1137module_init(ahci_init);
1138module_exit(ahci_exit);