blob: 78634dfc0f77e02776a9806f97ad01b124ce98c4 [file] [log] [blame]
Maxime Ripard03c4c712015-10-29 09:39:01 +01001/*
2 * Copyright (C) 2015 Free Electrons
3 * Copyright (C) 2015 NextThing Co
4 *
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13#include <linux/clk.h>
14#include <linux/component.h>
15#include <linux/of_address.h>
16#include <linux/regmap.h>
17#include <linux/reset.h>
18
19#include <drm/drmP.h>
20#include <drm/drm_atomic_helper.h>
21#include <drm/drm_crtc_helper.h>
22#include <drm/drm_panel.h>
23
24#include "sun4i_backend.h"
25#include "sun4i_drv.h"
26#include "sun4i_tcon.h"
27
28#define SUN4I_TVE_EN_REG 0x000
29#define SUN4I_TVE_EN_DAC_MAP_MASK GENMASK(19, 4)
30#define SUN4I_TVE_EN_DAC_MAP(dac, out) (((out) & 0xf) << (dac + 1) * 4)
31#define SUN4I_TVE_EN_ENABLE BIT(0)
32
33#define SUN4I_TVE_CFG0_REG 0x004
34#define SUN4I_TVE_CFG0_DAC_CONTROL_54M BIT(26)
35#define SUN4I_TVE_CFG0_CORE_DATAPATH_54M BIT(25)
36#define SUN4I_TVE_CFG0_CORE_CONTROL_54M BIT(24)
37#define SUN4I_TVE_CFG0_YC_EN BIT(17)
38#define SUN4I_TVE_CFG0_COMP_EN BIT(16)
39#define SUN4I_TVE_CFG0_RES(x) ((x) & 0xf)
40#define SUN4I_TVE_CFG0_RES_480i SUN4I_TVE_CFG0_RES(0)
41#define SUN4I_TVE_CFG0_RES_576i SUN4I_TVE_CFG0_RES(1)
42
43#define SUN4I_TVE_DAC0_REG 0x008
44#define SUN4I_TVE_DAC0_CLOCK_INVERT BIT(24)
45#define SUN4I_TVE_DAC0_LUMA(x) (((x) & 3) << 20)
46#define SUN4I_TVE_DAC0_LUMA_0_4 SUN4I_TVE_DAC0_LUMA(3)
47#define SUN4I_TVE_DAC0_CHROMA(x) (((x) & 3) << 18)
48#define SUN4I_TVE_DAC0_CHROMA_0_75 SUN4I_TVE_DAC0_CHROMA(3)
49#define SUN4I_TVE_DAC0_INTERNAL_DAC(x) (((x) & 3) << 16)
50#define SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS SUN4I_TVE_DAC0_INTERNAL_DAC(3)
51#define SUN4I_TVE_DAC0_DAC_EN(dac) BIT(dac)
52
53#define SUN4I_TVE_NOTCH_REG 0x00c
54#define SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(dac, x) ((4 - (x)) << (dac * 3))
55
56#define SUN4I_TVE_CHROMA_FREQ_REG 0x010
57
58#define SUN4I_TVE_PORCH_REG 0x014
59#define SUN4I_TVE_PORCH_BACK(x) ((x) << 16)
60#define SUN4I_TVE_PORCH_FRONT(x) (x)
61
62#define SUN4I_TVE_LINE_REG 0x01c
63#define SUN4I_TVE_LINE_FIRST(x) ((x) << 16)
64#define SUN4I_TVE_LINE_NUMBER(x) (x)
65
66#define SUN4I_TVE_LEVEL_REG 0x020
67#define SUN4I_TVE_LEVEL_BLANK(x) ((x) << 16)
68#define SUN4I_TVE_LEVEL_BLACK(x) (x)
69
70#define SUN4I_TVE_DAC1_REG 0x024
71#define SUN4I_TVE_DAC1_AMPLITUDE(dac, x) ((x) << (dac * 8))
72
73#define SUN4I_TVE_DETECT_STA_REG 0x038
74#define SUN4I_TVE_DETECT_STA_DAC(dac) BIT((dac * 8))
75#define SUN4I_TVE_DETECT_STA_UNCONNECTED 0
76#define SUN4I_TVE_DETECT_STA_CONNECTED 1
77#define SUN4I_TVE_DETECT_STA_GROUND 2
78
79#define SUN4I_TVE_CB_CR_LVL_REG 0x10c
80#define SUN4I_TVE_CB_CR_LVL_CR_BURST(x) ((x) << 8)
81#define SUN4I_TVE_CB_CR_LVL_CB_BURST(x) (x)
82
83#define SUN4I_TVE_TINT_BURST_PHASE_REG 0x110
84#define SUN4I_TVE_TINT_BURST_PHASE_CHROMA(x) (x)
85
86#define SUN4I_TVE_BURST_WIDTH_REG 0x114
87#define SUN4I_TVE_BURST_WIDTH_BREEZEWAY(x) ((x) << 16)
88#define SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(x) ((x) << 8)
89#define SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(x) (x)
90
91#define SUN4I_TVE_CB_CR_GAIN_REG 0x118
92#define SUN4I_TVE_CB_CR_GAIN_CR(x) ((x) << 8)
93#define SUN4I_TVE_CB_CR_GAIN_CB(x) (x)
94
95#define SUN4I_TVE_SYNC_VBI_REG 0x11c
96#define SUN4I_TVE_SYNC_VBI_SYNC(x) ((x) << 16)
97#define SUN4I_TVE_SYNC_VBI_VBLANK(x) (x)
98
99#define SUN4I_TVE_ACTIVE_LINE_REG 0x124
100#define SUN4I_TVE_ACTIVE_LINE(x) (x)
101
102#define SUN4I_TVE_CHROMA_REG 0x128
103#define SUN4I_TVE_CHROMA_COMP_GAIN(x) ((x) & 3)
104#define SUN4I_TVE_CHROMA_COMP_GAIN_50 SUN4I_TVE_CHROMA_COMP_GAIN(2)
105
106#define SUN4I_TVE_12C_REG 0x12c
107#define SUN4I_TVE_12C_NOTCH_WIDTH_WIDE BIT(8)
108#define SUN4I_TVE_12C_COMP_YUV_EN BIT(0)
109
110#define SUN4I_TVE_RESYNC_REG 0x130
111#define SUN4I_TVE_RESYNC_FIELD BIT(31)
112#define SUN4I_TVE_RESYNC_LINE(x) ((x) << 16)
113#define SUN4I_TVE_RESYNC_PIXEL(x) (x)
114
115#define SUN4I_TVE_SLAVE_REG 0x134
116
117#define SUN4I_TVE_WSS_DATA2_REG 0x244
118
119struct color_gains {
120 u16 cb;
121 u16 cr;
122};
123
124struct burst_levels {
125 u16 cb;
126 u16 cr;
127};
128
129struct video_levels {
130 u16 black;
131 u16 blank;
132};
133
134struct resync_parameters {
135 bool field;
136 u16 line;
137 u16 pixel;
138};
139
140struct tv_mode {
141 char *name;
142
143 u32 mode;
144 u32 chroma_freq;
145 u16 back_porch;
146 u16 front_porch;
147 u16 line_number;
148 u16 vblank_level;
149
150 u32 hdisplay;
151 u16 hfront_porch;
152 u16 hsync_len;
153 u16 hback_porch;
154
155 u32 vdisplay;
156 u16 vfront_porch;
157 u16 vsync_len;
158 u16 vback_porch;
159
160 bool yc_en;
161 bool dac3_en;
162 bool dac_bit25_en;
163
164 struct color_gains *color_gains;
165 struct burst_levels *burst_levels;
166 struct video_levels *video_levels;
167 struct resync_parameters *resync_params;
168};
169
170struct sun4i_tv {
171 struct drm_connector connector;
172 struct drm_encoder encoder;
173
174 struct clk *clk;
175 struct regmap *regs;
176 struct reset_control *reset;
177
178 struct sun4i_drv *drv;
179};
180
181struct tv_mode tv_modes[] = {
182};
183
184static inline struct sun4i_tv *
185drm_encoder_to_sun4i_tv(struct drm_encoder *encoder)
186{
187 return container_of(encoder, struct sun4i_tv,
188 encoder);
189}
190
191static inline struct sun4i_tv *
192drm_connector_to_sun4i_tv(struct drm_connector *connector)
193{
194 return container_of(connector, struct sun4i_tv,
195 connector);
196}
197
198/*
199 * FIXME: If only the drm_display_mode private field was usable, this
200 * could go away...
201 *
202 * So far, it doesn't seem to be preserved when the mode is passed by
203 * to mode_set for some reason.
204 */
205static struct tv_mode *sun4i_tv_find_tv_by_mode(struct drm_display_mode *mode)
206{
207 int i;
208
209 /* First try to identify the mode by name */
210 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
211 struct tv_mode *tv_mode = &tv_modes[i];
212
213 DRM_DEBUG_DRIVER("Comparing mode %s vs %s",
214 mode->name, tv_mode->name);
215
216 if (!strcmp(mode->name, tv_mode->name))
217 return tv_mode;
218 }
219
220 /* Then by number of lines */
221 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
222 struct tv_mode *tv_mode = &tv_modes[i];
223
224 DRM_DEBUG_DRIVER("Comparing mode %s vs %s (X: %d vs %d)",
225 mode->name, tv_mode->name,
226 mode->vdisplay, tv_mode->vdisplay);
227
228 if (mode->vdisplay == tv_mode->vdisplay)
229 return tv_mode;
230 }
231
232 return NULL;
233}
234
235static void sun4i_tv_mode_to_drm_mode(struct tv_mode *tv_mode,
236 struct drm_display_mode *mode)
237{
238 DRM_DEBUG_DRIVER("Creating mode %s\n", mode->name);
239
240 mode->type = DRM_MODE_TYPE_DRIVER;
241 mode->clock = 13500;
242 mode->flags = DRM_MODE_FLAG_INTERLACE;
243
244 mode->hdisplay = tv_mode->hdisplay;
245 mode->hsync_start = mode->hdisplay + tv_mode->hfront_porch;
246 mode->hsync_end = mode->hsync_start + tv_mode->hsync_len;
247 mode->htotal = mode->hsync_end + tv_mode->hback_porch;
248
249 mode->vdisplay = tv_mode->vdisplay;
250 mode->vsync_start = mode->vdisplay + tv_mode->vfront_porch;
251 mode->vsync_end = mode->vsync_start + tv_mode->vsync_len;
252 mode->vtotal = mode->vsync_end + tv_mode->vback_porch;
253}
254
255static int sun4i_tv_atomic_check(struct drm_encoder *encoder,
256 struct drm_crtc_state *crtc_state,
257 struct drm_connector_state *conn_state)
258{
259 return 0;
260}
261
262static void sun4i_tv_disable(struct drm_encoder *encoder)
263{
264 struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
265 struct sun4i_drv *drv = tv->drv;
266 struct sun4i_tcon *tcon = drv->tcon;
267
268 DRM_DEBUG_DRIVER("Disabling the TV Output\n");
269
270 sun4i_tcon_channel_disable(tcon, 1);
271
272 regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
273 SUN4I_TVE_EN_ENABLE,
274 0);
275 sun4i_backend_disable_color_correction(drv->backend);
276}
277
278static void sun4i_tv_enable(struct drm_encoder *encoder)
279{
280 struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
281 struct sun4i_drv *drv = tv->drv;
282 struct sun4i_tcon *tcon = drv->tcon;
283
284 DRM_DEBUG_DRIVER("Enabling the TV Output\n");
285
286 sun4i_backend_apply_color_correction(drv->backend);
287
288 regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
289 SUN4I_TVE_EN_ENABLE,
290 SUN4I_TVE_EN_ENABLE);
291
292 sun4i_tcon_channel_enable(tcon, 1);
293}
294
295static void sun4i_tv_mode_set(struct drm_encoder *encoder,
296 struct drm_display_mode *mode,
297 struct drm_display_mode *adjusted_mode)
298{
299 struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
300 struct sun4i_drv *drv = tv->drv;
301 struct sun4i_tcon *tcon = drv->tcon;
302 struct tv_mode *tv_mode = sun4i_tv_find_tv_by_mode(mode);
303
304 sun4i_tcon1_mode_set(tcon, mode);
305
306 /* Enable and map the DAC to the output */
307 regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
308 SUN4I_TVE_EN_DAC_MAP_MASK,
309 SUN4I_TVE_EN_DAC_MAP(0, 1) |
310 SUN4I_TVE_EN_DAC_MAP(1, 2) |
311 SUN4I_TVE_EN_DAC_MAP(2, 3) |
312 SUN4I_TVE_EN_DAC_MAP(3, 4));
313
314 /* Set PAL settings */
315 regmap_write(tv->regs, SUN4I_TVE_CFG0_REG,
316 tv_mode->mode |
317 (tv_mode->yc_en ? SUN4I_TVE_CFG0_YC_EN : 0) |
318 SUN4I_TVE_CFG0_COMP_EN |
319 SUN4I_TVE_CFG0_DAC_CONTROL_54M |
320 SUN4I_TVE_CFG0_CORE_DATAPATH_54M |
321 SUN4I_TVE_CFG0_CORE_CONTROL_54M);
322
323 /* Configure the DAC for a composite output */
324 regmap_write(tv->regs, SUN4I_TVE_DAC0_REG,
325 SUN4I_TVE_DAC0_DAC_EN(0) |
326 (tv_mode->dac3_en ? SUN4I_TVE_DAC0_DAC_EN(3) : 0) |
327 SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS |
328 SUN4I_TVE_DAC0_CHROMA_0_75 |
329 SUN4I_TVE_DAC0_LUMA_0_4 |
330 SUN4I_TVE_DAC0_CLOCK_INVERT |
331 (tv_mode->dac_bit25_en ? BIT(25) : 0) |
332 BIT(30));
333
334 /* Configure the sample delay between DAC0 and the other DAC */
335 regmap_write(tv->regs, SUN4I_TVE_NOTCH_REG,
336 SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(1, 0) |
337 SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(2, 0));
338
339 regmap_write(tv->regs, SUN4I_TVE_CHROMA_FREQ_REG,
340 tv_mode->chroma_freq);
341
342 /* Set the front and back porch */
343 regmap_write(tv->regs, SUN4I_TVE_PORCH_REG,
344 SUN4I_TVE_PORCH_BACK(tv_mode->back_porch) |
345 SUN4I_TVE_PORCH_FRONT(tv_mode->front_porch));
346
347 /* Set the lines setup */
348 regmap_write(tv->regs, SUN4I_TVE_LINE_REG,
349 SUN4I_TVE_LINE_FIRST(22) |
350 SUN4I_TVE_LINE_NUMBER(tv_mode->line_number));
351
352 regmap_write(tv->regs, SUN4I_TVE_LEVEL_REG,
353 SUN4I_TVE_LEVEL_BLANK(tv_mode->video_levels->blank) |
354 SUN4I_TVE_LEVEL_BLACK(tv_mode->video_levels->black));
355
356 regmap_write(tv->regs, SUN4I_TVE_DAC1_REG,
357 SUN4I_TVE_DAC1_AMPLITUDE(0, 0x18) |
358 SUN4I_TVE_DAC1_AMPLITUDE(1, 0x18) |
359 SUN4I_TVE_DAC1_AMPLITUDE(2, 0x18) |
360 SUN4I_TVE_DAC1_AMPLITUDE(3, 0x18));
361
362 regmap_write(tv->regs, SUN4I_TVE_CB_CR_LVL_REG,
363 SUN4I_TVE_CB_CR_LVL_CB_BURST(tv_mode->burst_levels->cb) |
364 SUN4I_TVE_CB_CR_LVL_CR_BURST(tv_mode->burst_levels->cr));
365
366 /* Set burst width for a composite output */
367 regmap_write(tv->regs, SUN4I_TVE_BURST_WIDTH_REG,
368 SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(126) |
369 SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(68) |
370 SUN4I_TVE_BURST_WIDTH_BREEZEWAY(22));
371
372 regmap_write(tv->regs, SUN4I_TVE_CB_CR_GAIN_REG,
373 SUN4I_TVE_CB_CR_GAIN_CB(tv_mode->color_gains->cb) |
374 SUN4I_TVE_CB_CR_GAIN_CR(tv_mode->color_gains->cr));
375
376 regmap_write(tv->regs, SUN4I_TVE_SYNC_VBI_REG,
377 SUN4I_TVE_SYNC_VBI_SYNC(0x10) |
378 SUN4I_TVE_SYNC_VBI_VBLANK(tv_mode->vblank_level));
379
380 regmap_write(tv->regs, SUN4I_TVE_ACTIVE_LINE_REG,
381 SUN4I_TVE_ACTIVE_LINE(1440));
382
383 /* Set composite chroma gain to 50 % */
384 regmap_write(tv->regs, SUN4I_TVE_CHROMA_REG,
385 SUN4I_TVE_CHROMA_COMP_GAIN_50);
386
387 regmap_write(tv->regs, SUN4I_TVE_12C_REG,
388 SUN4I_TVE_12C_COMP_YUV_EN |
389 SUN4I_TVE_12C_NOTCH_WIDTH_WIDE);
390
391 regmap_write(tv->regs, SUN4I_TVE_RESYNC_REG,
392 SUN4I_TVE_RESYNC_PIXEL(tv_mode->resync_params->pixel) |
393 SUN4I_TVE_RESYNC_LINE(tv_mode->resync_params->line) |
394 (tv_mode->resync_params->field ?
395 SUN4I_TVE_RESYNC_FIELD : 0));
396
397 regmap_write(tv->regs, SUN4I_TVE_SLAVE_REG, 0);
398
399 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
400}
401
402static struct drm_encoder_helper_funcs sun4i_tv_helper_funcs = {
403 .atomic_check = sun4i_tv_atomic_check,
404 .disable = sun4i_tv_disable,
405 .enable = sun4i_tv_enable,
406 .mode_set = sun4i_tv_mode_set,
407};
408
409static void sun4i_tv_destroy(struct drm_encoder *encoder)
410{
411 drm_encoder_cleanup(encoder);
412}
413
414static struct drm_encoder_funcs sun4i_tv_funcs = {
415 .destroy = sun4i_tv_destroy,
416};
417
418static int sun4i_tv_comp_get_modes(struct drm_connector *connector)
419{
420 int i;
421
422 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
423 struct drm_display_mode *mode = drm_mode_create(connector->dev);
424 struct tv_mode *tv_mode = &tv_modes[i];
425
426 strcpy(mode->name, tv_mode->name);
427
428 sun4i_tv_mode_to_drm_mode(tv_mode, mode);
429 drm_mode_probed_add(connector, mode);
430 }
431
432 return i;
433}
434
435static int sun4i_tv_comp_mode_valid(struct drm_connector *connector,
436 struct drm_display_mode *mode)
437{
438 /* TODO */
439 return MODE_OK;
440}
441
442static struct drm_encoder *
443sun4i_tv_comp_best_encoder(struct drm_connector *connector)
444{
445 struct sun4i_tv *tv = drm_connector_to_sun4i_tv(connector);
446
447 return &tv->encoder;
448}
449
450static struct drm_connector_helper_funcs sun4i_tv_comp_connector_helper_funcs = {
451 .get_modes = sun4i_tv_comp_get_modes,
452 .mode_valid = sun4i_tv_comp_mode_valid,
453 .best_encoder = sun4i_tv_comp_best_encoder,
454};
455
456static enum drm_connector_status
457sun4i_tv_comp_connector_detect(struct drm_connector *connector, bool force)
458{
459 return connector_status_connected;
460}
461
462static void
463sun4i_tv_comp_connector_destroy(struct drm_connector *connector)
464{
465 drm_connector_cleanup(connector);
466}
467
468static struct drm_connector_funcs sun4i_tv_comp_connector_funcs = {
469 .dpms = drm_atomic_helper_connector_dpms,
470 .detect = sun4i_tv_comp_connector_detect,
471 .fill_modes = drm_helper_probe_single_connector_modes,
472 .destroy = sun4i_tv_comp_connector_destroy,
473 .reset = drm_atomic_helper_connector_reset,
474 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
475 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
476};
477
478static struct regmap_config sun4i_tv_regmap_config = {
479 .reg_bits = 32,
480 .val_bits = 32,
481 .reg_stride = 4,
482 .max_register = SUN4I_TVE_WSS_DATA2_REG,
483 .name = "tv-encoder",
484};
485
486static int sun4i_tv_bind(struct device *dev, struct device *master,
487 void *data)
488{
489 struct platform_device *pdev = to_platform_device(dev);
490 struct drm_device *drm = data;
491 struct sun4i_drv *drv = drm->dev_private;
492 struct sun4i_tv *tv;
493 struct resource *res;
494 void __iomem *regs;
495 int ret;
496
497 tv = devm_kzalloc(dev, sizeof(*tv), GFP_KERNEL);
498 if (!tv)
499 return -ENOMEM;
500 tv->drv = drv;
501 dev_set_drvdata(dev, tv);
502
503 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
504 regs = devm_ioremap_resource(dev, res);
505 if (IS_ERR(regs)) {
506 dev_err(dev, "Couldn't map the TV encoder registers\n");
507 return PTR_ERR(regs);
508 }
509
510 tv->regs = devm_regmap_init_mmio(dev, regs,
511 &sun4i_tv_regmap_config);
512 if (IS_ERR(tv->regs)) {
513 dev_err(dev, "Couldn't create the TV encoder regmap\n");
514 return PTR_ERR(tv->regs);
515 }
516
517 tv->reset = devm_reset_control_get(dev, NULL);
518 if (IS_ERR(tv->reset)) {
519 dev_err(dev, "Couldn't get our reset line\n");
520 return PTR_ERR(tv->reset);
521 }
522
523 ret = reset_control_deassert(tv->reset);
524 if (ret) {
525 dev_err(dev, "Couldn't deassert our reset line\n");
526 return ret;
527 }
528
529 tv->clk = devm_clk_get(dev, NULL);
530 if (IS_ERR(tv->clk)) {
531 dev_err(dev, "Couldn't get the TV encoder clock\n");
532 ret = PTR_ERR(tv->clk);
533 goto err_assert_reset;
534 }
535 clk_prepare_enable(tv->clk);
536
537 drm_encoder_helper_add(&tv->encoder,
538 &sun4i_tv_helper_funcs);
539 ret = drm_encoder_init(drm,
540 &tv->encoder,
541 &sun4i_tv_funcs,
542 DRM_MODE_ENCODER_TVDAC,
543 NULL);
544 if (ret) {
545 dev_err(dev, "Couldn't initialise the TV encoder\n");
546 goto err_disable_clk;
547 }
548
549 tv->encoder.possible_crtcs = BIT(0);
550
551 drm_connector_helper_add(&tv->connector,
552 &sun4i_tv_comp_connector_helper_funcs);
553 ret = drm_connector_init(drm, &tv->connector,
554 &sun4i_tv_comp_connector_funcs,
555 DRM_MODE_CONNECTOR_Composite);
556 if (ret) {
557 dev_err(dev,
558 "Couldn't initialise the Composite connector\n");
559 goto err_cleanup_connector;
560 }
561 tv->connector.interlace_allowed = true;
562
563 drm_mode_connector_attach_encoder(&tv->connector, &tv->encoder);
564
565 return 0;
566
567err_cleanup_connector:
568 drm_encoder_cleanup(&tv->encoder);
569err_disable_clk:
570 clk_disable_unprepare(tv->clk);
571err_assert_reset:
572 reset_control_assert(tv->reset);
573 return ret;
574}
575
576static void sun4i_tv_unbind(struct device *dev, struct device *master,
577 void *data)
578{
579 struct sun4i_tv *tv = dev_get_drvdata(dev);
580
581 drm_connector_cleanup(&tv->connector);
582 drm_encoder_cleanup(&tv->encoder);
583 clk_disable_unprepare(tv->clk);
584}
585
586static struct component_ops sun4i_tv_ops = {
587 .bind = sun4i_tv_bind,
588 .unbind = sun4i_tv_unbind,
589};
590
591static int sun4i_tv_probe(struct platform_device *pdev)
592{
593 return component_add(&pdev->dev, &sun4i_tv_ops);
594}
595
596static int sun4i_tv_remove(struct platform_device *pdev)
597{
598 component_del(&pdev->dev, &sun4i_tv_ops);
599
600 return 0;
601}
602
603static const struct of_device_id sun4i_tv_of_table[] = {
604 { .compatible = "allwinner,sun4i-a10-tv-encoder" },
605 { }
606};
607MODULE_DEVICE_TABLE(of, sun4i_tv_of_table);
608
609static struct platform_driver sun4i_tv_platform_driver = {
610 .probe = sun4i_tv_probe,
611 .remove = sun4i_tv_remove,
612 .driver = {
613 .name = "sun4i-tve",
614 .of_match_table = sun4i_tv_of_table,
615 },
616};
617module_platform_driver(sun4i_tv_platform_driver);
618
619MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
620MODULE_DESCRIPTION("Allwinner A10 TV Encoder Driver");
621MODULE_LICENSE("GPL");