blob: 4a47df5a9ff9c076ddee640a437eca7f7c9348c9 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*******************************************************************************
2
3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Recieve
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * Under typical operation, the receive unit (RU) is start once,
110 * and the controller happily fills RFDs as frames arrive. If
111 * replacement RFDs cannot be allocated, or the RU goes non-active,
112 * the RU must be restarted. Frame arrival generates an interrupt,
113 * and Rx indication and re-allocation happen in the same context,
114 * therefore no locking is required. A software-generated interrupt
115 * is generated from the watchdog to recover from a failed allocation
116 * senario where all Rx resources have been indicated and none re-
117 * placed.
118 *
119 * V. Miscellaneous
120 *
121 * VLAN offloading of tagging, stripping and filtering is not
122 * supported, but driver will accommodate the extra 4-byte VLAN tag
123 * for processing by upper layers. Tx/Rx Checksum offloading is not
124 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
125 * not supported (hardware limitation).
126 *
127 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
128 *
129 * Thanks to JC (jchapman@katalix.com) for helping with
130 * testing/troubleshooting the development driver.
131 *
132 * TODO:
133 * o several entry points race with dev->close
134 * o check for tx-no-resources/stop Q races with tx clean/wake Q
135 */
136
137#include <linux/config.h>
138#include <linux/module.h>
139#include <linux/moduleparam.h>
140#include <linux/kernel.h>
141#include <linux/types.h>
142#include <linux/slab.h>
143#include <linux/delay.h>
144#include <linux/init.h>
145#include <linux/pci.h>
146#include <linux/netdevice.h>
147#include <linux/etherdevice.h>
148#include <linux/mii.h>
149#include <linux/if_vlan.h>
150#include <linux/skbuff.h>
151#include <linux/ethtool.h>
152#include <linux/string.h>
153#include <asm/unaligned.h>
154
155
156#define DRV_NAME "e100"
157#define DRV_EXT "-NAPI"
Malli Chilakala042e2fb2005-04-28 19:20:14 -0700158#define DRV_VERSION "3.4.8-k2"DRV_EXT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
Malli Chilakala042e2fb2005-04-28 19:20:14 -0700160#define DRV_COPYRIGHT "Copyright(c) 1999-2005 Intel Corporation"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161#define PFX DRV_NAME ": "
162
163#define E100_WATCHDOG_PERIOD (2 * HZ)
164#define E100_NAPI_WEIGHT 16
165
166MODULE_DESCRIPTION(DRV_DESCRIPTION);
167MODULE_AUTHOR(DRV_COPYRIGHT);
168MODULE_LICENSE("GPL");
169MODULE_VERSION(DRV_VERSION);
170
171static int debug = 3;
172module_param(debug, int, 0);
173MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
174#define DPRINTK(nlevel, klevel, fmt, args...) \
175 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
176 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
177 __FUNCTION__ , ## args))
178
179#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
180 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
181 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
182static struct pci_device_id e100_id_table[] = {
183 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
184 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
185 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
186 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
187 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
188 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
189 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
190 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
191 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
192 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
193 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
194 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
195 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
196 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
197 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
198 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
199 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
200 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
201 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
202 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
203 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
204 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
205 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
206 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
207 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
208 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
209 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
210 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
212 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
Malli Chilakala042e2fb2005-04-28 19:20:14 -0700213 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
214 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
215 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
216 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
217 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
219 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
220 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
221 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
222 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
Malli Chilakala042e2fb2005-04-28 19:20:14 -0700223 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224 { 0, }
225};
226MODULE_DEVICE_TABLE(pci, e100_id_table);
227
228enum mac {
229 mac_82557_D100_A = 0,
230 mac_82557_D100_B = 1,
231 mac_82557_D100_C = 2,
232 mac_82558_D101_A4 = 4,
233 mac_82558_D101_B0 = 5,
234 mac_82559_D101M = 8,
235 mac_82559_D101S = 9,
236 mac_82550_D102 = 12,
237 mac_82550_D102_C = 13,
238 mac_82551_E = 14,
239 mac_82551_F = 15,
240 mac_82551_10 = 16,
241 mac_unknown = 0xFF,
242};
243
244enum phy {
245 phy_100a = 0x000003E0,
246 phy_100c = 0x035002A8,
247 phy_82555_tx = 0x015002A8,
248 phy_nsc_tx = 0x5C002000,
249 phy_82562_et = 0x033002A8,
250 phy_82562_em = 0x032002A8,
251 phy_82562_ek = 0x031002A8,
252 phy_82562_eh = 0x017002A8,
253 phy_unknown = 0xFFFFFFFF,
254};
255
256/* CSR (Control/Status Registers) */
257struct csr {
258 struct {
259 u8 status;
260 u8 stat_ack;
261 u8 cmd_lo;
262 u8 cmd_hi;
263 u32 gen_ptr;
264 } scb;
265 u32 port;
266 u16 flash_ctrl;
267 u8 eeprom_ctrl_lo;
268 u8 eeprom_ctrl_hi;
269 u32 mdi_ctrl;
270 u32 rx_dma_count;
271};
272
273enum scb_status {
274 rus_ready = 0x10,
275 rus_mask = 0x3C,
276};
277
Malli Chilakala1f533672005-04-28 19:17:20 -0700278enum ru_state {
279 RU_SUSPENDED = 0,
280 RU_RUNNING = 1,
281 RU_UNINITIALIZED = -1,
282};
283
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284enum scb_stat_ack {
285 stat_ack_not_ours = 0x00,
286 stat_ack_sw_gen = 0x04,
287 stat_ack_rnr = 0x10,
288 stat_ack_cu_idle = 0x20,
289 stat_ack_frame_rx = 0x40,
290 stat_ack_cu_cmd_done = 0x80,
291 stat_ack_not_present = 0xFF,
292 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
293 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
294};
295
296enum scb_cmd_hi {
297 irq_mask_none = 0x00,
298 irq_mask_all = 0x01,
299 irq_sw_gen = 0x02,
300};
301
302enum scb_cmd_lo {
303 cuc_nop = 0x00,
304 ruc_start = 0x01,
305 ruc_load_base = 0x06,
306 cuc_start = 0x10,
307 cuc_resume = 0x20,
308 cuc_dump_addr = 0x40,
309 cuc_dump_stats = 0x50,
310 cuc_load_base = 0x60,
311 cuc_dump_reset = 0x70,
312};
313
314enum cuc_dump {
315 cuc_dump_complete = 0x0000A005,
316 cuc_dump_reset_complete = 0x0000A007,
317};
318
319enum port {
320 software_reset = 0x0000,
321 selftest = 0x0001,
322 selective_reset = 0x0002,
323};
324
325enum eeprom_ctrl_lo {
326 eesk = 0x01,
327 eecs = 0x02,
328 eedi = 0x04,
329 eedo = 0x08,
330};
331
332enum mdi_ctrl {
333 mdi_write = 0x04000000,
334 mdi_read = 0x08000000,
335 mdi_ready = 0x10000000,
336};
337
338enum eeprom_op {
339 op_write = 0x05,
340 op_read = 0x06,
341 op_ewds = 0x10,
342 op_ewen = 0x13,
343};
344
345enum eeprom_offsets {
346 eeprom_cnfg_mdix = 0x03,
347 eeprom_id = 0x0A,
348 eeprom_config_asf = 0x0D,
349 eeprom_smbus_addr = 0x90,
350};
351
352enum eeprom_cnfg_mdix {
353 eeprom_mdix_enabled = 0x0080,
354};
355
356enum eeprom_id {
357 eeprom_id_wol = 0x0020,
358};
359
360enum eeprom_config_asf {
361 eeprom_asf = 0x8000,
362 eeprom_gcl = 0x4000,
363};
364
365enum cb_status {
366 cb_complete = 0x8000,
367 cb_ok = 0x2000,
368};
369
370enum cb_command {
371 cb_nop = 0x0000,
372 cb_iaaddr = 0x0001,
373 cb_config = 0x0002,
374 cb_multi = 0x0003,
375 cb_tx = 0x0004,
376 cb_ucode = 0x0005,
377 cb_dump = 0x0006,
378 cb_tx_sf = 0x0008,
379 cb_cid = 0x1f00,
380 cb_i = 0x2000,
381 cb_s = 0x4000,
382 cb_el = 0x8000,
383};
384
385struct rfd {
386 u16 status;
387 u16 command;
388 u32 link;
389 u32 rbd;
390 u16 actual_size;
391 u16 size;
392};
393
394struct rx {
395 struct rx *next, *prev;
396 struct sk_buff *skb;
397 dma_addr_t dma_addr;
398};
399
400#if defined(__BIG_ENDIAN_BITFIELD)
401#define X(a,b) b,a
402#else
403#define X(a,b) a,b
404#endif
405struct config {
406/*0*/ u8 X(byte_count:6, pad0:2);
407/*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
408/*2*/ u8 adaptive_ifs;
409/*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
410 term_write_cache_line:1), pad3:4);
411/*4*/ u8 X(rx_dma_max_count:7, pad4:1);
412/*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
413/*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
414 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
415 rx_discard_overruns:1), rx_save_bad_frames:1);
416/*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
417 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
418 tx_dynamic_tbd:1);
419/*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
420/*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
421 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
422/*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
423 loopback:2);
424/*11*/ u8 X(linear_priority:3, pad11:5);
425/*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
426/*13*/ u8 ip_addr_lo;
427/*14*/ u8 ip_addr_hi;
428/*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
429 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
430 pad15_2:1), crs_or_cdt:1);
431/*16*/ u8 fc_delay_lo;
432/*17*/ u8 fc_delay_hi;
433/*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
434 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
435/*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
436 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
437 full_duplex_force:1), full_duplex_pin:1);
438/*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
439/*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
440/*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
441 u8 pad_d102[9];
442};
443
444#define E100_MAX_MULTICAST_ADDRS 64
445struct multi {
446 u16 count;
447 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
448};
449
450/* Important: keep total struct u32-aligned */
451#define UCODE_SIZE 134
452struct cb {
453 u16 status;
454 u16 command;
455 u32 link;
456 union {
457 u8 iaaddr[ETH_ALEN];
458 u32 ucode[UCODE_SIZE];
459 struct config config;
460 struct multi multi;
461 struct {
462 u32 tbd_array;
463 u16 tcb_byte_count;
464 u8 threshold;
465 u8 tbd_count;
466 struct {
467 u32 buf_addr;
468 u16 size;
469 u16 eol;
470 } tbd;
471 } tcb;
472 u32 dump_buffer_addr;
473 } u;
474 struct cb *next, *prev;
475 dma_addr_t dma_addr;
476 struct sk_buff *skb;
477};
478
479enum loopback {
480 lb_none = 0, lb_mac = 1, lb_phy = 3,
481};
482
483struct stats {
484 u32 tx_good_frames, tx_max_collisions, tx_late_collisions,
485 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
486 tx_multiple_collisions, tx_total_collisions;
487 u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
488 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
489 rx_short_frame_errors;
490 u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
491 u16 xmt_tco_frames, rcv_tco_frames;
492 u32 complete;
493};
494
495struct mem {
496 struct {
497 u32 signature;
498 u32 result;
499 } selftest;
500 struct stats stats;
501 u8 dump_buf[596];
502};
503
504struct param_range {
505 u32 min;
506 u32 max;
507 u32 count;
508};
509
510struct params {
511 struct param_range rfds;
512 struct param_range cbs;
513};
514
515struct nic {
516 /* Begin: frequently used values: keep adjacent for cache effect */
517 u32 msg_enable ____cacheline_aligned;
518 struct net_device *netdev;
519 struct pci_dev *pdev;
520
521 struct rx *rxs ____cacheline_aligned;
522 struct rx *rx_to_use;
523 struct rx *rx_to_clean;
524 struct rfd blank_rfd;
Malli Chilakala1f533672005-04-28 19:17:20 -0700525 enum ru_state ru_running;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526
527 spinlock_t cb_lock ____cacheline_aligned;
528 spinlock_t cmd_lock;
529 struct csr __iomem *csr;
530 enum scb_cmd_lo cuc_cmd;
531 unsigned int cbs_avail;
532 struct cb *cbs;
533 struct cb *cb_to_use;
534 struct cb *cb_to_send;
535 struct cb *cb_to_clean;
536 u16 tx_command;
537 /* End: frequently used values: keep adjacent for cache effect */
538
539 enum {
540 ich = (1 << 0),
541 promiscuous = (1 << 1),
542 multicast_all = (1 << 2),
543 wol_magic = (1 << 3),
544 ich_10h_workaround = (1 << 4),
545 } flags ____cacheline_aligned;
546
547 enum mac mac;
548 enum phy phy;
549 struct params params;
550 struct net_device_stats net_stats;
551 struct timer_list watchdog;
552 struct timer_list blink_timer;
553 struct mii_if_info mii;
Malli Chilakala2acdb1e2005-04-28 19:16:58 -0700554 struct work_struct tx_timeout_task;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555 enum loopback loopback;
556
557 struct mem *mem;
558 dma_addr_t dma_addr;
559
560 dma_addr_t cbs_dma_addr;
561 u8 adaptive_ifs;
562 u8 tx_threshold;
563 u32 tx_frames;
564 u32 tx_collisions;
565 u32 tx_deferred;
566 u32 tx_single_collisions;
567 u32 tx_multiple_collisions;
568 u32 tx_fc_pause;
569 u32 tx_tco_frames;
570
571 u32 rx_fc_pause;
572 u32 rx_fc_unsupported;
573 u32 rx_tco_frames;
574 u32 rx_over_length_errors;
575
576 u8 rev_id;
577 u16 leds;
578 u16 eeprom_wc;
579 u16 eeprom[256];
580};
581
582static inline void e100_write_flush(struct nic *nic)
583{
584 /* Flush previous PCI writes through intermediate bridges
585 * by doing a benign read */
586 (void)readb(&nic->csr->scb.status);
587}
588
589static inline void e100_enable_irq(struct nic *nic)
590{
591 unsigned long flags;
592
593 spin_lock_irqsave(&nic->cmd_lock, flags);
594 writeb(irq_mask_none, &nic->csr->scb.cmd_hi);
595 spin_unlock_irqrestore(&nic->cmd_lock, flags);
596 e100_write_flush(nic);
597}
598
599static inline void e100_disable_irq(struct nic *nic)
600{
601 unsigned long flags;
602
603 spin_lock_irqsave(&nic->cmd_lock, flags);
604 writeb(irq_mask_all, &nic->csr->scb.cmd_hi);
605 spin_unlock_irqrestore(&nic->cmd_lock, flags);
606 e100_write_flush(nic);
607}
608
609static void e100_hw_reset(struct nic *nic)
610{
611 /* Put CU and RU into idle with a selective reset to get
612 * device off of PCI bus */
613 writel(selective_reset, &nic->csr->port);
614 e100_write_flush(nic); udelay(20);
615
616 /* Now fully reset device */
617 writel(software_reset, &nic->csr->port);
618 e100_write_flush(nic); udelay(20);
619
620 /* Mask off our interrupt line - it's unmasked after reset */
621 e100_disable_irq(nic);
622}
623
624static int e100_self_test(struct nic *nic)
625{
626 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
627
628 /* Passing the self-test is a pretty good indication
629 * that the device can DMA to/from host memory */
630
631 nic->mem->selftest.signature = 0;
632 nic->mem->selftest.result = 0xFFFFFFFF;
633
634 writel(selftest | dma_addr, &nic->csr->port);
635 e100_write_flush(nic);
636 /* Wait 10 msec for self-test to complete */
637 msleep(10);
638
639 /* Interrupts are enabled after self-test */
640 e100_disable_irq(nic);
641
642 /* Check results of self-test */
643 if(nic->mem->selftest.result != 0) {
644 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
645 nic->mem->selftest.result);
646 return -ETIMEDOUT;
647 }
648 if(nic->mem->selftest.signature == 0) {
649 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
650 return -ETIMEDOUT;
651 }
652
653 return 0;
654}
655
656static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)
657{
658 u32 cmd_addr_data[3];
659 u8 ctrl;
660 int i, j;
661
662 /* Three cmds: write/erase enable, write data, write/erase disable */
663 cmd_addr_data[0] = op_ewen << (addr_len - 2);
664 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
665 cpu_to_le16(data);
666 cmd_addr_data[2] = op_ewds << (addr_len - 2);
667
668 /* Bit-bang cmds to write word to eeprom */
669 for(j = 0; j < 3; j++) {
670
671 /* Chip select */
672 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
673 e100_write_flush(nic); udelay(4);
674
675 for(i = 31; i >= 0; i--) {
676 ctrl = (cmd_addr_data[j] & (1 << i)) ?
677 eecs | eedi : eecs;
678 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
679 e100_write_flush(nic); udelay(4);
680
681 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
682 e100_write_flush(nic); udelay(4);
683 }
684 /* Wait 10 msec for cmd to complete */
685 msleep(10);
686
687 /* Chip deselect */
688 writeb(0, &nic->csr->eeprom_ctrl_lo);
689 e100_write_flush(nic); udelay(4);
690 }
691};
692
693/* General technique stolen from the eepro100 driver - very clever */
694static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
695{
696 u32 cmd_addr_data;
697 u16 data = 0;
698 u8 ctrl;
699 int i;
700
701 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
702
703 /* Chip select */
704 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
705 e100_write_flush(nic); udelay(4);
706
707 /* Bit-bang to read word from eeprom */
708 for(i = 31; i >= 0; i--) {
709 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
710 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
711 e100_write_flush(nic); udelay(4);
712
713 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
714 e100_write_flush(nic); udelay(4);
715
716 /* Eeprom drives a dummy zero to EEDO after receiving
717 * complete address. Use this to adjust addr_len. */
718 ctrl = readb(&nic->csr->eeprom_ctrl_lo);
719 if(!(ctrl & eedo) && i > 16) {
720 *addr_len -= (i - 16);
721 i = 17;
722 }
723
724 data = (data << 1) | (ctrl & eedo ? 1 : 0);
725 }
726
727 /* Chip deselect */
728 writeb(0, &nic->csr->eeprom_ctrl_lo);
729 e100_write_flush(nic); udelay(4);
730
731 return le16_to_cpu(data);
732};
733
734/* Load entire EEPROM image into driver cache and validate checksum */
735static int e100_eeprom_load(struct nic *nic)
736{
737 u16 addr, addr_len = 8, checksum = 0;
738
739 /* Try reading with an 8-bit addr len to discover actual addr len */
740 e100_eeprom_read(nic, &addr_len, 0);
741 nic->eeprom_wc = 1 << addr_len;
742
743 for(addr = 0; addr < nic->eeprom_wc; addr++) {
744 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
745 if(addr < nic->eeprom_wc - 1)
746 checksum += cpu_to_le16(nic->eeprom[addr]);
747 }
748
749 /* The checksum, stored in the last word, is calculated such that
750 * the sum of words should be 0xBABA */
751 checksum = le16_to_cpu(0xBABA - checksum);
752 if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {
753 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
754 return -EAGAIN;
755 }
756
757 return 0;
758}
759
760/* Save (portion of) driver EEPROM cache to device and update checksum */
761static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
762{
763 u16 addr, addr_len = 8, checksum = 0;
764
765 /* Try reading with an 8-bit addr len to discover actual addr len */
766 e100_eeprom_read(nic, &addr_len, 0);
767 nic->eeprom_wc = 1 << addr_len;
768
769 if(start + count >= nic->eeprom_wc)
770 return -EINVAL;
771
772 for(addr = start; addr < start + count; addr++)
773 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
774
775 /* The checksum, stored in the last word, is calculated such that
776 * the sum of words should be 0xBABA */
777 for(addr = 0; addr < nic->eeprom_wc - 1; addr++)
778 checksum += cpu_to_le16(nic->eeprom[addr]);
779 nic->eeprom[nic->eeprom_wc - 1] = le16_to_cpu(0xBABA - checksum);
780 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
781 nic->eeprom[nic->eeprom_wc - 1]);
782
783 return 0;
784}
785
Malli Chilakala962082b2005-04-28 19:19:46 -0700786#define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700787static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
788{
789 unsigned long flags;
790 unsigned int i;
791 int err = 0;
792
793 spin_lock_irqsave(&nic->cmd_lock, flags);
794
795 /* Previous command is accepted when SCB clears */
796 for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
797 if(likely(!readb(&nic->csr->scb.cmd_lo)))
798 break;
799 cpu_relax();
800 if(unlikely(i > (E100_WAIT_SCB_TIMEOUT >> 1)))
801 udelay(5);
802 }
803 if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
804 err = -EAGAIN;
805 goto err_unlock;
806 }
807
808 if(unlikely(cmd != cuc_resume))
809 writel(dma_addr, &nic->csr->scb.gen_ptr);
810 writeb(cmd, &nic->csr->scb.cmd_lo);
811
812err_unlock:
813 spin_unlock_irqrestore(&nic->cmd_lock, flags);
814
815 return err;
816}
817
818static inline int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
819 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
820{
821 struct cb *cb;
822 unsigned long flags;
823 int err = 0;
824
825 spin_lock_irqsave(&nic->cb_lock, flags);
826
827 if(unlikely(!nic->cbs_avail)) {
828 err = -ENOMEM;
829 goto err_unlock;
830 }
831
832 cb = nic->cb_to_use;
833 nic->cb_to_use = cb->next;
834 nic->cbs_avail--;
835 cb->skb = skb;
836
837 if(unlikely(!nic->cbs_avail))
838 err = -ENOSPC;
839
840 cb_prepare(nic, cb, skb);
841
842 /* Order is important otherwise we'll be in a race with h/w:
843 * set S-bit in current first, then clear S-bit in previous. */
844 cb->command |= cpu_to_le16(cb_s);
845 wmb();
846 cb->prev->command &= cpu_to_le16(~cb_s);
847
848 while(nic->cb_to_send != nic->cb_to_use) {
849 if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
850 nic->cb_to_send->dma_addr))) {
851 /* Ok, here's where things get sticky. It's
852 * possible that we can't schedule the command
853 * because the controller is too busy, so
854 * let's just queue the command and try again
855 * when another command is scheduled. */
Malli Chilakala962082b2005-04-28 19:19:46 -0700856 if(err == -ENOSPC) {
857 //request a reset
858 schedule_work(&nic->tx_timeout_task);
859 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860 break;
861 } else {
862 nic->cuc_cmd = cuc_resume;
863 nic->cb_to_send = nic->cb_to_send->next;
864 }
865 }
866
867err_unlock:
868 spin_unlock_irqrestore(&nic->cb_lock, flags);
869
870 return err;
871}
872
873static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
874{
875 u32 data_out = 0;
876 unsigned int i;
877
878 writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
879
880 for(i = 0; i < 100; i++) {
881 udelay(20);
882 if((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)
883 break;
884 }
885
886 DPRINTK(HW, DEBUG,
887 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
888 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
889 return (u16)data_out;
890}
891
892static int mdio_read(struct net_device *netdev, int addr, int reg)
893{
894 return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);
895}
896
897static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
898{
899 mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);
900}
901
902static void e100_get_defaults(struct nic *nic)
903{
Malli Chilakala962082b2005-04-28 19:19:46 -0700904 struct param_range rfds = { .min = 16, .max = 256, .count = 64 };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905 struct param_range cbs = { .min = 64, .max = 256, .count = 64 };
906
907 pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
908 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
909 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;
910 if(nic->mac == mac_unknown)
911 nic->mac = mac_82557_D100_A;
912
913 nic->params.rfds = rfds;
914 nic->params.cbs = cbs;
915
916 /* Quadwords to DMA into FIFO before starting frame transmit */
917 nic->tx_threshold = 0xE0;
918
Malli Chilakala962082b2005-04-28 19:19:46 -0700919 /* no interrupt for every tx completion, delay = 256us if not 557*/
920 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
921 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700922
923 /* Template for a freshly allocated RFD */
924 nic->blank_rfd.command = cpu_to_le16(cb_el);
925 nic->blank_rfd.rbd = 0xFFFFFFFF;
926 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
927
928 /* MII setup */
929 nic->mii.phy_id_mask = 0x1F;
930 nic->mii.reg_num_mask = 0x1F;
931 nic->mii.dev = nic->netdev;
932 nic->mii.mdio_read = mdio_read;
933 nic->mii.mdio_write = mdio_write;
934}
935
936static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
937{
938 struct config *config = &cb->u.config;
939 u8 *c = (u8 *)config;
940
941 cb->command = cpu_to_le16(cb_config);
942
943 memset(config, 0, sizeof(struct config));
944
945 config->byte_count = 0x16; /* bytes in this struct */
946 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
947 config->direct_rx_dma = 0x1; /* reserved */
948 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
949 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
950 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
951 config->tx_underrun_retry = 0x3; /* # of underrun retries */
952 config->mii_mode = 0x1; /* 1=MII mode, 0=503 mode */
953 config->pad10 = 0x6;
954 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
955 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
956 config->ifs = 0x6; /* x16 = inter frame spacing */
957 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
958 config->pad15_1 = 0x1;
959 config->pad15_2 = 0x1;
960 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
961 config->fc_delay_hi = 0x40; /* time delay for fc frame */
962 config->tx_padding = 0x1; /* 1=pad short frames */
963 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
964 config->pad18 = 0x1;
965 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
966 config->pad20_1 = 0x1F;
967 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
968 config->pad21_1 = 0x5;
969
970 config->adaptive_ifs = nic->adaptive_ifs;
971 config->loopback = nic->loopback;
972
973 if(nic->mii.force_media && nic->mii.full_duplex)
974 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
975
976 if(nic->flags & promiscuous || nic->loopback) {
977 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
978 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
979 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
980 }
981
982 if(nic->flags & multicast_all)
983 config->multicast_all = 0x1; /* 1=accept, 0=no */
984
Malli Chilakala6bdacb12005-04-28 19:17:54 -0700985 /* disable WoL when up */
986 if(netif_running(nic->netdev) || !(nic->flags & wol_magic))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700987 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
988
989 if(nic->mac >= mac_82558_D101_A4) {
990 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
991 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
992 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
993 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
994 if(nic->mac >= mac_82559_D101M)
995 config->tno_intr = 0x1; /* TCO stats enable */
996 else
997 config->standard_stat_counter = 0x0;
998 }
999
1000 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1001 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1002 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1003 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1004 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1005 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1006}
1007
1008static void e100_load_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1009{
1010 int i;
1011 static const u32 ucode[UCODE_SIZE] = {
1012 /* NFS packets are misinterpreted as TCO packets and
1013 * incorrectly routed to the BMC over SMBus. This
1014 * microcode patch checks the fragmented IP bit in the
1015 * NFS/UDP header to distinguish between NFS and TCO. */
1016 0x0EF70E36, 0x1FFF1FFF, 0x1FFF1FFF, 0x1FFF1FFF, 0x1FFF1FFF,
1017 0x1FFF1FFF, 0x00906E41, 0x00800E3C, 0x00E00E39, 0x00000000,
1018 0x00906EFD, 0x00900EFD, 0x00E00EF8,
1019 };
1020
1021 if(nic->mac == mac_82551_F || nic->mac == mac_82551_10) {
1022 for(i = 0; i < UCODE_SIZE; i++)
1023 cb->u.ucode[i] = cpu_to_le32(ucode[i]);
1024 cb->command = cpu_to_le16(cb_ucode);
1025 } else
1026 cb->command = cpu_to_le16(cb_nop);
1027}
1028
1029static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1030 struct sk_buff *skb)
1031{
1032 cb->command = cpu_to_le16(cb_iaaddr);
1033 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1034}
1035
1036static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1037{
1038 cb->command = cpu_to_le16(cb_dump);
1039 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1040 offsetof(struct mem, dump_buf));
1041}
1042
1043#define NCONFIG_AUTO_SWITCH 0x0080
1044#define MII_NSC_CONG MII_RESV1
1045#define NSC_CONG_ENABLE 0x0100
1046#define NSC_CONG_TXREADY 0x0400
1047#define ADVERTISE_FC_SUPPORTED 0x0400
1048static int e100_phy_init(struct nic *nic)
1049{
1050 struct net_device *netdev = nic->netdev;
1051 u32 addr;
1052 u16 bmcr, stat, id_lo, id_hi, cong;
1053
1054 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1055 for(addr = 0; addr < 32; addr++) {
1056 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1057 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1058 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1059 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1060 if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1061 break;
1062 }
1063 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1064 if(addr == 32)
1065 return -EAGAIN;
1066
1067 /* Selected the phy and isolate the rest */
1068 for(addr = 0; addr < 32; addr++) {
1069 if(addr != nic->mii.phy_id) {
1070 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1071 } else {
1072 bmcr = mdio_read(netdev, addr, MII_BMCR);
1073 mdio_write(netdev, addr, MII_BMCR,
1074 bmcr & ~BMCR_ISOLATE);
1075 }
1076 }
1077
1078 /* Get phy ID */
1079 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1080 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1081 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1082 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1083
1084 /* Handle National tx phys */
1085#define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1086 if((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1087 /* Disable congestion control */
1088 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1089 cong |= NSC_CONG_TXREADY;
1090 cong &= ~NSC_CONG_ENABLE;
1091 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1092 }
1093
1094 if((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1095 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1096 (nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled)))
1097 /* enable/disable MDI/MDI-X auto-switching */
1098 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1099 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1100
1101 return 0;
1102}
1103
1104static int e100_hw_init(struct nic *nic)
1105{
1106 int err;
1107
1108 e100_hw_reset(nic);
1109
1110 DPRINTK(HW, ERR, "e100_hw_init\n");
1111 if(!in_interrupt() && (err = e100_self_test(nic)))
1112 return err;
1113
1114 if((err = e100_phy_init(nic)))
1115 return err;
1116 if((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1117 return err;
1118 if((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1119 return err;
1120 if((err = e100_exec_cb(nic, NULL, e100_load_ucode)))
1121 return err;
1122 if((err = e100_exec_cb(nic, NULL, e100_configure)))
1123 return err;
1124 if((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1125 return err;
1126 if((err = e100_exec_cmd(nic, cuc_dump_addr,
1127 nic->dma_addr + offsetof(struct mem, stats))))
1128 return err;
1129 if((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1130 return err;
1131
1132 e100_disable_irq(nic);
1133
1134 return 0;
1135}
1136
1137static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1138{
1139 struct net_device *netdev = nic->netdev;
1140 struct dev_mc_list *list = netdev->mc_list;
1141 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1142
1143 cb->command = cpu_to_le16(cb_multi);
1144 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1145 for(i = 0; list && i < count; i++, list = list->next)
1146 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1147 ETH_ALEN);
1148}
1149
1150static void e100_set_multicast_list(struct net_device *netdev)
1151{
1152 struct nic *nic = netdev_priv(netdev);
1153
1154 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1155 netdev->mc_count, netdev->flags);
1156
1157 if(netdev->flags & IFF_PROMISC)
1158 nic->flags |= promiscuous;
1159 else
1160 nic->flags &= ~promiscuous;
1161
1162 if(netdev->flags & IFF_ALLMULTI ||
1163 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1164 nic->flags |= multicast_all;
1165 else
1166 nic->flags &= ~multicast_all;
1167
1168 e100_exec_cb(nic, NULL, e100_configure);
1169 e100_exec_cb(nic, NULL, e100_multi);
1170}
1171
1172static void e100_update_stats(struct nic *nic)
1173{
1174 struct net_device_stats *ns = &nic->net_stats;
1175 struct stats *s = &nic->mem->stats;
1176 u32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1177 (nic->mac < mac_82559_D101M) ? (u32 *)&s->xmt_tco_frames :
1178 &s->complete;
1179
1180 /* Device's stats reporting may take several microseconds to
1181 * complete, so where always waiting for results of the
1182 * previous command. */
1183
1184 if(*complete == le32_to_cpu(cuc_dump_reset_complete)) {
1185 *complete = 0;
1186 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1187 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1188 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1189 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1190 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1191 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1192 ns->collisions += nic->tx_collisions;
1193 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1194 le32_to_cpu(s->tx_lost_crs);
1195 ns->rx_dropped += le32_to_cpu(s->rx_resource_errors);
1196 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1197 nic->rx_over_length_errors;
1198 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1199 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1200 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1201 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1202 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1203 le32_to_cpu(s->rx_alignment_errors) +
1204 le32_to_cpu(s->rx_short_frame_errors) +
1205 le32_to_cpu(s->rx_cdt_errors);
1206 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1207 nic->tx_single_collisions +=
1208 le32_to_cpu(s->tx_single_collisions);
1209 nic->tx_multiple_collisions +=
1210 le32_to_cpu(s->tx_multiple_collisions);
1211 if(nic->mac >= mac_82558_D101_A4) {
1212 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1213 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1214 nic->rx_fc_unsupported +=
1215 le32_to_cpu(s->fc_rcv_unsupported);
1216 if(nic->mac >= mac_82559_D101M) {
1217 nic->tx_tco_frames +=
1218 le16_to_cpu(s->xmt_tco_frames);
1219 nic->rx_tco_frames +=
1220 le16_to_cpu(s->rcv_tco_frames);
1221 }
1222 }
1223 }
1224
Malli Chilakala1f533672005-04-28 19:17:20 -07001225
1226 if(e100_exec_cmd(nic, cuc_dump_reset, 0))
1227 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001228}
1229
1230static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1231{
1232 /* Adjust inter-frame-spacing (IFS) between two transmits if
1233 * we're getting collisions on a half-duplex connection. */
1234
1235 if(duplex == DUPLEX_HALF) {
1236 u32 prev = nic->adaptive_ifs;
1237 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1238
1239 if((nic->tx_frames / 32 < nic->tx_collisions) &&
1240 (nic->tx_frames > min_frames)) {
1241 if(nic->adaptive_ifs < 60)
1242 nic->adaptive_ifs += 5;
1243 } else if (nic->tx_frames < min_frames) {
1244 if(nic->adaptive_ifs >= 5)
1245 nic->adaptive_ifs -= 5;
1246 }
1247 if(nic->adaptive_ifs != prev)
1248 e100_exec_cb(nic, NULL, e100_configure);
1249 }
1250}
1251
1252static void e100_watchdog(unsigned long data)
1253{
1254 struct nic *nic = (struct nic *)data;
1255 struct ethtool_cmd cmd;
1256
1257 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1258
1259 /* mii library handles link maintenance tasks */
1260
1261 mii_ethtool_gset(&nic->mii, &cmd);
1262
1263 if(mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1264 DPRINTK(LINK, INFO, "link up, %sMbps, %s-duplex\n",
1265 cmd.speed == SPEED_100 ? "100" : "10",
1266 cmd.duplex == DUPLEX_FULL ? "full" : "half");
1267 } else if(!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1268 DPRINTK(LINK, INFO, "link down\n");
1269 }
1270
1271 mii_check_link(&nic->mii);
1272
1273 /* Software generated interrupt to recover from (rare) Rx
1274 * allocation failure.
1275 * Unfortunately have to use a spinlock to not re-enable interrupts
1276 * accidentally, due to hardware that shares a register between the
1277 * interrupt mask bit and the SW Interrupt generation bit */
1278 spin_lock_irq(&nic->cmd_lock);
1279 writeb(readb(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1280 spin_unlock_irq(&nic->cmd_lock);
1281 e100_write_flush(nic);
1282
1283 e100_update_stats(nic);
1284 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1285
1286 if(nic->mac <= mac_82557_D100_C)
1287 /* Issue a multicast command to workaround a 557 lock up */
1288 e100_set_multicast_list(nic->netdev);
1289
1290 if(nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1291 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1292 nic->flags |= ich_10h_workaround;
1293 else
1294 nic->flags &= ~ich_10h_workaround;
1295
1296 mod_timer(&nic->watchdog, jiffies + E100_WATCHDOG_PERIOD);
1297}
1298
1299static inline void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1300 struct sk_buff *skb)
1301{
1302 cb->command = nic->tx_command;
Malli Chilakala962082b2005-04-28 19:19:46 -07001303 /* interrupt every 16 packets regardless of delay */
1304 if((nic->cbs_avail & ~15) == nic->cbs_avail) cb->command |= cb_i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001305 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1306 cb->u.tcb.tcb_byte_count = 0;
1307 cb->u.tcb.threshold = nic->tx_threshold;
1308 cb->u.tcb.tbd_count = 1;
1309 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1310 skb->data, skb->len, PCI_DMA_TODEVICE));
Malli Chilakala962082b2005-04-28 19:19:46 -07001311 // check for mapping failure?
Linus Torvalds1da177e2005-04-16 15:20:36 -07001312 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1313}
1314
1315static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1316{
1317 struct nic *nic = netdev_priv(netdev);
1318 int err;
1319
1320 if(nic->flags & ich_10h_workaround) {
1321 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1322 Issue a NOP command followed by a 1us delay before
1323 issuing the Tx command. */
Malli Chilakala1f533672005-04-28 19:17:20 -07001324 if(e100_exec_cmd(nic, cuc_nop, 0))
1325 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001326 udelay(1);
1327 }
1328
1329 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1330
1331 switch(err) {
1332 case -ENOSPC:
1333 /* We queued the skb, but now we're out of space. */
1334 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1335 netif_stop_queue(netdev);
1336 break;
1337 case -ENOMEM:
1338 /* This is a hard error - log it. */
1339 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1340 netif_stop_queue(netdev);
1341 return 1;
1342 }
1343
1344 netdev->trans_start = jiffies;
1345 return 0;
1346}
1347
1348static inline int e100_tx_clean(struct nic *nic)
1349{
1350 struct cb *cb;
1351 int tx_cleaned = 0;
1352
1353 spin_lock(&nic->cb_lock);
1354
1355 DPRINTK(TX_DONE, DEBUG, "cb->status = 0x%04X\n",
1356 nic->cb_to_clean->status);
1357
1358 /* Clean CBs marked complete */
1359 for(cb = nic->cb_to_clean;
1360 cb->status & cpu_to_le16(cb_complete);
1361 cb = nic->cb_to_clean = cb->next) {
1362 if(likely(cb->skb != NULL)) {
1363 nic->net_stats.tx_packets++;
1364 nic->net_stats.tx_bytes += cb->skb->len;
1365
1366 pci_unmap_single(nic->pdev,
1367 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1368 le16_to_cpu(cb->u.tcb.tbd.size),
1369 PCI_DMA_TODEVICE);
1370 dev_kfree_skb_any(cb->skb);
1371 cb->skb = NULL;
1372 tx_cleaned = 1;
1373 }
1374 cb->status = 0;
1375 nic->cbs_avail++;
1376 }
1377
1378 spin_unlock(&nic->cb_lock);
1379
1380 /* Recover from running out of Tx resources in xmit_frame */
1381 if(unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1382 netif_wake_queue(nic->netdev);
1383
1384 return tx_cleaned;
1385}
1386
1387static void e100_clean_cbs(struct nic *nic)
1388{
1389 if(nic->cbs) {
1390 while(nic->cbs_avail != nic->params.cbs.count) {
1391 struct cb *cb = nic->cb_to_clean;
1392 if(cb->skb) {
1393 pci_unmap_single(nic->pdev,
1394 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1395 le16_to_cpu(cb->u.tcb.tbd.size),
1396 PCI_DMA_TODEVICE);
1397 dev_kfree_skb(cb->skb);
1398 }
1399 nic->cb_to_clean = nic->cb_to_clean->next;
1400 nic->cbs_avail++;
1401 }
1402 pci_free_consistent(nic->pdev,
1403 sizeof(struct cb) * nic->params.cbs.count,
1404 nic->cbs, nic->cbs_dma_addr);
1405 nic->cbs = NULL;
1406 nic->cbs_avail = 0;
1407 }
1408 nic->cuc_cmd = cuc_start;
1409 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1410 nic->cbs;
1411}
1412
1413static int e100_alloc_cbs(struct nic *nic)
1414{
1415 struct cb *cb;
1416 unsigned int i, count = nic->params.cbs.count;
1417
1418 nic->cuc_cmd = cuc_start;
1419 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1420 nic->cbs_avail = 0;
1421
1422 nic->cbs = pci_alloc_consistent(nic->pdev,
1423 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1424 if(!nic->cbs)
1425 return -ENOMEM;
1426
1427 for(cb = nic->cbs, i = 0; i < count; cb++, i++) {
1428 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1429 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1430
1431 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1432 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1433 ((i+1) % count) * sizeof(struct cb));
1434 cb->skb = NULL;
1435 }
1436
1437 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1438 nic->cbs_avail = count;
1439
1440 return 0;
1441}
1442
Malli Chilakala1f533672005-04-28 19:17:20 -07001443static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001444{
Malli Chilakala1f533672005-04-28 19:17:20 -07001445 if(!nic->rxs) return;
1446 if(RU_SUSPENDED != nic->ru_running) return;
1447
1448 /* handle init time starts */
1449 if(!rx) rx = nic->rxs;
1450
Linus Torvalds1da177e2005-04-16 15:20:36 -07001451 /* (Re)start RU if suspended or idle and RFA is non-NULL */
Malli Chilakala1f533672005-04-28 19:17:20 -07001452 if(rx->skb) {
1453 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1454 nic->ru_running = RU_RUNNING;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001455 }
1456}
1457
1458#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1459static inline int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1460{
1461 if(!(rx->skb = dev_alloc_skb(RFD_BUF_LEN + NET_IP_ALIGN)))
1462 return -ENOMEM;
1463
1464 /* Align, init, and map the RFD. */
1465 rx->skb->dev = nic->netdev;
1466 skb_reserve(rx->skb, NET_IP_ALIGN);
1467 memcpy(rx->skb->data, &nic->blank_rfd, sizeof(struct rfd));
1468 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1469 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1470
Malli Chilakala1f533672005-04-28 19:17:20 -07001471 if(pci_dma_mapping_error(rx->dma_addr)) {
1472 dev_kfree_skb_any(rx->skb);
1473 rx->skb = 0;
1474 rx->dma_addr = 0;
1475 return -ENOMEM;
1476 }
1477
Linus Torvalds1da177e2005-04-16 15:20:36 -07001478 /* Link the RFD to end of RFA by linking previous RFD to
1479 * this one, and clearing EL bit of previous. */
1480 if(rx->prev->skb) {
1481 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1482 put_unaligned(cpu_to_le32(rx->dma_addr),
1483 (u32 *)&prev_rfd->link);
1484 wmb();
1485 prev_rfd->command &= ~cpu_to_le16(cb_el);
1486 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1487 sizeof(struct rfd), PCI_DMA_TODEVICE);
1488 }
1489
1490 return 0;
1491}
1492
1493static inline int e100_rx_indicate(struct nic *nic, struct rx *rx,
1494 unsigned int *work_done, unsigned int work_to_do)
1495{
1496 struct sk_buff *skb = rx->skb;
1497 struct rfd *rfd = (struct rfd *)skb->data;
1498 u16 rfd_status, actual_size;
1499
1500 if(unlikely(work_done && *work_done >= work_to_do))
1501 return -EAGAIN;
1502
1503 /* Need to sync before taking a peek at cb_complete bit */
1504 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1505 sizeof(struct rfd), PCI_DMA_FROMDEVICE);
1506 rfd_status = le16_to_cpu(rfd->status);
1507
1508 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1509
1510 /* If data isn't ready, nothing to indicate */
1511 if(unlikely(!(rfd_status & cb_complete)))
Malli Chilakala1f533672005-04-28 19:17:20 -07001512 return -ENODATA;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001513
1514 /* Get actual data size */
1515 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1516 if(unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1517 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1518
1519 /* Get data */
1520 pci_unmap_single(nic->pdev, rx->dma_addr,
1521 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1522
Malli Chilakala1f533672005-04-28 19:17:20 -07001523 /* this allows for a fast restart without re-enabling interrupts */
1524 if(le16_to_cpu(rfd->command) & cb_el)
1525 nic->ru_running = RU_SUSPENDED;
1526
Linus Torvalds1da177e2005-04-16 15:20:36 -07001527 /* Pull off the RFD and put the actual data (minus eth hdr) */
1528 skb_reserve(skb, sizeof(struct rfd));
1529 skb_put(skb, actual_size);
1530 skb->protocol = eth_type_trans(skb, nic->netdev);
1531
1532 if(unlikely(!(rfd_status & cb_ok))) {
1533 /* Don't indicate if hardware indicates errors */
1534 nic->net_stats.rx_dropped++;
1535 dev_kfree_skb_any(skb);
1536 } else if(actual_size > nic->netdev->mtu + VLAN_ETH_HLEN) {
1537 /* Don't indicate oversized frames */
1538 nic->rx_over_length_errors++;
1539 nic->net_stats.rx_dropped++;
1540 dev_kfree_skb_any(skb);
1541 } else {
1542 nic->net_stats.rx_packets++;
1543 nic->net_stats.rx_bytes += actual_size;
1544 nic->netdev->last_rx = jiffies;
1545 netif_receive_skb(skb);
1546 if(work_done)
1547 (*work_done)++;
1548 }
1549
1550 rx->skb = NULL;
1551
1552 return 0;
1553}
1554
1555static inline void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1556 unsigned int work_to_do)
1557{
1558 struct rx *rx;
Malli Chilakala1f533672005-04-28 19:17:20 -07001559 int restart_required = 0;
1560 struct rx *rx_to_start = NULL;
1561
1562 /* are we already rnr? then pay attention!!! this ensures that
1563 * the state machine progression never allows a start with a
1564 * partially cleaned list, avoiding a race between hardware
1565 * and rx_to_clean when in NAPI mode */
1566 if(RU_SUSPENDED == nic->ru_running)
1567 restart_required = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001568
1569 /* Indicate newly arrived packets */
1570 for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
Malli Chilakala1f533672005-04-28 19:17:20 -07001571 int err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1572 if(-EAGAIN == err) {
1573 /* hit quota so have more work to do, restart once
1574 * cleanup is complete */
1575 restart_required = 0;
1576 break;
1577 } else if(-ENODATA == err)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001578 break; /* No more to clean */
1579 }
1580
Malli Chilakala1f533672005-04-28 19:17:20 -07001581 /* save our starting point as the place we'll restart the receiver */
1582 if(restart_required)
1583 rx_to_start = nic->rx_to_clean;
1584
Linus Torvalds1da177e2005-04-16 15:20:36 -07001585 /* Alloc new skbs to refill list */
1586 for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1587 if(unlikely(e100_rx_alloc_skb(nic, rx)))
1588 break; /* Better luck next time (see watchdog) */
1589 }
1590
Malli Chilakala1f533672005-04-28 19:17:20 -07001591 if(restart_required) {
1592 // ack the rnr?
1593 writeb(stat_ack_rnr, &nic->csr->scb.stat_ack);
1594 e100_start_receiver(nic, rx_to_start);
1595 if(work_done)
1596 (*work_done)++;
1597 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001598}
1599
1600static void e100_rx_clean_list(struct nic *nic)
1601{
1602 struct rx *rx;
1603 unsigned int i, count = nic->params.rfds.count;
1604
Malli Chilakala1f533672005-04-28 19:17:20 -07001605 nic->ru_running = RU_UNINITIALIZED;
1606
Linus Torvalds1da177e2005-04-16 15:20:36 -07001607 if(nic->rxs) {
1608 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1609 if(rx->skb) {
1610 pci_unmap_single(nic->pdev, rx->dma_addr,
1611 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1612 dev_kfree_skb(rx->skb);
1613 }
1614 }
1615 kfree(nic->rxs);
1616 nic->rxs = NULL;
1617 }
1618
1619 nic->rx_to_use = nic->rx_to_clean = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001620}
1621
1622static int e100_rx_alloc_list(struct nic *nic)
1623{
1624 struct rx *rx;
1625 unsigned int i, count = nic->params.rfds.count;
1626
1627 nic->rx_to_use = nic->rx_to_clean = NULL;
Malli Chilakala1f533672005-04-28 19:17:20 -07001628 nic->ru_running = RU_UNINITIALIZED;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001629
1630 if(!(nic->rxs = kmalloc(sizeof(struct rx) * count, GFP_ATOMIC)))
1631 return -ENOMEM;
1632 memset(nic->rxs, 0, sizeof(struct rx) * count);
1633
1634 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1635 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
1636 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
1637 if(e100_rx_alloc_skb(nic, rx)) {
1638 e100_rx_clean_list(nic);
1639 return -ENOMEM;
1640 }
1641 }
1642
1643 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
Malli Chilakala1f533672005-04-28 19:17:20 -07001644 nic->ru_running = RU_SUSPENDED;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001645
1646 return 0;
1647}
1648
1649static irqreturn_t e100_intr(int irq, void *dev_id, struct pt_regs *regs)
1650{
1651 struct net_device *netdev = dev_id;
1652 struct nic *nic = netdev_priv(netdev);
1653 u8 stat_ack = readb(&nic->csr->scb.stat_ack);
1654
1655 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
1656
1657 if(stat_ack == stat_ack_not_ours || /* Not our interrupt */
1658 stat_ack == stat_ack_not_present) /* Hardware is ejected */
1659 return IRQ_NONE;
1660
1661 /* Ack interrupt(s) */
1662 writeb(stat_ack, &nic->csr->scb.stat_ack);
1663
1664 /* We hit Receive No Resource (RNR); restart RU after cleaning */
1665 if(stat_ack & stat_ack_rnr)
Malli Chilakala1f533672005-04-28 19:17:20 -07001666 nic->ru_running = RU_SUSPENDED;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001667
1668 e100_disable_irq(nic);
1669 netif_rx_schedule(netdev);
1670
1671 return IRQ_HANDLED;
1672}
1673
1674static int e100_poll(struct net_device *netdev, int *budget)
1675{
1676 struct nic *nic = netdev_priv(netdev);
1677 unsigned int work_to_do = min(netdev->quota, *budget);
1678 unsigned int work_done = 0;
1679 int tx_cleaned;
1680
1681 e100_rx_clean(nic, &work_done, work_to_do);
1682 tx_cleaned = e100_tx_clean(nic);
1683
1684 /* If no Rx and Tx cleanup work was done, exit polling mode. */
1685 if((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
1686 netif_rx_complete(netdev);
1687 e100_enable_irq(nic);
1688 return 0;
1689 }
1690
1691 *budget -= work_done;
1692 netdev->quota -= work_done;
1693
1694 return 1;
1695}
1696
1697#ifdef CONFIG_NET_POLL_CONTROLLER
1698static void e100_netpoll(struct net_device *netdev)
1699{
1700 struct nic *nic = netdev_priv(netdev);
1701 e100_disable_irq(nic);
1702 e100_intr(nic->pdev->irq, netdev, NULL);
1703 e100_tx_clean(nic);
1704 e100_enable_irq(nic);
1705}
1706#endif
1707
1708static struct net_device_stats *e100_get_stats(struct net_device *netdev)
1709{
1710 struct nic *nic = netdev_priv(netdev);
1711 return &nic->net_stats;
1712}
1713
1714static int e100_set_mac_address(struct net_device *netdev, void *p)
1715{
1716 struct nic *nic = netdev_priv(netdev);
1717 struct sockaddr *addr = p;
1718
1719 if (!is_valid_ether_addr(addr->sa_data))
1720 return -EADDRNOTAVAIL;
1721
1722 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1723 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
1724
1725 return 0;
1726}
1727
1728static int e100_change_mtu(struct net_device *netdev, int new_mtu)
1729{
1730 if(new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
1731 return -EINVAL;
1732 netdev->mtu = new_mtu;
1733 return 0;
1734}
1735
Malli Chilakala6bdacb12005-04-28 19:17:54 -07001736#ifdef CONFIG_PM
Linus Torvalds1da177e2005-04-16 15:20:36 -07001737static int e100_asf(struct nic *nic)
1738{
1739 /* ASF can be enabled from eeprom */
1740 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
1741 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
1742 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
1743 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
1744}
Malli Chilakala6bdacb12005-04-28 19:17:54 -07001745#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001746
1747static int e100_up(struct nic *nic)
1748{
1749 int err;
1750
1751 if((err = e100_rx_alloc_list(nic)))
1752 return err;
1753 if((err = e100_alloc_cbs(nic)))
1754 goto err_rx_clean_list;
1755 if((err = e100_hw_init(nic)))
1756 goto err_clean_cbs;
1757 e100_set_multicast_list(nic->netdev);
Malli Chilakala1f533672005-04-28 19:17:20 -07001758 e100_start_receiver(nic, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001759 mod_timer(&nic->watchdog, jiffies);
1760 if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ,
1761 nic->netdev->name, nic->netdev)))
1762 goto err_no_irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001763 netif_wake_queue(nic->netdev);
Malli Chilakala0236ebb2005-04-28 19:17:42 -07001764 netif_poll_enable(nic->netdev);
1765 /* enable ints _after_ enabling poll, preventing a race between
1766 * disable ints+schedule */
1767 e100_enable_irq(nic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001768 return 0;
1769
1770err_no_irq:
1771 del_timer_sync(&nic->watchdog);
1772err_clean_cbs:
1773 e100_clean_cbs(nic);
1774err_rx_clean_list:
1775 e100_rx_clean_list(nic);
1776 return err;
1777}
1778
1779static void e100_down(struct nic *nic)
1780{
Malli Chilakala0236ebb2005-04-28 19:17:42 -07001781 /* wait here for poll to complete */
1782 netif_poll_disable(nic->netdev);
1783 netif_stop_queue(nic->netdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001784 e100_hw_reset(nic);
1785 free_irq(nic->pdev->irq, nic->netdev);
1786 del_timer_sync(&nic->watchdog);
1787 netif_carrier_off(nic->netdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001788 e100_clean_cbs(nic);
1789 e100_rx_clean_list(nic);
1790}
1791
1792static void e100_tx_timeout(struct net_device *netdev)
1793{
1794 struct nic *nic = netdev_priv(netdev);
1795
Malli Chilakala2acdb1e2005-04-28 19:16:58 -07001796 /* Reset outside of interrupt context, to avoid request_irq
1797 * in interrupt context */
1798 schedule_work(&nic->tx_timeout_task);
1799}
1800
1801static void e100_tx_timeout_task(struct net_device *netdev)
1802{
1803 struct nic *nic = netdev_priv(netdev);
1804
Linus Torvalds1da177e2005-04-16 15:20:36 -07001805 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
1806 readb(&nic->csr->scb.status));
1807 e100_down(netdev_priv(netdev));
1808 e100_up(netdev_priv(netdev));
1809}
1810
1811static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
1812{
1813 int err;
1814 struct sk_buff *skb;
1815
1816 /* Use driver resources to perform internal MAC or PHY
1817 * loopback test. A single packet is prepared and transmitted
1818 * in loopback mode, and the test passes if the received
1819 * packet compares byte-for-byte to the transmitted packet. */
1820
1821 if((err = e100_rx_alloc_list(nic)))
1822 return err;
1823 if((err = e100_alloc_cbs(nic)))
1824 goto err_clean_rx;
1825
1826 /* ICH PHY loopback is broken so do MAC loopback instead */
1827 if(nic->flags & ich && loopback_mode == lb_phy)
1828 loopback_mode = lb_mac;
1829
1830 nic->loopback = loopback_mode;
1831 if((err = e100_hw_init(nic)))
1832 goto err_loopback_none;
1833
1834 if(loopback_mode == lb_phy)
1835 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
1836 BMCR_LOOPBACK);
1837
Malli Chilakala1f533672005-04-28 19:17:20 -07001838 e100_start_receiver(nic, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001839
1840 if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) {
1841 err = -ENOMEM;
1842 goto err_loopback_none;
1843 }
1844 skb_put(skb, ETH_DATA_LEN);
1845 memset(skb->data, 0xFF, ETH_DATA_LEN);
1846 e100_xmit_frame(skb, nic->netdev);
1847
1848 msleep(10);
1849
1850 if(memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
1851 skb->data, ETH_DATA_LEN))
1852 err = -EAGAIN;
1853
1854err_loopback_none:
1855 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
1856 nic->loopback = lb_none;
1857 e100_hw_init(nic);
1858 e100_clean_cbs(nic);
1859err_clean_rx:
1860 e100_rx_clean_list(nic);
1861 return err;
1862}
1863
1864#define MII_LED_CONTROL 0x1B
1865static void e100_blink_led(unsigned long data)
1866{
1867 struct nic *nic = (struct nic *)data;
1868 enum led_state {
1869 led_on = 0x01,
1870 led_off = 0x04,
1871 led_on_559 = 0x05,
1872 led_on_557 = 0x07,
1873 };
1874
1875 nic->leds = (nic->leds & led_on) ? led_off :
1876 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
1877 mdio_write(nic->netdev, nic->mii.phy_id, MII_LED_CONTROL, nic->leds);
1878 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
1879}
1880
1881static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1882{
1883 struct nic *nic = netdev_priv(netdev);
1884 return mii_ethtool_gset(&nic->mii, cmd);
1885}
1886
1887static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1888{
1889 struct nic *nic = netdev_priv(netdev);
1890 int err;
1891
1892 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
1893 err = mii_ethtool_sset(&nic->mii, cmd);
1894 e100_exec_cb(nic, NULL, e100_configure);
1895
1896 return err;
1897}
1898
1899static void e100_get_drvinfo(struct net_device *netdev,
1900 struct ethtool_drvinfo *info)
1901{
1902 struct nic *nic = netdev_priv(netdev);
1903 strcpy(info->driver, DRV_NAME);
1904 strcpy(info->version, DRV_VERSION);
1905 strcpy(info->fw_version, "N/A");
1906 strcpy(info->bus_info, pci_name(nic->pdev));
1907}
1908
1909static int e100_get_regs_len(struct net_device *netdev)
1910{
1911 struct nic *nic = netdev_priv(netdev);
1912#define E100_PHY_REGS 0x1C
1913#define E100_REGS_LEN 1 + E100_PHY_REGS + \
1914 sizeof(nic->mem->dump_buf) / sizeof(u32)
1915 return E100_REGS_LEN * sizeof(u32);
1916}
1917
1918static void e100_get_regs(struct net_device *netdev,
1919 struct ethtool_regs *regs, void *p)
1920{
1921 struct nic *nic = netdev_priv(netdev);
1922 u32 *buff = p;
1923 int i;
1924
1925 regs->version = (1 << 24) | nic->rev_id;
1926 buff[0] = readb(&nic->csr->scb.cmd_hi) << 24 |
1927 readb(&nic->csr->scb.cmd_lo) << 16 |
1928 readw(&nic->csr->scb.status);
1929 for(i = E100_PHY_REGS; i >= 0; i--)
1930 buff[1 + E100_PHY_REGS - i] =
1931 mdio_read(netdev, nic->mii.phy_id, i);
1932 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
1933 e100_exec_cb(nic, NULL, e100_dump);
1934 msleep(10);
1935 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
1936 sizeof(nic->mem->dump_buf));
1937}
1938
1939static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1940{
1941 struct nic *nic = netdev_priv(netdev);
1942 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
1943 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
1944}
1945
1946static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1947{
1948 struct nic *nic = netdev_priv(netdev);
1949
1950 if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
1951 return -EOPNOTSUPP;
1952
1953 if(wol->wolopts)
1954 nic->flags |= wol_magic;
1955 else
1956 nic->flags &= ~wol_magic;
1957
Linus Torvalds1da177e2005-04-16 15:20:36 -07001958 e100_exec_cb(nic, NULL, e100_configure);
1959
1960 return 0;
1961}
1962
1963static u32 e100_get_msglevel(struct net_device *netdev)
1964{
1965 struct nic *nic = netdev_priv(netdev);
1966 return nic->msg_enable;
1967}
1968
1969static void e100_set_msglevel(struct net_device *netdev, u32 value)
1970{
1971 struct nic *nic = netdev_priv(netdev);
1972 nic->msg_enable = value;
1973}
1974
1975static int e100_nway_reset(struct net_device *netdev)
1976{
1977 struct nic *nic = netdev_priv(netdev);
1978 return mii_nway_restart(&nic->mii);
1979}
1980
1981static u32 e100_get_link(struct net_device *netdev)
1982{
1983 struct nic *nic = netdev_priv(netdev);
1984 return mii_link_ok(&nic->mii);
1985}
1986
1987static int e100_get_eeprom_len(struct net_device *netdev)
1988{
1989 struct nic *nic = netdev_priv(netdev);
1990 return nic->eeprom_wc << 1;
1991}
1992
1993#define E100_EEPROM_MAGIC 0x1234
1994static int e100_get_eeprom(struct net_device *netdev,
1995 struct ethtool_eeprom *eeprom, u8 *bytes)
1996{
1997 struct nic *nic = netdev_priv(netdev);
1998
1999 eeprom->magic = E100_EEPROM_MAGIC;
2000 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2001
2002 return 0;
2003}
2004
2005static int e100_set_eeprom(struct net_device *netdev,
2006 struct ethtool_eeprom *eeprom, u8 *bytes)
2007{
2008 struct nic *nic = netdev_priv(netdev);
2009
2010 if(eeprom->magic != E100_EEPROM_MAGIC)
2011 return -EINVAL;
2012
2013 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2014
2015 return e100_eeprom_save(nic, eeprom->offset >> 1,
2016 (eeprom->len >> 1) + 1);
2017}
2018
2019static void e100_get_ringparam(struct net_device *netdev,
2020 struct ethtool_ringparam *ring)
2021{
2022 struct nic *nic = netdev_priv(netdev);
2023 struct param_range *rfds = &nic->params.rfds;
2024 struct param_range *cbs = &nic->params.cbs;
2025
2026 ring->rx_max_pending = rfds->max;
2027 ring->tx_max_pending = cbs->max;
2028 ring->rx_mini_max_pending = 0;
2029 ring->rx_jumbo_max_pending = 0;
2030 ring->rx_pending = rfds->count;
2031 ring->tx_pending = cbs->count;
2032 ring->rx_mini_pending = 0;
2033 ring->rx_jumbo_pending = 0;
2034}
2035
2036static int e100_set_ringparam(struct net_device *netdev,
2037 struct ethtool_ringparam *ring)
2038{
2039 struct nic *nic = netdev_priv(netdev);
2040 struct param_range *rfds = &nic->params.rfds;
2041 struct param_range *cbs = &nic->params.cbs;
2042
2043 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2044 return -EINVAL;
2045
2046 if(netif_running(netdev))
2047 e100_down(nic);
2048 rfds->count = max(ring->rx_pending, rfds->min);
2049 rfds->count = min(rfds->count, rfds->max);
2050 cbs->count = max(ring->tx_pending, cbs->min);
2051 cbs->count = min(cbs->count, cbs->max);
2052 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
2053 rfds->count, cbs->count);
2054 if(netif_running(netdev))
2055 e100_up(nic);
2056
2057 return 0;
2058}
2059
2060static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2061 "Link test (on/offline)",
2062 "Eeprom test (on/offline)",
2063 "Self test (offline)",
2064 "Mac loopback (offline)",
2065 "Phy loopback (offline)",
2066};
2067#define E100_TEST_LEN sizeof(e100_gstrings_test) / ETH_GSTRING_LEN
2068
2069static int e100_diag_test_count(struct net_device *netdev)
2070{
2071 return E100_TEST_LEN;
2072}
2073
2074static void e100_diag_test(struct net_device *netdev,
2075 struct ethtool_test *test, u64 *data)
2076{
2077 struct ethtool_cmd cmd;
2078 struct nic *nic = netdev_priv(netdev);
2079 int i, err;
2080
2081 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2082 data[0] = !mii_link_ok(&nic->mii);
2083 data[1] = e100_eeprom_load(nic);
2084 if(test->flags & ETH_TEST_FL_OFFLINE) {
2085
2086 /* save speed, duplex & autoneg settings */
2087 err = mii_ethtool_gset(&nic->mii, &cmd);
2088
2089 if(netif_running(netdev))
2090 e100_down(nic);
2091 data[2] = e100_self_test(nic);
2092 data[3] = e100_loopback_test(nic, lb_mac);
2093 data[4] = e100_loopback_test(nic, lb_phy);
2094
2095 /* restore speed, duplex & autoneg settings */
2096 err = mii_ethtool_sset(&nic->mii, &cmd);
2097
2098 if(netif_running(netdev))
2099 e100_up(nic);
2100 }
2101 for(i = 0; i < E100_TEST_LEN; i++)
2102 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2103}
2104
2105static int e100_phys_id(struct net_device *netdev, u32 data)
2106{
2107 struct nic *nic = netdev_priv(netdev);
2108
2109 if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2110 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2111 mod_timer(&nic->blink_timer, jiffies);
2112 msleep_interruptible(data * 1000);
2113 del_timer_sync(&nic->blink_timer);
2114 mdio_write(netdev, nic->mii.phy_id, MII_LED_CONTROL, 0);
2115
2116 return 0;
2117}
2118
2119static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2120 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2121 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2122 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2123 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2124 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2125 "tx_heartbeat_errors", "tx_window_errors",
2126 /* device-specific stats */
2127 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2128 "tx_flow_control_pause", "rx_flow_control_pause",
2129 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2130};
2131#define E100_NET_STATS_LEN 21
2132#define E100_STATS_LEN sizeof(e100_gstrings_stats) / ETH_GSTRING_LEN
2133
2134static int e100_get_stats_count(struct net_device *netdev)
2135{
2136 return E100_STATS_LEN;
2137}
2138
2139static void e100_get_ethtool_stats(struct net_device *netdev,
2140 struct ethtool_stats *stats, u64 *data)
2141{
2142 struct nic *nic = netdev_priv(netdev);
2143 int i;
2144
2145 for(i = 0; i < E100_NET_STATS_LEN; i++)
2146 data[i] = ((unsigned long *)&nic->net_stats)[i];
2147
2148 data[i++] = nic->tx_deferred;
2149 data[i++] = nic->tx_single_collisions;
2150 data[i++] = nic->tx_multiple_collisions;
2151 data[i++] = nic->tx_fc_pause;
2152 data[i++] = nic->rx_fc_pause;
2153 data[i++] = nic->rx_fc_unsupported;
2154 data[i++] = nic->tx_tco_frames;
2155 data[i++] = nic->rx_tco_frames;
2156}
2157
2158static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2159{
2160 switch(stringset) {
2161 case ETH_SS_TEST:
2162 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2163 break;
2164 case ETH_SS_STATS:
2165 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2166 break;
2167 }
2168}
2169
2170static struct ethtool_ops e100_ethtool_ops = {
2171 .get_settings = e100_get_settings,
2172 .set_settings = e100_set_settings,
2173 .get_drvinfo = e100_get_drvinfo,
2174 .get_regs_len = e100_get_regs_len,
2175 .get_regs = e100_get_regs,
2176 .get_wol = e100_get_wol,
2177 .set_wol = e100_set_wol,
2178 .get_msglevel = e100_get_msglevel,
2179 .set_msglevel = e100_set_msglevel,
2180 .nway_reset = e100_nway_reset,
2181 .get_link = e100_get_link,
2182 .get_eeprom_len = e100_get_eeprom_len,
2183 .get_eeprom = e100_get_eeprom,
2184 .set_eeprom = e100_set_eeprom,
2185 .get_ringparam = e100_get_ringparam,
2186 .set_ringparam = e100_set_ringparam,
2187 .self_test_count = e100_diag_test_count,
2188 .self_test = e100_diag_test,
2189 .get_strings = e100_get_strings,
2190 .phys_id = e100_phys_id,
2191 .get_stats_count = e100_get_stats_count,
2192 .get_ethtool_stats = e100_get_ethtool_stats,
2193};
2194
2195static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2196{
2197 struct nic *nic = netdev_priv(netdev);
2198
2199 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2200}
2201
2202static int e100_alloc(struct nic *nic)
2203{
2204 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2205 &nic->dma_addr);
2206 return nic->mem ? 0 : -ENOMEM;
2207}
2208
2209static void e100_free(struct nic *nic)
2210{
2211 if(nic->mem) {
2212 pci_free_consistent(nic->pdev, sizeof(struct mem),
2213 nic->mem, nic->dma_addr);
2214 nic->mem = NULL;
2215 }
2216}
2217
2218static int e100_open(struct net_device *netdev)
2219{
2220 struct nic *nic = netdev_priv(netdev);
2221 int err = 0;
2222
2223 netif_carrier_off(netdev);
2224 if((err = e100_up(nic)))
2225 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2226 return err;
2227}
2228
2229static int e100_close(struct net_device *netdev)
2230{
2231 e100_down(netdev_priv(netdev));
2232 return 0;
2233}
2234
2235static int __devinit e100_probe(struct pci_dev *pdev,
2236 const struct pci_device_id *ent)
2237{
2238 struct net_device *netdev;
2239 struct nic *nic;
2240 int err;
2241
2242 if(!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2243 if(((1 << debug) - 1) & NETIF_MSG_PROBE)
2244 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2245 return -ENOMEM;
2246 }
2247
2248 netdev->open = e100_open;
2249 netdev->stop = e100_close;
2250 netdev->hard_start_xmit = e100_xmit_frame;
2251 netdev->get_stats = e100_get_stats;
2252 netdev->set_multicast_list = e100_set_multicast_list;
2253 netdev->set_mac_address = e100_set_mac_address;
2254 netdev->change_mtu = e100_change_mtu;
2255 netdev->do_ioctl = e100_do_ioctl;
2256 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2257 netdev->tx_timeout = e100_tx_timeout;
2258 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2259 netdev->poll = e100_poll;
2260 netdev->weight = E100_NAPI_WEIGHT;
2261#ifdef CONFIG_NET_POLL_CONTROLLER
2262 netdev->poll_controller = e100_netpoll;
2263#endif
2264 strcpy(netdev->name, pci_name(pdev));
2265
2266 nic = netdev_priv(netdev);
2267 nic->netdev = netdev;
2268 nic->pdev = pdev;
2269 nic->msg_enable = (1 << debug) - 1;
2270 pci_set_drvdata(pdev, netdev);
2271
2272 if((err = pci_enable_device(pdev))) {
2273 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2274 goto err_out_free_dev;
2275 }
2276
2277 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2278 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2279 "base address, aborting.\n");
2280 err = -ENODEV;
2281 goto err_out_disable_pdev;
2282 }
2283
2284 if((err = pci_request_regions(pdev, DRV_NAME))) {
2285 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2286 goto err_out_disable_pdev;
2287 }
2288
2289 if((err = pci_set_dma_mask(pdev, 0xFFFFFFFFULL))) {
2290 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2291 goto err_out_free_res;
2292 }
2293
2294 SET_MODULE_OWNER(netdev);
2295 SET_NETDEV_DEV(netdev, &pdev->dev);
2296
2297 nic->csr = ioremap(pci_resource_start(pdev, 0), sizeof(struct csr));
2298 if(!nic->csr) {
2299 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2300 err = -ENOMEM;
2301 goto err_out_free_res;
2302 }
2303
2304 if(ent->driver_data)
2305 nic->flags |= ich;
2306 else
2307 nic->flags &= ~ich;
2308
2309 e100_get_defaults(nic);
2310
Malli Chilakala1f533672005-04-28 19:17:20 -07002311 /* locks must be initialized before calling hw_reset */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002312 spin_lock_init(&nic->cb_lock);
2313 spin_lock_init(&nic->cmd_lock);
2314
2315 /* Reset the device before pci_set_master() in case device is in some
2316 * funky state and has an interrupt pending - hint: we don't have the
2317 * interrupt handler registered yet. */
2318 e100_hw_reset(nic);
2319
2320 pci_set_master(pdev);
2321
2322 init_timer(&nic->watchdog);
2323 nic->watchdog.function = e100_watchdog;
2324 nic->watchdog.data = (unsigned long)nic;
2325 init_timer(&nic->blink_timer);
2326 nic->blink_timer.function = e100_blink_led;
2327 nic->blink_timer.data = (unsigned long)nic;
2328
Malli Chilakala2acdb1e2005-04-28 19:16:58 -07002329 INIT_WORK(&nic->tx_timeout_task,
2330 (void (*)(void *))e100_tx_timeout_task, netdev);
2331
Linus Torvalds1da177e2005-04-16 15:20:36 -07002332 if((err = e100_alloc(nic))) {
2333 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2334 goto err_out_iounmap;
2335 }
2336
2337 e100_phy_init(nic);
2338
2339 if((err = e100_eeprom_load(nic)))
2340 goto err_out_free;
2341
2342 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2343 if(!is_valid_ether_addr(netdev->dev_addr)) {
2344 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2345 "EEPROM, aborting.\n");
2346 err = -EAGAIN;
2347 goto err_out_free;
2348 }
2349
2350 /* Wol magic packet can be enabled from eeprom */
2351 if((nic->mac >= mac_82558_D101_A4) &&
2352 (nic->eeprom[eeprom_id] & eeprom_id_wol))
2353 nic->flags |= wol_magic;
2354
Malli Chilakala6bdacb12005-04-28 19:17:54 -07002355 /* ack any pending wake events, disable PME */
2356 pci_enable_wake(pdev, 0, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002357
2358 strcpy(netdev->name, "eth%d");
2359 if((err = register_netdev(netdev))) {
2360 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2361 goto err_out_free;
2362 }
2363
2364 DPRINTK(PROBE, INFO, "addr 0x%lx, irq %d, "
2365 "MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
2366 pci_resource_start(pdev, 0), pdev->irq,
2367 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
2368 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
2369
2370 return 0;
2371
2372err_out_free:
2373 e100_free(nic);
2374err_out_iounmap:
2375 iounmap(nic->csr);
2376err_out_free_res:
2377 pci_release_regions(pdev);
2378err_out_disable_pdev:
2379 pci_disable_device(pdev);
2380err_out_free_dev:
2381 pci_set_drvdata(pdev, NULL);
2382 free_netdev(netdev);
2383 return err;
2384}
2385
2386static void __devexit e100_remove(struct pci_dev *pdev)
2387{
2388 struct net_device *netdev = pci_get_drvdata(pdev);
2389
2390 if(netdev) {
2391 struct nic *nic = netdev_priv(netdev);
2392 unregister_netdev(netdev);
2393 e100_free(nic);
2394 iounmap(nic->csr);
2395 free_netdev(netdev);
2396 pci_release_regions(pdev);
2397 pci_disable_device(pdev);
2398 pci_set_drvdata(pdev, NULL);
2399 }
2400}
2401
2402#ifdef CONFIG_PM
2403static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2404{
2405 struct net_device *netdev = pci_get_drvdata(pdev);
2406 struct nic *nic = netdev_priv(netdev);
2407
2408 if(netif_running(netdev))
2409 e100_down(nic);
2410 e100_hw_reset(nic);
2411 netif_device_detach(netdev);
2412
2413 pci_save_state(pdev);
2414 pci_enable_wake(pdev, pci_choose_state(pdev, state), nic->flags & (wol_magic | e100_asf(nic)));
2415 pci_disable_device(pdev);
2416 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2417
2418 return 0;
2419}
2420
2421static int e100_resume(struct pci_dev *pdev)
2422{
2423 struct net_device *netdev = pci_get_drvdata(pdev);
2424 struct nic *nic = netdev_priv(netdev);
2425
2426 pci_set_power_state(pdev, PCI_D0);
2427 pci_restore_state(pdev);
Malli Chilakala6bdacb12005-04-28 19:17:54 -07002428 /* ack any pending wake events, disable PME */
2429 pci_enable_wake(pdev, 0, 0);
Malli Chilakala1f533672005-04-28 19:17:20 -07002430 if(e100_hw_init(nic))
2431 DPRINTK(HW, ERR, "e100_hw_init failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002432
2433 netif_device_attach(netdev);
2434 if(netif_running(netdev))
2435 e100_up(nic);
2436
2437 return 0;
2438}
2439#endif
2440
Malli Chilakala6bdacb12005-04-28 19:17:54 -07002441
2442static void e100_shutdown(struct device *dev)
2443{
2444 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2445 struct net_device *netdev = pci_get_drvdata(pdev);
2446 struct nic *nic = netdev_priv(netdev);
2447
2448#ifdef CONFIG_PM
2449 pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
2450#else
2451 pci_enable_wake(pdev, 0, nic->flags & (wol_magic));
2452#endif
2453}
2454
2455
Linus Torvalds1da177e2005-04-16 15:20:36 -07002456static struct pci_driver e100_driver = {
2457 .name = DRV_NAME,
2458 .id_table = e100_id_table,
2459 .probe = e100_probe,
2460 .remove = __devexit_p(e100_remove),
2461#ifdef CONFIG_PM
2462 .suspend = e100_suspend,
2463 .resume = e100_resume,
2464#endif
Malli Chilakala6bdacb12005-04-28 19:17:54 -07002465
2466 .driver = {
2467 .shutdown = e100_shutdown,
2468 }
2469
Linus Torvalds1da177e2005-04-16 15:20:36 -07002470};
2471
2472static int __init e100_init_module(void)
2473{
2474 if(((1 << debug) - 1) & NETIF_MSG_DRV) {
2475 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
2476 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
2477 }
2478 return pci_module_init(&e100_driver);
2479}
2480
2481static void __exit e100_cleanup_module(void)
2482{
2483 pci_unregister_driver(&e100_driver);
2484}
2485
2486module_init(e100_init_module);
2487module_exit(e100_cleanup_module);