Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 1 | /* |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 2 | * Copyright (C) 2010 Google, Inc. |
| 3 | * |
| 4 | * Author: |
| 5 | * Colin Cross <ccross@google.com> |
| 6 | * |
| 7 | * This software is licensed under the terms of the GNU General Public |
| 8 | * License version 2, as published by the Free Software Foundation, and |
| 9 | * may be copied, distributed, and modified under those terms. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #include <linux/init.h> |
Colin Cross | 62248ae | 2011-02-21 17:04:37 -0800 | [diff] [blame] | 19 | #include <linux/err.h> |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 20 | #include <linux/time.h> |
| 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/irq.h> |
| 23 | #include <linux/clockchips.h> |
| 24 | #include <linux/clocksource.h> |
| 25 | #include <linux/clk.h> |
| 26 | #include <linux/io.h> |
Stephen Warren | 3a04931 | 2012-10-23 11:40:25 -0600 | [diff] [blame] | 27 | #include <linux/of_address.h> |
Stephen Warren | 5641548 | 2012-09-19 13:13:33 -0600 | [diff] [blame] | 28 | #include <linux/of_irq.h> |
Stephen Boyd | 38ff87f | 2013-06-01 23:39:40 -0700 | [diff] [blame] | 29 | #include <linux/sched_clock.h> |
Peter De Schrijver | 0ff36b4 | 2014-06-12 18:58:29 +0300 | [diff] [blame] | 30 | #include <linux/delay.h> |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 31 | |
| 32 | #include <asm/mach/time.h> |
Marc Zyngier | 1fcf3a6 | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 33 | #include <asm/smp_twd.h> |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 34 | |
Colin Cross | 0936178 | 2010-11-28 16:26:19 -0800 | [diff] [blame] | 35 | #define RTC_SECONDS 0x08 |
| 36 | #define RTC_SHADOW_SECONDS 0x0c |
| 37 | #define RTC_MILLISECONDS 0x10 |
| 38 | |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 39 | #define TIMERUS_CNTR_1US 0x10 |
| 40 | #define TIMERUS_USEC_CFG 0x14 |
| 41 | #define TIMERUS_CNTR_FREEZE 0x4c |
| 42 | |
| 43 | #define TIMER1_BASE 0x0 |
| 44 | #define TIMER2_BASE 0x8 |
| 45 | #define TIMER3_BASE 0x50 |
| 46 | #define TIMER4_BASE 0x58 |
| 47 | |
| 48 | #define TIMER_PTV 0x0 |
| 49 | #define TIMER_PCR 0x4 |
| 50 | |
Stephen Warren | 3a04931 | 2012-10-23 11:40:25 -0600 | [diff] [blame] | 51 | static void __iomem *timer_reg_base; |
| 52 | static void __iomem *rtc_base; |
Colin Cross | 0936178 | 2010-11-28 16:26:19 -0800 | [diff] [blame] | 53 | |
Xunlei Pang | a0c2998 | 2015-04-01 20:34:25 -0700 | [diff] [blame] | 54 | static struct timespec64 persistent_ts; |
Colin Cross | 0936178 | 2010-11-28 16:26:19 -0800 | [diff] [blame] | 55 | static u64 persistent_ms, last_persistent_ms; |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 56 | |
Peter De Schrijver | 0ff36b4 | 2014-06-12 18:58:29 +0300 | [diff] [blame] | 57 | static struct delay_timer tegra_delay_timer; |
| 58 | |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 59 | #define timer_writel(value, reg) \ |
Dmitry Osipenko | 59196bc | 2015-03-30 22:17:11 +0200 | [diff] [blame] | 60 | writel_relaxed(value, timer_reg_base + (reg)) |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 61 | #define timer_readl(reg) \ |
Dmitry Osipenko | 59196bc | 2015-03-30 22:17:11 +0200 | [diff] [blame] | 62 | readl_relaxed(timer_reg_base + (reg)) |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 63 | |
| 64 | static int tegra_timer_set_next_event(unsigned long cycles, |
| 65 | struct clock_event_device *evt) |
| 66 | { |
| 67 | u32 reg; |
| 68 | |
| 69 | reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0); |
| 70 | timer_writel(reg, TIMER3_BASE + TIMER_PTV); |
| 71 | |
| 72 | return 0; |
| 73 | } |
| 74 | |
| 75 | static void tegra_timer_set_mode(enum clock_event_mode mode, |
| 76 | struct clock_event_device *evt) |
| 77 | { |
| 78 | u32 reg; |
| 79 | |
| 80 | timer_writel(0, TIMER3_BASE + TIMER_PTV); |
| 81 | |
| 82 | switch (mode) { |
| 83 | case CLOCK_EVT_MODE_PERIODIC: |
| 84 | reg = 0xC0000000 | ((1000000/HZ)-1); |
| 85 | timer_writel(reg, TIMER3_BASE + TIMER_PTV); |
| 86 | break; |
| 87 | case CLOCK_EVT_MODE_ONESHOT: |
| 88 | break; |
| 89 | case CLOCK_EVT_MODE_UNUSED: |
| 90 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 91 | case CLOCK_EVT_MODE_RESUME: |
| 92 | break; |
| 93 | } |
| 94 | } |
| 95 | |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 96 | static struct clock_event_device tegra_clockevent = { |
| 97 | .name = "timer0", |
| 98 | .rating = 300, |
| 99 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, |
| 100 | .set_next_event = tegra_timer_set_next_event, |
| 101 | .set_mode = tegra_timer_set_mode, |
| 102 | }; |
| 103 | |
Stephen Boyd | 3570299 | 2013-07-18 16:21:26 -0700 | [diff] [blame] | 104 | static u64 notrace tegra_read_sched_clock(void) |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 105 | { |
Marc Zyngier | 2f0778af | 2011-12-15 12:19:23 +0100 | [diff] [blame] | 106 | return timer_readl(TIMERUS_CNTR_1US); |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 107 | } |
| 108 | |
Colin Cross | 0936178 | 2010-11-28 16:26:19 -0800 | [diff] [blame] | 109 | /* |
| 110 | * tegra_rtc_read - Reads the Tegra RTC registers |
| 111 | * Care must be taken that this funciton is not called while the |
| 112 | * tegra_rtc driver could be executing to avoid race conditions |
| 113 | * on the RTC shadow register |
| 114 | */ |
Olof Johansson | b28fba2 | 2011-09-08 17:50:03 -0700 | [diff] [blame] | 115 | static u64 tegra_rtc_read_ms(void) |
Colin Cross | 0936178 | 2010-11-28 16:26:19 -0800 | [diff] [blame] | 116 | { |
| 117 | u32 ms = readl(rtc_base + RTC_MILLISECONDS); |
| 118 | u32 s = readl(rtc_base + RTC_SHADOW_SECONDS); |
| 119 | return (u64)s * MSEC_PER_SEC + ms; |
| 120 | } |
| 121 | |
| 122 | /* |
Xunlei Pang | a0c2998 | 2015-04-01 20:34:25 -0700 | [diff] [blame] | 123 | * tegra_read_persistent_clock64 - Return time from a persistent clock. |
Colin Cross | 0936178 | 2010-11-28 16:26:19 -0800 | [diff] [blame] | 124 | * |
| 125 | * Reads the time from a source which isn't disabled during PM, the |
| 126 | * 32k sync timer. Convert the cycles elapsed since last read into |
Xunlei Pang | a0c2998 | 2015-04-01 20:34:25 -0700 | [diff] [blame] | 127 | * nsecs and adds to a monotonically increasing timespec64. |
Colin Cross | 0936178 | 2010-11-28 16:26:19 -0800 | [diff] [blame] | 128 | * Care must be taken that this funciton is not called while the |
| 129 | * tegra_rtc driver could be executing to avoid race conditions |
| 130 | * on the RTC shadow register |
| 131 | */ |
Xunlei Pang | a0c2998 | 2015-04-01 20:34:25 -0700 | [diff] [blame] | 132 | static void tegra_read_persistent_clock64(struct timespec64 *ts) |
Colin Cross | 0936178 | 2010-11-28 16:26:19 -0800 | [diff] [blame] | 133 | { |
| 134 | u64 delta; |
Colin Cross | 0936178 | 2010-11-28 16:26:19 -0800 | [diff] [blame] | 135 | |
| 136 | last_persistent_ms = persistent_ms; |
| 137 | persistent_ms = tegra_rtc_read_ms(); |
| 138 | delta = persistent_ms - last_persistent_ms; |
| 139 | |
Xunlei Pang | a0c2998 | 2015-04-01 20:34:25 -0700 | [diff] [blame] | 140 | timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC); |
| 141 | *ts = persistent_ts; |
| 142 | } |
| 143 | |
Peter De Schrijver | 0ff36b4 | 2014-06-12 18:58:29 +0300 | [diff] [blame] | 144 | static unsigned long tegra_delay_timer_read_counter_long(void) |
| 145 | { |
| 146 | return readl(timer_reg_base + TIMERUS_CNTR_1US); |
| 147 | } |
| 148 | |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 149 | static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) |
| 150 | { |
| 151 | struct clock_event_device *evt = (struct clock_event_device *)dev_id; |
| 152 | timer_writel(1<<30, TIMER3_BASE + TIMER_PCR); |
| 153 | evt->event_handler(evt); |
| 154 | return IRQ_HANDLED; |
| 155 | } |
| 156 | |
| 157 | static struct irqaction tegra_timer_irq = { |
| 158 | .name = "timer0", |
Michael Opdenacker | 39304fa | 2013-12-09 10:35:45 +0100 | [diff] [blame] | 159 | .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH, |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 160 | .handler = tegra_timer_interrupt, |
| 161 | .dev_id = &tegra_clockevent, |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 162 | }; |
| 163 | |
Rob Herring | effbfdd | 2013-02-06 14:40:22 -0600 | [diff] [blame] | 164 | static void __init tegra20_init_timer(struct device_node *np) |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 165 | { |
Colin Cross | 62248ae | 2011-02-21 17:04:37 -0800 | [diff] [blame] | 166 | struct clk *clk; |
Peter De Schrijver | 8e4fab2 | 2011-12-14 17:03:16 +0200 | [diff] [blame] | 167 | unsigned long rate; |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 168 | int ret; |
| 169 | |
Stephen Warren | 3a04931 | 2012-10-23 11:40:25 -0600 | [diff] [blame] | 170 | timer_reg_base = of_iomap(np, 0); |
| 171 | if (!timer_reg_base) { |
Hiroshi Doyu | 3734086 | 2012-12-17 13:35:23 +0200 | [diff] [blame] | 172 | pr_err("Can't map timer registers\n"); |
Stephen Warren | 3a04931 | 2012-10-23 11:40:25 -0600 | [diff] [blame] | 173 | BUG(); |
| 174 | } |
| 175 | |
Stephen Warren | 5641548 | 2012-09-19 13:13:33 -0600 | [diff] [blame] | 176 | tegra_timer_irq.irq = irq_of_parse_and_map(np, 2); |
| 177 | if (tegra_timer_irq.irq <= 0) { |
| 178 | pr_err("Failed to map timer IRQ\n"); |
| 179 | BUG(); |
| 180 | } |
| 181 | |
Peter De Schrijver | 6f88fb8 | 2013-02-04 15:40:30 +0200 | [diff] [blame] | 182 | clk = of_clk_get(np, 0); |
Peter De Schrijver | 8e4fab2 | 2011-12-14 17:03:16 +0200 | [diff] [blame] | 183 | if (IS_ERR(clk)) { |
Stephen Warren | 58664f9 | 2012-10-23 12:21:39 -0600 | [diff] [blame] | 184 | pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); |
Peter De Schrijver | 8e4fab2 | 2011-12-14 17:03:16 +0200 | [diff] [blame] | 185 | rate = 12000000; |
| 186 | } else { |
Prashant Gaikwad | 6a5278d | 2012-06-05 09:59:35 +0530 | [diff] [blame] | 187 | clk_prepare_enable(clk); |
Peter De Schrijver | 8e4fab2 | 2011-12-14 17:03:16 +0200 | [diff] [blame] | 188 | rate = clk_get_rate(clk); |
| 189 | } |
Colin Cross | 62248ae | 2011-02-21 17:04:37 -0800 | [diff] [blame] | 190 | |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 191 | switch (rate) { |
| 192 | case 12000000: |
| 193 | timer_writel(0x000b, TIMERUS_USEC_CFG); |
| 194 | break; |
| 195 | case 13000000: |
| 196 | timer_writel(0x000c, TIMERUS_USEC_CFG); |
| 197 | break; |
| 198 | case 19200000: |
| 199 | timer_writel(0x045f, TIMERUS_USEC_CFG); |
| 200 | break; |
| 201 | case 26000000: |
| 202 | timer_writel(0x0019, TIMERUS_USEC_CFG); |
| 203 | break; |
| 204 | default: |
| 205 | WARN(1, "Unknown clock rate"); |
| 206 | } |
| 207 | |
Stephen Boyd | 3570299 | 2013-07-18 16:21:26 -0700 | [diff] [blame] | 208 | sched_clock_register(tegra_read_sched_clock, 32, 1000000); |
Russell King | e3f4c0a | 2010-12-15 21:49:42 +0000 | [diff] [blame] | 209 | |
Russell King | 234b6ced | 2011-05-08 14:09:47 +0100 | [diff] [blame] | 210 | if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, |
| 211 | "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { |
Stephen Warren | 58664f9 | 2012-10-23 12:21:39 -0600 | [diff] [blame] | 212 | pr_err("Failed to register clocksource\n"); |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 213 | BUG(); |
| 214 | } |
| 215 | |
Peter De Schrijver | 0ff36b4 | 2014-06-12 18:58:29 +0300 | [diff] [blame] | 216 | tegra_delay_timer.read_current_timer = |
| 217 | tegra_delay_timer_read_counter_long; |
| 218 | tegra_delay_timer.freq = 1000000; |
| 219 | register_current_timer_delay(&tegra_delay_timer); |
| 220 | |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 221 | ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); |
| 222 | if (ret) { |
Stephen Warren | 58664f9 | 2012-10-23 12:21:39 -0600 | [diff] [blame] | 223 | pr_err("Failed to register timer IRQ: %d\n", ret); |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 224 | BUG(); |
| 225 | } |
| 226 | |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 227 | tegra_clockevent.cpumask = cpu_all_mask; |
| 228 | tegra_clockevent.irq = tegra_timer_irq.irq; |
Shawn Guo | 838a2ae | 2013-01-12 11:50:05 +0000 | [diff] [blame] | 229 | clockevents_config_and_register(&tegra_clockevent, 1000000, |
| 230 | 0x1, 0x1fffffff); |
Rob Herring | 1d16cfb | 2013-02-07 11:36:23 -0600 | [diff] [blame] | 231 | } |
| 232 | CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); |
| 233 | |
| 234 | static void __init tegra20_init_rtc(struct device_node *np) |
| 235 | { |
| 236 | struct clk *clk; |
| 237 | |
| 238 | rtc_base = of_iomap(np, 0); |
| 239 | if (!rtc_base) { |
| 240 | pr_err("Can't map RTC registers"); |
| 241 | BUG(); |
| 242 | } |
| 243 | |
| 244 | /* |
| 245 | * rtc registers are used by read_persistent_clock, keep the rtc clock |
| 246 | * enabled |
| 247 | */ |
Arnd Bergmann | 8024206 | 2013-04-09 15:27:52 +0200 | [diff] [blame] | 248 | clk = of_clk_get(np, 0); |
Rob Herring | 1d16cfb | 2013-02-07 11:36:23 -0600 | [diff] [blame] | 249 | if (IS_ERR(clk)) |
| 250 | pr_warn("Unable to get rtc-tegra clock\n"); |
| 251 | else |
| 252 | clk_prepare_enable(clk); |
| 253 | |
Xunlei Pang | cb85071 | 2015-04-01 20:34:26 -0700 | [diff] [blame] | 254 | register_persistent_clock(NULL, tegra_read_persistent_clock64); |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 255 | } |
Rob Herring | 1d16cfb | 2013-02-07 11:36:23 -0600 | [diff] [blame] | 256 | CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); |
Colin Cross | 2d5cd9a | 2010-01-28 16:41:42 -0800 | [diff] [blame] | 257 | |
Colin Cross | 0936178 | 2010-11-28 16:26:19 -0800 | [diff] [blame] | 258 | #ifdef CONFIG_PM |
| 259 | static u32 usec_config; |
| 260 | |
| 261 | void tegra_timer_suspend(void) |
| 262 | { |
| 263 | usec_config = timer_readl(TIMERUS_USEC_CFG); |
| 264 | } |
| 265 | |
| 266 | void tegra_timer_resume(void) |
| 267 | { |
| 268 | timer_writel(usec_config, TIMERUS_USEC_CFG); |
| 269 | } |
| 270 | #endif |