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gerrit-public.fairphone.software / kernel / msm-4.19 / 055114a38804947554065194d50ded4bc7d7c4c6 / . / drivers / net / wireless / b43 / phy_lp.c
blob: cb6c18d2cdbd56d74903721be201f814b81d282e [file] [log] [blame]
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11g LP-PHY driver
5
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]6 Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
25#include "b43.h"
Michael Bueschce1a9ee2009-02-04 19:55:22 +0100[diff] [blame]26#include "main.h"
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]27#include "phy_lp.h"
28#include "phy_common.h"
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]29#include "tables_lpphy.h"
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]30
31
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]32static inline u16 channel2freq_lp(u8 channel)
33{
34 if (channel < 14)
35 return (2407 + 5 * channel);
36 else if (channel == 14)
37 return 2484;
38 else if (channel < 184)
39 return (5000 + 5 * channel);
40 else
41 return (4000 + 5 * channel);
42}
43
44static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
45{
46 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
47 return 1;
48 return 36;
49}
50
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]51static int b43_lpphy_op_allocate(struct b43_wldev *dev)
52{
53 struct b43_phy_lp *lpphy;
54
55 lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
56 if (!lpphy)
57 return -ENOMEM;
58 dev->phy.lp = lpphy;
59
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]60 return 0;
61}
62
Michael Bueschfb111372008-09-02 13:00:34 +0200[diff] [blame]63static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
64{
65 struct b43_phy *phy = &dev->phy;
66 struct b43_phy_lp *lpphy = phy->lp;
67
68 memset(lpphy, 0, sizeof(*lpphy));
69
70 //TODO
71}
72
73static void b43_lpphy_op_free(struct b43_wldev *dev)
74{
75 struct b43_phy_lp *lpphy = dev->phy.lp;
76
77 kfree(lpphy);
78 dev->phy.lp = NULL;
79}
80
Gábor Stefanik84ec1672009-08-11 21:47:00 +0200[diff] [blame]81static void lpphy_read_band_sprom(struct b43_wldev *dev)
82{
83 struct b43_phy_lp *lpphy = dev->phy.lp;
84 struct ssb_bus *bus = dev->dev->bus;
85 u16 cckpo, maxpwr;
86 u32 ofdmpo;
87 int i;
88
89 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
90 lpphy->tx_isolation_med_band = bus->sprom.tri2g;
91 lpphy->bx_arch = bus->sprom.bxa2g;
92 lpphy->rx_pwr_offset = bus->sprom.rxpo2g;
93 lpphy->rssi_vf = bus->sprom.rssismf2g;
94 lpphy->rssi_vc = bus->sprom.rssismc2g;
95 lpphy->rssi_gs = bus->sprom.rssisav2g;
96 lpphy->txpa[0] = bus->sprom.pa0b0;
97 lpphy->txpa[1] = bus->sprom.pa0b1;
98 lpphy->txpa[2] = bus->sprom.pa0b2;
99 maxpwr = bus->sprom.maxpwr_bg;
100 lpphy->max_tx_pwr_med_band = maxpwr;
101 cckpo = bus->sprom.cck2gpo;
102 ofdmpo = bus->sprom.ofdm2gpo;
103 if (cckpo) {
104 for (i = 0; i < 4; i++) {
105 lpphy->tx_max_rate[i] =
106 maxpwr - (ofdmpo & 0xF) * 2;
107 ofdmpo >>= 4;
108 }
109 ofdmpo = bus->sprom.ofdm2gpo;
110 for (i = 4; i < 15; i++) {
111 lpphy->tx_max_rate[i] =
112 maxpwr - (ofdmpo & 0xF) * 2;
113 ofdmpo >>= 4;
114 }
115 } else {
116 ofdmpo &= 0xFF;
117 for (i = 0; i < 4; i++)
118 lpphy->tx_max_rate[i] = maxpwr;
119 for (i = 4; i < 15; i++)
120 lpphy->tx_max_rate[i] = maxpwr - ofdmpo;
121 }
122 } else { /* 5GHz */
123 lpphy->tx_isolation_low_band = bus->sprom.tri5gl;
124 lpphy->tx_isolation_med_band = bus->sprom.tri5g;
125 lpphy->tx_isolation_hi_band = bus->sprom.tri5gh;
126 lpphy->bx_arch = bus->sprom.bxa5g;
127 lpphy->rx_pwr_offset = bus->sprom.rxpo5g;
128 lpphy->rssi_vf = bus->sprom.rssismf5g;
129 lpphy->rssi_vc = bus->sprom.rssismc5g;
130 lpphy->rssi_gs = bus->sprom.rssisav5g;
131 lpphy->txpa[0] = bus->sprom.pa1b0;
132 lpphy->txpa[1] = bus->sprom.pa1b1;
133 lpphy->txpa[2] = bus->sprom.pa1b2;
134 lpphy->txpal[0] = bus->sprom.pa1lob0;
135 lpphy->txpal[1] = bus->sprom.pa1lob1;
136 lpphy->txpal[2] = bus->sprom.pa1lob2;
137 lpphy->txpah[0] = bus->sprom.pa1hib0;
138 lpphy->txpah[1] = bus->sprom.pa1hib1;
139 lpphy->txpah[2] = bus->sprom.pa1hib2;
140 maxpwr = bus->sprom.maxpwr_al;
141 ofdmpo = bus->sprom.ofdm5glpo;
142 lpphy->max_tx_pwr_low_band = maxpwr;
143 for (i = 4; i < 12; i++) {
144 lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
145 ofdmpo >>= 4;
146 }
147 maxpwr = bus->sprom.maxpwr_a;
148 ofdmpo = bus->sprom.ofdm5gpo;
149 lpphy->max_tx_pwr_med_band = maxpwr;
150 for (i = 4; i < 12; i++) {
151 lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
152 ofdmpo >>= 4;
153 }
154 maxpwr = bus->sprom.maxpwr_ah;
155 ofdmpo = bus->sprom.ofdm5ghpo;
156 lpphy->max_tx_pwr_hi_band = maxpwr;
157 for (i = 4; i < 12; i++) {
158 lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
159 ofdmpo >>= 4;
160 }
161 }
162}
163
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]164static void lpphy_adjust_gain_table(struct b43_wldev *dev, u32 freq)
Gábor Stefanikc65d6fb2009-08-10 20:39:47 +0200[diff] [blame]165{
166 struct b43_phy_lp *lpphy = dev->phy.lp;
Gábor Stefanikc65d6fb2009-08-10 20:39:47 +0200[diff] [blame]167 u16 temp[3];
168 u16 isolation;
169
170 B43_WARN_ON(dev->phy.rev >= 2);
171
172 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
173 isolation = lpphy->tx_isolation_med_band;
174 else if (freq <= 5320)
175 isolation = lpphy->tx_isolation_low_band;
176 else if (freq <= 5700)
177 isolation = lpphy->tx_isolation_med_band;
178 else
179 isolation = lpphy->tx_isolation_hi_band;
180
181 temp[0] = ((isolation - 26) / 12) << 12;
182 temp[1] = temp[0] + 0x1000;
183 temp[2] = temp[0] + 0x2000;
184
185 b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
186 b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
187}
188
Michael Buescha387cc72009-01-31 14:20:44 +0100[diff] [blame]189static void lpphy_table_init(struct b43_wldev *dev)
190{
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]191 u32 freq = channel2freq_lp(b43_lpphy_op_get_default_chan(dev));
192
Gábor Stefanikc65d6fb2009-08-10 20:39:47 +0200[diff] [blame]193 if (dev->phy.rev < 2)
194 lpphy_rev0_1_table_init(dev);
195 else
196 lpphy_rev2plus_table_init(dev);
197
198 lpphy_init_tx_gain_table(dev);
199
200 if (dev->phy.rev < 2)
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]201 lpphy_adjust_gain_table(dev, freq);
Michael Buescha387cc72009-01-31 14:20:44 +0100[diff] [blame]202}
203
204static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
205{
Gábor Stefanik738f0f42009-08-03 01:28:12 +0200[diff] [blame]206 struct ssb_bus *bus = dev->dev->bus;
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]207 struct b43_phy_lp *lpphy = dev->phy.lp;
Gábor Stefanik738f0f42009-08-03 01:28:12 +0200[diff] [blame]208 u16 tmp, tmp2;
209
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]210 b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF);
211 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0);
212 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
213 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
214 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
215 b43_phy_set(dev, B43_LPPHY_AFE_DAC_CTL, 0x0004);
216 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x0078);
217 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
218 b43_phy_write(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x0016);
219 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_0, 0xFFF8, 0x0004);
220 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5400);
221 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2400);
222 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
223 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0x0006);
224 b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE);
225 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x0005);
226 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC10, 0x0180);
227 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x3800);
228 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFFF0, 0x0005);
229 b43_phy_maskset(dev, B43_LPPHY_GAIN_MISMATCH_LIMIT, 0xFFC0, 0x001A);
230 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0x00B3);
231 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
232 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB,
233 0xFF00, lpphy->rx_pwr_offset);
234 if ((bus->sprom.boardflags_lo & B43_BFL_FEM) &&
235 ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
236 (bus->sprom.boardflags_hi & B43_BFH_PAREF))) {
237 /* TODO:
238 * Set the LDO voltage to 0x0028 - FIXME: What is this?
239 * Call sb_pmu_set_ldo_voltage with 4 and the LDO voltage
240 * as arguments
241 * Call sb_pmu_paref_ldo_enable with argument TRUE
242 */
243 if (dev->phy.rev == 0) {
244 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
245 0xFFCF, 0x0010);
246 }
247 b43_lptab_write(dev, B43_LPTAB16(11, 7), 60);
248 } else {
249 //TODO: Call ssb_pmu_paref_ldo_enable with argument FALSE
250 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
251 0xFFCF, 0x0020);
252 b43_lptab_write(dev, B43_LPTAB16(11, 7), 100);
253 }
254 tmp = lpphy->rssi_vf | lpphy->rssi_vc << 4 | 0xA000;
255 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp);
256 if (bus->sprom.boardflags_hi & B43_BFH_RSSIINV)
257 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA);
258 else
259 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA);
260 b43_lptab_write(dev, B43_LPTAB16(11, 1), 24);
261 b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL,
262 0xFFF9, (lpphy->bx_arch << 1));
Gábor Stefanik738f0f42009-08-03 01:28:12 +0200[diff] [blame]263 if (dev->phy.rev == 1 &&
264 (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
265 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
266 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
267 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
268 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
269 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
270 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
271 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
272 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
273 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
274 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
275 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
276 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
277 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
278 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
279 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
280 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
281 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
282 (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
283 (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
284 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
285 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
286 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
287 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
288 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
289 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
290 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
291 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
292 } else if (dev->phy.rev == 1 ||
293 (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
294 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
295 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
296 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
297 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
298 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
299 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
300 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
301 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
302 } else {
303 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
304 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
305 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
306 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
307 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
308 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
309 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
310 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
311 }
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]312 if (dev->phy.rev == 1 && (bus->sprom.boardflags_hi & B43_BFH_PAREF)) {
Gábor Stefanik738f0f42009-08-03 01:28:12 +0200[diff] [blame]313 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
314 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
315 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
316 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
317 }
318 if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
319 (bus->chip_id == 0x5354) &&
320 (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
321 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
322 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
323 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]324 //FIXME the Broadcom driver caches & delays this HF write!
Gábor Stefanik7c81e982009-08-05 00:25:42 +0200[diff] [blame]325 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
Gábor Stefanik738f0f42009-08-03 01:28:12 +0200[diff] [blame]326 }
327 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
328 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
329 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
330 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
331 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
332 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
333 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
334 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
335 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
336 } else { /* 5GHz */
337 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
338 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
339 }
340 if (dev->phy.rev == 1) {
341 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
342 tmp2 = (tmp & 0x03E0) >> 5;
343 tmp2 |= tmp << 5;
344 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
345 tmp = b43_phy_read(dev, B43_LPPHY_OFDMSYNCTHRESH0);
346 tmp2 = (tmp & 0x1F00) >> 8;
347 tmp2 |= tmp << 5;
348 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
349 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
350 tmp2 = tmp & 0x00FF;
351 tmp2 |= tmp << 8;
352 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
353 }
Michael Buescha387cc72009-01-31 14:20:44 +0100[diff] [blame]354}
355
Gábor Stefanika3e14f32009-08-10 20:57:06 +0200[diff] [blame]356static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
357{
358 static const u16 addr[] = {
359 B43_PHY_OFDM(0xC1),
360 B43_PHY_OFDM(0xC2),
361 B43_PHY_OFDM(0xC3),
362 B43_PHY_OFDM(0xC4),
363 B43_PHY_OFDM(0xC5),
364 B43_PHY_OFDM(0xC6),
365 B43_PHY_OFDM(0xC7),
366 B43_PHY_OFDM(0xC8),
367 B43_PHY_OFDM(0xCF),
368 };
369
370 static const u16 coefs[] = {
371 0xDE5E, 0xE832, 0xE331, 0x4D26,
372 0x0026, 0x1420, 0x0020, 0xFE08,
373 0x0008,
374 };
375
376 struct b43_phy_lp *lpphy = dev->phy.lp;
377 int i;
378
379 for (i = 0; i < ARRAY_SIZE(addr); i++) {
380 lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]);
381 b43_phy_write(dev, addr[i], coefs[i]);
382 }
383}
384
385static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
386{
387 static const u16 addr[] = {
388 B43_PHY_OFDM(0xC1),
389 B43_PHY_OFDM(0xC2),
390 B43_PHY_OFDM(0xC3),
391 B43_PHY_OFDM(0xC4),
392 B43_PHY_OFDM(0xC5),
393 B43_PHY_OFDM(0xC6),
394 B43_PHY_OFDM(0xC7),
395 B43_PHY_OFDM(0xC8),
396 B43_PHY_OFDM(0xCF),
397 };
398
399 struct b43_phy_lp *lpphy = dev->phy.lp;
400 int i;
401
402 for (i = 0; i < ARRAY_SIZE(addr); i++)
403 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
404}
405
Michael Buescha387cc72009-01-31 14:20:44 +0100[diff] [blame]406static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
407{
Michael Buesch686aa5f2009-02-03 19:36:45 +0100[diff] [blame]408 struct ssb_bus *bus = dev->dev->bus;
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]409 struct b43_phy_lp *lpphy = dev->phy.lp;
410
411 b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
412 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
413 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
414 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
415 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
416 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
417 b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
418 b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
419 b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
Gábor Stefanika3e14f32009-08-10 20:57:06 +0200[diff] [blame]420 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4);
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]421 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
422 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
423 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
424 b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
425 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
426 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
427 b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
Gábor Stefanika3e14f32009-08-10 20:57:06 +0200[diff] [blame]428 if (bus->boardinfo.rev >= 0x18) {
429 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
430 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
431 } else {
432 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
433 }
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]434 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]435 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]436 b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
437 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
438 b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
439 b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
440 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
441 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]442 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0);
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]443 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
444 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
Michael Buesch686aa5f2009-02-03 19:36:45 +0100[diff] [blame]445 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
446 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
447 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
448 } else {
449 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
450 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
451 }
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]452 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
453 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
454 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
455 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
456 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
457 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
458 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
459 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
460 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
461 b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
462
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]463 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
Gábor Stefanika3e14f32009-08-10 20:57:06 +0200[diff] [blame]464 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
465 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
466 }
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]467
468 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
469 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
470 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
471 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
472 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
473 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]474 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
Michael Buesch6c1bb922009-01-31 16:52:29 +0100[diff] [blame]475 } else /* 5GHz */
476 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
477
478 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
479 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
480 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
481 b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
482 b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
483 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
484 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
485 0x2000 | ((u16)lpphy->rssi_gs << 10) |
486 ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
Gábor Stefanika3e14f32009-08-10 20:57:06 +0200[diff] [blame]487
488 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
489 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
490 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
491 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
492 }
493
494 lpphy_save_dig_flt_state(dev);
Michael Buescha387cc72009-01-31 14:20:44 +0100[diff] [blame]495}
496
497static void lpphy_baseband_init(struct b43_wldev *dev)
498{
499 lpphy_table_init(dev);
500 if (dev->phy.rev >= 2)
501 lpphy_baseband_rev2plus_init(dev);
502 else
503 lpphy_baseband_rev0_1_init(dev);
504}
505
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]506struct b2062_freqdata {
507 u16 freq;
508 u8 data[6];
509};
510
511/* Initialize the 2062 radio. */
512static void lpphy_2062_init(struct b43_wldev *dev)
513{
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]514 struct b43_phy_lp *lpphy = dev->phy.lp;
Michael Buesch99e0fca2009-02-03 20:06:14 +0100[diff] [blame]515 struct ssb_bus *bus = dev->dev->bus;
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]516 u32 crystalfreq, tmp, ref;
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]517 unsigned int i;
518 const struct b2062_freqdata *fd = NULL;
519
520 static const struct b2062_freqdata freqdata_tab[] = {
521 { .freq = 12000, .data[0] = 6, .data[1] = 6, .data[2] = 6,
522 .data[3] = 6, .data[4] = 10, .data[5] = 6, },
523 { .freq = 13000, .data[0] = 4, .data[1] = 4, .data[2] = 4,
524 .data[3] = 4, .data[4] = 11, .data[5] = 7, },
525 { .freq = 14400, .data[0] = 3, .data[1] = 3, .data[2] = 3,
526 .data[3] = 3, .data[4] = 12, .data[5] = 7, },
527 { .freq = 16200, .data[0] = 3, .data[1] = 3, .data[2] = 3,
528 .data[3] = 3, .data[4] = 13, .data[5] = 8, },
529 { .freq = 18000, .data[0] = 2, .data[1] = 2, .data[2] = 2,
530 .data[3] = 2, .data[4] = 14, .data[5] = 8, },
531 { .freq = 19200, .data[0] = 1, .data[1] = 1, .data[2] = 1,
532 .data[3] = 1, .data[4] = 14, .data[5] = 9, },
533 };
534
535 b2062_upload_init_table(dev);
536
537 b43_radio_write(dev, B2062_N_TX_CTL3, 0);
538 b43_radio_write(dev, B2062_N_TX_CTL4, 0);
539 b43_radio_write(dev, B2062_N_TX_CTL5, 0);
540 b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
541 b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
542 b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
543 b43_radio_write(dev, B2062_N_CALIB_TS, 0);
544 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
545 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
546 else
547 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
548
Michael Buesch99e0fca2009-02-03 20:06:14 +0100[diff] [blame]549 /* Get the crystal freq, in Hz. */
550 crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
551
552 B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
553 B43_WARN_ON(crystalfreq == 0);
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]554
555 if (crystalfreq >= 30000000) {
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]556 lpphy->pdiv = 1;
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]557 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
558 } else {
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]559 lpphy->pdiv = 2;
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]560 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
561 }
562
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]563 tmp = (800000000 * lpphy->pdiv + crystalfreq) /
564 (32000000 * lpphy->pdiv);
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]565 tmp = (tmp - 1) & 0xFF;
566 b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
567
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]568 tmp = (2 * crystalfreq + 1000000 * lpphy->pdiv) /
569 (2000000 * lpphy->pdiv);
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]570 tmp = ((tmp & 0xFF) - 1) & 0xFFFF;
571 b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
572
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]573 ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv);
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]574 ref &= 0xFFFF;
575 for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
576 if (ref < freqdata_tab[i].freq) {
577 fd = &freqdata_tab[i];
578 break;
579 }
580 }
Michael Buesch99e0fca2009-02-03 20:06:14 +0100[diff] [blame]581 if (!fd)
582 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
583 b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
584 fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]585
586 b43_radio_write(dev, B2062_S_RFPLL_CTL8,
587 ((u16)(fd->data[1]) << 4) | fd->data[0]);
588 b43_radio_write(dev, B2062_S_RFPLL_CTL9,
Michael Buesch99e0fca2009-02-03 20:06:14 +0100[diff] [blame]589 ((u16)(fd->data[3]) << 4) | fd->data[2]);
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]590 b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
591 b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
592}
593
594/* Initialize the 2063 radio. */
595static void lpphy_2063_init(struct b43_wldev *dev)
Michael Buescha387cc72009-01-31 14:20:44 +0100[diff] [blame]596{
Gábor Stefanikc10e47f2009-08-04 23:57:32 +0200[diff] [blame]597 b2063_upload_init_table(dev);
598 b43_radio_write(dev, B2063_LOGEN_SP5, 0);
599 b43_radio_set(dev, B2063_COMM8, 0x38);
600 b43_radio_write(dev, B2063_REG_SP1, 0x56);
601 b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
602 b43_radio_write(dev, B2063_PA_SP7, 0);
603 b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
604 b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
605 b43_radio_write(dev, B2063_PA_SP3, 0xa0);
606 b43_radio_write(dev, B2063_PA_SP4, 0xa0);
607 b43_radio_write(dev, B2063_PA_SP2, 0x18);
Michael Buescha387cc72009-01-31 14:20:44 +0100[diff] [blame]608}
609
Gábor Stefanik3281d952009-08-09 20:15:09 +0200[diff] [blame]610struct lpphy_stx_table_entry {
611 u16 phy_offset;
612 u16 phy_shift;
613 u16 rf_addr;
614 u16 rf_shift;
615 u16 mask;
616};
617
618static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
619 { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
620 { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
621 { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
622 { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
623 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
624 { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
625 { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
626 { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
627 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
628 { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
629 { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
630 { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
631 { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
632 { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
633 { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
634 { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
635 { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
636 { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
637 { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
638 { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
639 { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
640 { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
641 { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
642 { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
643 { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
644 { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
645 { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
646 { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
647 { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
648};
649
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]650static void lpphy_sync_stx(struct b43_wldev *dev)
651{
Gábor Stefanik3281d952009-08-09 20:15:09 +0200[diff] [blame]652 const struct lpphy_stx_table_entry *e;
653 unsigned int i;
654 u16 tmp;
655
656 for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
657 e = &lpphy_stx_table[i];
658 tmp = b43_radio_read(dev, e->rf_addr);
659 tmp >>= e->rf_shift;
660 tmp <<= e->phy_shift;
661 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
Gábor Stefanikd44517f22009-08-11 00:54:26 +0200[diff] [blame]662 ~(e->mask << e->phy_shift), tmp);
Gábor Stefanik3281d952009-08-09 20:15:09 +0200[diff] [blame]663 }
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]664}
665
666static void lpphy_radio_init(struct b43_wldev *dev)
667{
668 /* The radio is attached through the 4wire bus. */
669 b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
670 udelay(1);
671 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
672 udelay(1);
673
674 if (dev->phy.rev < 2) {
675 lpphy_2062_init(dev);
676 } else {
677 lpphy_2063_init(dev);
678 lpphy_sync_stx(dev);
679 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
680 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
Gábor Stefanik3281d952009-08-09 20:15:09 +0200[diff] [blame]681 if (dev->dev->bus->chip_id == 0x4325) {
682 // TODO SSB PMU recalibration
683 }
Michael Buesch24b5bcc2009-01-31 19:34:53 +0100[diff] [blame]684 }
685}
686
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]687struct lpphy_iq_est { u32 iq_prod, i_pwr, q_pwr; };
688
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]689static void lpphy_set_rc_cap(struct b43_wldev *dev)
690{
691 u8 rc_cap = dev->phy.lp->rc_cap;
692
693 b43_radio_write(dev, B2062_N_RXBB_CALIB2, max_t(u8, rc_cap-4, 0x80));
694 b43_radio_write(dev, B2062_N_TX_CTL_A, ((rc_cap & 0x1F) >> 1) | 0x80);
695 b43_radio_write(dev, B2062_S_RXG_CNT16, ((rc_cap & 0x1F) >> 2) | 0x80);
696}
697
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]698static u8 lpphy_get_bb_mult(struct b43_wldev *dev)
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]699{
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]700 return (b43_lptab_read(dev, B43_LPTAB16(0, 87)) & 0xFF00) >> 8;
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]701}
702
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]703static void lpphy_set_bb_mult(struct b43_wldev *dev, u8 bb_mult)
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]704{
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]705 b43_lptab_write(dev, B43_LPTAB16(0, 87), (u16)bb_mult << 8);
706}
707
708static void lpphy_disable_crs(struct b43_wldev *dev)
709{
710 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x80);
711 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x1);
712 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
713 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
714 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
715 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7);
716 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
717 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10);
718 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
719 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF);
720 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
721 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF);
722 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
723 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x7);
724 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x38);
725 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F);
726 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x100);
727 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF);
728 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0);
729 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1);
730 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20);
731 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF);
732 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF);
733 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0);
734 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF);
735 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF);
736}
737
738static void lpphy_restore_crs(struct b43_wldev *dev)
739{
740 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
741 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x60);
742 else
743 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x20);
744 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80);
745 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00);
746}
747
748struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
749
750static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
751{
752 struct lpphy_tx_gains gains;
753 u16 tmp;
754
755 gains.dac = (b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0x380) >> 7;
756 if (dev->phy.rev < 2) {
757 tmp = b43_phy_read(dev,
758 B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL) & 0x7FF;
759 gains.gm = tmp & 0x0007;
760 gains.pga = (tmp & 0x0078) >> 3;
761 gains.pad = (tmp & 0x780) >> 7;
762 } else {
763 tmp = b43_phy_read(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL);
764 gains.pad = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0xFF;
765 gains.gm = tmp & 0xFF;
766 gains.pga = (tmp >> 8) & 0xFF;
767 }
768
769 return gains;
770}
771
772static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
773{
774 u16 ctl = b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0xC7F;
775 ctl |= dac << 7;
776 b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
777}
778
779static void lpphy_set_tx_gains(struct b43_wldev *dev,
780 struct lpphy_tx_gains gains)
781{
782 u16 rf_gain, pa_gain;
783
784 if (dev->phy.rev < 2) {
785 rf_gain = (gains.pad << 7) | (gains.pga << 3) | gains.gm;
786 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
787 0xF800, rf_gain);
788 } else {
789 pa_gain = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x7F00;
790 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
791 (gains.pga << 8) | gains.gm);
792 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
793 0x8000, gains.pad | pa_gain);
794 b43_phy_write(dev, B43_PHY_OFDM(0xFC),
795 (gains.pga << 8) | gains.gm);
796 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
797 0x8000, gains.pad | pa_gain);
798 }
799 lpphy_set_dac_gain(dev, gains.dac);
800 if (dev->phy.rev < 2) {
801 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF, 1 << 8);
802 } else {
803 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F, 1 << 7);
804 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF, 1 << 14);
805 }
Gábor Stefanik16373f62009-08-14 22:10:34 +0200[diff] [blame]806 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFBF, 1 << 6);
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]807}
808
809static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
810{
811 u16 trsw = gain & 0x1;
812 u16 lna = (gain & 0xFFFC) | ((gain & 0xC) >> 2);
813 u16 ext_lna = (gain & 2) >> 1;
814
815 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
816 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
817 0xFBFF, ext_lna << 10);
818 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
819 0xF7FF, ext_lna << 11);
820 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna);
821}
822
823static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
824{
825 u16 low_gain = gain & 0xFFFF;
826 u16 high_gain = (gain >> 16) & 0xF;
827 u16 ext_lna = (gain >> 21) & 0x1;
828 u16 trsw = ~(gain >> 20) & 0x1;
829 u16 tmp;
830
831 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
832 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
833 0xFDFF, ext_lna << 9);
834 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
835 0xFBFF, ext_lna << 10);
836 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain);
837 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF0, high_gain);
838 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
839 tmp = (gain >> 2) & 0x3;
840 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
841 0xE7FF, tmp<<11);
842 b43_phy_maskset(dev, B43_PHY_OFDM(0xE6), 0xFFE7, tmp << 3);
843 }
844}
845
846static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
847{
848 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
849 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
850 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
851 if (dev->phy.rev >= 2) {
852 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
853 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ)
854 return;
855 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
856 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFF7);
857 } else {
858 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
859 }
860}
861
862static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
863{
864 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
865 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
866 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
867 if (dev->phy.rev >= 2) {
868 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
869 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ)
870 return;
871 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
872 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x8);
873 } else {
874 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
875 }
876}
877
878static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
879{
880 if (dev->phy.rev < 2)
881 lpphy_rev0_1_set_rx_gain(dev, gain);
882 else
883 lpphy_rev2plus_set_rx_gain(dev, gain);
884 lpphy_enable_rx_gain_override(dev);
885}
886
887static void lpphy_set_rx_gain_by_index(struct b43_wldev *dev, u16 idx)
888{
889 u32 gain = b43_lptab_read(dev, B43_LPTAB16(12, idx));
890 lpphy_set_rx_gain(dev, gain);
891}
892
893static void lpphy_stop_ddfs(struct b43_wldev *dev)
894{
895 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD);
896 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF);
897}
898
899static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on,
900 int incr1, int incr2, int scale_idx)
901{
902 lpphy_stop_ddfs(dev);
903 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80);
904 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF);
905 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0xFF80, incr1);
906 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0x80FF, incr2 << 8);
907 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF7, i_on << 3);
908 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFEF, q_on << 4);
909 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5);
910 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB);
911 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2);
912 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x20);
913}
914
915static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time,
916 struct lpphy_iq_est *iq_est)
917{
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]918 int i;
919
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]920 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7);
921 b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples);
922 b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time);
923 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF);
924 b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFDFF);
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]925
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]926 for (i = 0; i < 500; i++) {
927 if (!(b43_phy_read(dev,
928 B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200))
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]929 break;
930 msleep(1);
931 }
932
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]933 if ((b43_phy_read(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) {
934 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
935 return false;
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]936 }
937
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]938 iq_est->iq_prod = b43_phy_read(dev, B43_LPPHY_IQ_ACC_HI_ADDR);
939 iq_est->iq_prod <<= 16;
940 iq_est->iq_prod |= b43_phy_read(dev, B43_LPPHY_IQ_ACC_LO_ADDR);
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]941
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]942 iq_est->i_pwr = b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR);
943 iq_est->i_pwr <<= 16;
944 iq_est->i_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR);
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]945
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]946 iq_est->q_pwr = b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR);
947 iq_est->q_pwr <<= 16;
948 iq_est->q_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR);
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]949
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]950 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
951 return true;
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]952}
953
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]954static int lpphy_loopback(struct b43_wldev *dev)
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]955{
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]956 struct lpphy_iq_est iq_est;
957 int i, index = -1;
958 u32 tmp;
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]959
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]960 memset(&iq_est, 0, sizeof(iq_est));
961
962 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x3);
963 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
964 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
965 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
966 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
967 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
968 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x8);
969 b43_radio_write(dev, B2062_N_TX_CTL_A, 0x80);
970 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x80);
971 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x80);
972 for (i = 0; i < 32; i++) {
973 lpphy_set_rx_gain_by_index(dev, i);
974 lpphy_run_ddfs(dev, 1, 1, 5, 5, 0);
975 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
976 continue;
977 tmp = (iq_est.i_pwr + iq_est.q_pwr) / 1000;
978 if ((tmp > 4000) && (tmp < 10000)) {
979 index = i;
980 break;
981 }
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]982 }
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]983 lpphy_stop_ddfs(dev);
984 return index;
985}
986
987static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
988{
989 u32 quotient, remainder, rbit, roundup, tmp;
990
991 if (divisor == 0) {
992 quotient = 0;
993 remainder = 0;
994 } else {
995 quotient = dividend / divisor;
996 remainder = dividend % divisor;
997 }
998
999 rbit = divisor & 0x1;
1000 roundup = (divisor >> 1) + rbit;
1001 precision--;
1002
1003 while (precision != 0xFF) {
1004 tmp = remainder - roundup;
1005 quotient <<= 1;
1006 remainder <<= 1;
1007 if (remainder >= roundup) {
1008 remainder = (tmp << 1) + rbit;
1009 quotient--;
1010 }
1011 precision--;
1012 }
1013
1014 if (remainder >= roundup)
1015 quotient++;
1016
1017 return quotient;
Gábor Stefanikd4de9532009-08-11 21:53:06 +0200[diff] [blame]1018}
1019
Michael Bueschce1a9ee2009-02-04 19:55:22 +0100[diff] [blame]1020/* Read the TX power control mode from hardware. */
1021static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
1022{
1023 struct b43_phy_lp *lpphy = dev->phy.lp;
1024 u16 ctl;
1025
1026 ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
1027 switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
1028 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
1029 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
1030 break;
1031 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
1032 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
1033 break;
1034 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
1035 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
1036 break;
1037 default:
1038 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
1039 B43_WARN_ON(1);
1040 break;
1041 }
1042}
1043
1044/* Set the TX power control mode in hardware. */
1045static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
1046{
1047 struct b43_phy_lp *lpphy = dev->phy.lp;
1048 u16 ctl;
1049
1050 switch (lpphy->txpctl_mode) {
1051 case B43_LPPHY_TXPCTL_OFF:
1052 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
1053 break;
1054 case B43_LPPHY_TXPCTL_HW:
1055 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
1056 break;
1057 case B43_LPPHY_TXPCTL_SW:
1058 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
1059 break;
1060 default:
1061 ctl = 0;
1062 B43_WARN_ON(1);
1063 }
1064 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1065 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
1066}
1067
1068static void lpphy_set_tx_power_control(struct b43_wldev *dev,
1069 enum b43_lpphy_txpctl_mode mode)
1070{
1071 struct b43_phy_lp *lpphy = dev->phy.lp;
1072 enum b43_lpphy_txpctl_mode oldmode;
1073
1074 oldmode = lpphy->txpctl_mode;
1075 lpphy_read_tx_pctl_mode_from_hardware(dev);
1076 if (lpphy->txpctl_mode == mode)
1077 return;
1078 lpphy->txpctl_mode = mode;
1079
1080 if (oldmode == B43_LPPHY_TXPCTL_HW) {
1081 //TODO Update TX Power NPT
1082 //TODO Clear all TX Power offsets
1083 } else {
1084 if (mode == B43_LPPHY_TXPCTL_HW) {
1085 //TODO Recalculate target TX power
1086 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1087 0xFF80, lpphy->tssi_idx);
1088 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
1089 0x8FFF, ((u16)lpphy->tssi_npt << 16));
1090 //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
1091 //TODO Disable TX gain override
1092 lpphy->tx_pwr_idx_over = -1;
1093 }
1094 }
1095 if (dev->phy.rev >= 2) {
1096 if (mode == B43_LPPHY_TXPCTL_HW)
1097 b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0x2);
1098 else
1099 b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0);
1100 }
1101 lpphy_write_tx_pctl_mode_to_hardware(dev);
1102}
1103
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]1104static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
1105{
1106 struct b43_phy_lp *lpphy = dev->phy.lp;
1107 struct lpphy_iq_est iq_est;
1108 struct lpphy_tx_gains tx_gains;
1109 static const u32 ideal_pwr_table[22] = {
1110 0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64,
1111 0x0eda2, 0x0e5d4, 0x0efd1, 0x0fbe8, 0x0b7b8, 0x04b35,
1112 0x01a5e, 0x00a0b, 0x00444, 0x001fd, 0x000ff, 0x00088,
1113 0x0004c, 0x0002c, 0x0001a, 0xc0006,
1114 };
1115 bool old_txg_ovr;
1116 u8 old_bbmult;
1117 u16 old_rf_ovr, old_rf_ovrval, old_afe_ovr, old_afe_ovrval,
Gábor Stefanik12456842009-08-14 23:00:32 +0200[diff] [blame]1118 old_rf2_ovr, old_rf2_ovrval, old_phy_ctl;
1119 enum b43_lpphy_txpctl_mode old_txpctl;
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]1120 u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0;
1121 int loopback, i, j, inner_sum;
1122
1123 memset(&iq_est, 0, sizeof(iq_est));
1124
1125 b43_switch_channel(dev, 7);
1126 old_txg_ovr = (b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) >> 6) & 1;
1127 old_bbmult = lpphy_get_bb_mult(dev);
1128 if (old_txg_ovr)
1129 tx_gains = lpphy_get_tx_gains(dev);
1130 old_rf_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_0);
1131 old_rf_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_VAL_0);
1132 old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR);
1133 old_afe_ovrval = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVRVAL);
1134 old_rf2_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2);
1135 old_rf2_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2_VAL);
1136 old_phy_ctl = b43_phy_read(dev, B43_LPPHY_LP_PHY_CTL);
Gábor Stefanik12456842009-08-14 23:00:32 +0200[diff] [blame]1137 lpphy_read_tx_pctl_mode_from_hardware(dev);
1138 old_txpctl = lpphy->txpctl_mode;
Gábor Stefanik560ad812009-08-13 14:19:02 +0200[diff] [blame]1139
1140 lpphy_set_tx_power_control(dev, B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
1141 lpphy_disable_crs(dev);
1142 loopback = lpphy_loopback(dev);
1143 if (loopback == -1)
1144 goto finish;
1145 lpphy_set_rx_gain_by_index(dev, loopback);
1146 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFFBF, 0x40);
1147 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFF8, 0x1);
1148 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFC7, 0x8);
1149 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F, 0xC0);
1150 for (i = 128; i <= 159; i++) {
1151 b43_radio_write(dev, B2062_N_RXBB_CALIB2, i);
1152 inner_sum = 0;
1153 for (j = 5; j <= 25; j++) {
1154 lpphy_run_ddfs(dev, 1, 1, j, j, 0);
1155 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1156 goto finish;
1157 mean_sq_pwr = iq_est.i_pwr + iq_est.q_pwr;
1158 if (j == 5)
1159 tmp = mean_sq_pwr;
1160 ideal_pwr = ((ideal_pwr_table[j-5] >> 3) + 1) >> 1;
1161 normal_pwr = lpphy_qdiv_roundup(mean_sq_pwr, tmp, 12);
1162 mean_sq_pwr = ideal_pwr - normal_pwr;
1163 mean_sq_pwr *= mean_sq_pwr;
1164 inner_sum += mean_sq_pwr;
1165 if ((i = 128) || (inner_sum < mean_sq_pwr_min)) {
1166 lpphy->rc_cap = i;
1167 mean_sq_pwr_min = inner_sum;
1168 }
1169 }
1170 }
1171 lpphy_stop_ddfs(dev);
1172
1173finish:
1174 lpphy_restore_crs(dev);
1175 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval);
1176 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr);
1177 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval);
1178 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr);
1179 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval);
1180 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr);
1181 b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl);
1182
1183 lpphy_set_bb_mult(dev, old_bbmult);
1184 if (old_txg_ovr) {
1185 /*
1186 * SPEC FIXME: The specs say "get_tx_gains" here, which is
1187 * illogical. According to lwfinger, vendor driver v4.150.10.5
1188 * has a Set here, while v4.174.64.19 has a Get - regression in
1189 * the vendor driver? This should be tested this once the code
1190 * is testable.
1191 */
1192 lpphy_set_tx_gains(dev, tx_gains);
1193 }
1194 lpphy_set_tx_power_control(dev, old_txpctl);
1195 if (lpphy->rc_cap)
1196 lpphy_set_rc_cap(dev);
1197}
1198
1199static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev)
1200{
1201 struct ssb_bus *bus = dev->dev->bus;
1202 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1203 u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF;
1204 int i;
1205
1206 b43_radio_write(dev, B2063_RX_BB_SP8, 0x0);
1207 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1208 b43_radio_mask(dev, B2063_PLL_SP1, 0xF7);
1209 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1210 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x15);
1211 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x70);
1212 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x52);
1213 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1214 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7D);
1215
1216 for (i = 0; i < 10000; i++) {
1217 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1218 break;
1219 msleep(1);
1220 }
1221
1222 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1223 b43_radio_write(dev, B2063_RX_BB_SP8, tmp);
1224
1225 tmp = b43_radio_read(dev, B2063_TX_BB_SP3) & 0xFF;
1226
1227 b43_radio_write(dev, B2063_TX_BB_SP3, 0x0);
1228 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1229 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1230 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x55);
1231 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x76);
1232
1233 if (crystal_freq == 24000000) {
1234 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0xFC);
1235 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x0);
1236 } else {
1237 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x13);
1238 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1239 }
1240
1241 b43_radio_write(dev, B2063_PA_SP7, 0x7D);
1242
1243 for (i = 0; i < 10000; i++) {
1244 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1245 break;
1246 msleep(1);
1247 }
1248
1249 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1250 b43_radio_write(dev, B2063_TX_BB_SP3, tmp);
1251
1252 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1253}
1254
1255static void lpphy_calibrate_rc(struct b43_wldev *dev)
1256{
1257 struct b43_phy_lp *lpphy = dev->phy.lp;
1258
1259 if (dev->phy.rev >= 2) {
1260 lpphy_rev2plus_rc_calib(dev);
1261 } else if (!lpphy->rc_cap) {
1262 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1263 lpphy_rev0_1_rc_calib(dev);
1264 } else {
1265 lpphy_set_rc_cap(dev);
1266 }
1267}
1268
Michael Bueschce1a9ee2009-02-04 19:55:22 +0100[diff] [blame]1269static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
1270{
1271 struct b43_phy_lp *lpphy = dev->phy.lp;
1272
1273 lpphy->tx_pwr_idx_over = index;
1274 if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
1275 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
1276
1277 //TODO
1278}
1279
1280static void lpphy_btcoex_override(struct b43_wldev *dev)
1281{
1282 b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
1283 b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
1284}
1285
1286static void lpphy_pr41573_workaround(struct b43_wldev *dev)
1287{
1288 struct b43_phy_lp *lpphy = dev->phy.lp;
1289 u32 *saved_tab;
1290 const unsigned int saved_tab_size = 256;
1291 enum b43_lpphy_txpctl_mode txpctl_mode;
1292 s8 tx_pwr_idx_over;
1293 u16 tssi_npt, tssi_idx;
1294
1295 saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
1296 if (!saved_tab) {
1297 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
1298 return;
1299 }
1300
1301 lpphy_read_tx_pctl_mode_from_hardware(dev);
1302 txpctl_mode = lpphy->txpctl_mode;
1303 tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
1304 tssi_npt = lpphy->tssi_npt;
1305 tssi_idx = lpphy->tssi_idx;
1306
1307 if (dev->phy.rev < 2) {
1308 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
1309 saved_tab_size, saved_tab);
1310 } else {
1311 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
1312 saved_tab_size, saved_tab);
1313 }
1314 //TODO
1315
1316 kfree(saved_tab);
1317}
1318
1319static void lpphy_calibration(struct b43_wldev *dev)
1320{
1321 struct b43_phy_lp *lpphy = dev->phy.lp;
1322 enum b43_lpphy_txpctl_mode saved_pctl_mode;
1323
1324 b43_mac_suspend(dev);
1325
1326 lpphy_btcoex_override(dev);
1327 lpphy_read_tx_pctl_mode_from_hardware(dev);
1328 saved_pctl_mode = lpphy->txpctl_mode;
1329 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1330 //TODO Perform transmit power table I/Q LO calibration
1331 if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
1332 lpphy_pr41573_workaround(dev);
1333 //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
1334 lpphy_set_tx_power_control(dev, saved_pctl_mode);
1335 //TODO Perform I/Q calibration with a single control value set
1336
1337 b43_mac_enable(dev);
1338}
1339
Gábor Stefanik7021f622009-08-13 17:27:31 +0200[diff] [blame]1340static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode)
1341{
1342 if (mode != TSSI_MUX_EXT) {
1343 b43_radio_set(dev, B2063_PA_SP1, 0x2);
1344 b43_phy_set(dev, B43_PHY_OFDM(0xF3), 0x1000);
1345 b43_radio_write(dev, B2063_PA_CTL10, 0x51);
1346 if (mode == TSSI_MUX_POSTPA) {
1347 b43_radio_mask(dev, B2063_PA_SP1, 0xFFFE);
1348 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7);
1349 } else {
1350 b43_radio_maskset(dev, B2063_PA_SP1, 0xFFFE, 0x1);
1351 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVRVAL,
1352 0xFFC7, 0x20);
1353 }
1354 } else {
1355 B43_WARN_ON(1);
1356 }
1357}
1358
1359static void lpphy_tx_pctl_init_hw(struct b43_wldev *dev)
1360{
1361 u16 tmp;
1362 int i;
1363
1364 //SPEC TODO Call LP PHY Clear TX Power offsets
1365 for (i = 0; i < 64; i++) {
1366 if (dev->phy.rev >= 2)
1367 b43_lptab_write(dev, B43_LPTAB32(7, i + 1), i);
1368 else
1369 b43_lptab_write(dev, B43_LPTAB32(10, i + 1), i);
1370 }
1371
1372 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xFF00, 0xFF);
1373 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0x8FFF, 0x5000);
1374 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0xFFC0, 0x1F);
1375 if (dev->phy.rev < 2) {
1376 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF);
1377 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xDFFF, 0x2000);
1378 } else {
1379 b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE);
1380 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFFB, 0x4);
1381 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFEF, 0x10);
1382 b43_radio_maskset(dev, B2063_IQ_CALIB_CTL2, 0xF3, 0x1);
1383 lpphy_set_tssi_mux(dev, TSSI_MUX_POSTPA);
1384 }
1385 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0x7FFF, 0x8000);
1386 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF);
1387 b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA);
1388 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1389 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1390 B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
1391 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF);
1392 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1393 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1394 B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW);
1395
1396 if (dev->phy.rev < 2) {
1397 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF, 0x1000);
1398 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF);
1399 } else {
1400 lpphy_set_tx_power_by_index(dev, 0x7F);
1401 }
1402
1403 b43_dummy_transmission(dev, true, true);
1404
1405 tmp = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_STAT);
1406 if (tmp & 0x8000) {
1407 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI,
1408 0xFFC0, (tmp & 0xFF) - 32);
1409 }
1410
1411 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF);
1412
1413 // (SPEC?) TODO Set "Target TX frequency" variable to 0
1414 // SPEC FIXME "Set BB Multiplier to 0xE000" impossible - bb_mult is u8!
1415}
1416
1417static void lpphy_tx_pctl_init_sw(struct b43_wldev *dev)
1418{
1419 struct lpphy_tx_gains gains;
1420
1421 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1422 gains.gm = 4;
1423 gains.pad = 12;
1424 gains.pga = 12;
1425 gains.dac = 0;
1426 } else {
1427 gains.gm = 7;
1428 gains.pad = 14;
1429 gains.pga = 15;
1430 gains.dac = 0;
1431 }
1432 lpphy_set_tx_gains(dev, gains);
1433 lpphy_set_bb_mult(dev, 150);
1434}
1435
Michael Bueschce1a9ee2009-02-04 19:55:22 +0100[diff] [blame]1436/* Initialize TX power control */
1437static void lpphy_tx_pctl_init(struct b43_wldev *dev)
1438{
1439 if (0/*FIXME HWPCTL capable */) {
Gábor Stefanik7021f622009-08-13 17:27:31 +0200[diff] [blame]1440 lpphy_tx_pctl_init_hw(dev);
Michael Bueschce1a9ee2009-02-04 19:55:22 +0100[diff] [blame]1441 } else { /* This device is only software TX power control capable. */
Gábor Stefanik7021f622009-08-13 17:27:31 +0200[diff] [blame]1442 lpphy_tx_pctl_init_sw(dev);
Michael Bueschce1a9ee2009-02-04 19:55:22 +0100[diff] [blame]1443 }
1444}
1445
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]1446static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
1447{
Michael Buesch08887072008-08-30 11:49:45 +0200[diff] [blame]1448 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1449 return b43_read16(dev, B43_MMIO_PHY_DATA);
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]1450}
1451
1452static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1453{
Michael Buesch08887072008-08-30 11:49:45 +0200[diff] [blame]1454 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1455 b43_write16(dev, B43_MMIO_PHY_DATA, value);
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]1456}
1457
1458static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1459{
Michael Buesch08887072008-08-30 11:49:45 +0200[diff] [blame]1460 /* Register 1 is a 32-bit register. */
1461 B43_WARN_ON(reg == 1);
1462 /* LP-PHY needs a special bit set for read access */
1463 if (dev->phy.rev < 2) {
1464 if (reg != 0x4001)
1465 reg |= 0x100;
1466 } else
1467 reg |= 0x200;
1468
1469 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1470 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]1471}
1472
1473static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1474{
1475 /* Register 1 is a 32-bit register. */
1476 B43_WARN_ON(reg == 1);
1477
Michael Buesch08887072008-08-30 11:49:45 +0200[diff] [blame]1478 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1479 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]1480}
1481
1482static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
Johannes Berg19d337d2009-06-02 13:01:37 +0200[diff] [blame]1483 bool blocked)
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]1484{
1485 //TODO
1486}
1487
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]1488struct b206x_channel {
1489 u8 channel;
1490 u16 freq;
1491 u8 data[12];
1492};
1493
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]1494static const struct b206x_channel b2062_chantbl[] = {
1495 { .channel = 1, .freq = 2412, .data[0] = 0xFF, .data[1] = 0xFF,
1496 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1497 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1498 { .channel = 2, .freq = 2417, .data[0] = 0xFF, .data[1] = 0xFF,
1499 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1500 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1501 { .channel = 3, .freq = 2422, .data[0] = 0xFF, .data[1] = 0xFF,
1502 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1503 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1504 { .channel = 4, .freq = 2427, .data[0] = 0xFF, .data[1] = 0xFF,
1505 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1506 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1507 { .channel = 5, .freq = 2432, .data[0] = 0xFF, .data[1] = 0xFF,
1508 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1509 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1510 { .channel = 6, .freq = 2437, .data[0] = 0xFF, .data[1] = 0xFF,
1511 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1512 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1513 { .channel = 7, .freq = 2442, .data[0] = 0xFF, .data[1] = 0xFF,
1514 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1515 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1516 { .channel = 8, .freq = 2447, .data[0] = 0xFF, .data[1] = 0xFF,
1517 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1518 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1519 { .channel = 9, .freq = 2452, .data[0] = 0xFF, .data[1] = 0xFF,
1520 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1521 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1522 { .channel = 10, .freq = 2457, .data[0] = 0xFF, .data[1] = 0xFF,
1523 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1524 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1525 { .channel = 11, .freq = 2462, .data[0] = 0xFF, .data[1] = 0xFF,
1526 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1527 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1528 { .channel = 12, .freq = 2467, .data[0] = 0xFF, .data[1] = 0xFF,
1529 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1530 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1531 { .channel = 13, .freq = 2472, .data[0] = 0xFF, .data[1] = 0xFF,
1532 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1533 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1534 { .channel = 14, .freq = 2484, .data[0] = 0xFF, .data[1] = 0xFF,
1535 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1536 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1537 { .channel = 34, .freq = 5170, .data[0] = 0x00, .data[1] = 0x22,
1538 .data[2] = 0x20, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1539 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1540 { .channel = 38, .freq = 5190, .data[0] = 0x00, .data[1] = 0x11,
1541 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1542 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1543 { .channel = 42, .freq = 5210, .data[0] = 0x00, .data[1] = 0x11,
1544 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1545 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1546 { .channel = 46, .freq = 5230, .data[0] = 0x00, .data[1] = 0x00,
1547 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1548 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1549 { .channel = 36, .freq = 5180, .data[0] = 0x00, .data[1] = 0x11,
1550 .data[2] = 0x20, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1551 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1552 { .channel = 40, .freq = 5200, .data[0] = 0x00, .data[1] = 0x11,
1553 .data[2] = 0x10, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1554 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1555 { .channel = 44, .freq = 5220, .data[0] = 0x00, .data[1] = 0x11,
1556 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1557 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1558 { .channel = 48, .freq = 5240, .data[0] = 0x00, .data[1] = 0x00,
1559 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1560 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1561 { .channel = 52, .freq = 5260, .data[0] = 0x00, .data[1] = 0x00,
1562 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1563 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1564 { .channel = 56, .freq = 5280, .data[0] = 0x00, .data[1] = 0x00,
1565 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1566 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1567 { .channel = 60, .freq = 5300, .data[0] = 0x00, .data[1] = 0x00,
1568 .data[2] = 0x00, .data[3] = 0x63, .data[4] = 0x3C, .data[5] = 0x77,
1569 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1570 { .channel = 64, .freq = 5320, .data[0] = 0x00, .data[1] = 0x00,
1571 .data[2] = 0x00, .data[3] = 0x62, .data[4] = 0x3C, .data[5] = 0x77,
1572 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1573 { .channel = 100, .freq = 5500, .data[0] = 0x00, .data[1] = 0x00,
1574 .data[2] = 0x00, .data[3] = 0x30, .data[4] = 0x3C, .data[5] = 0x77,
1575 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1576 { .channel = 104, .freq = 5520, .data[0] = 0x00, .data[1] = 0x00,
1577 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1578 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1579 { .channel = 108, .freq = 5540, .data[0] = 0x00, .data[1] = 0x00,
1580 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1581 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1582 { .channel = 112, .freq = 5560, .data[0] = 0x00, .data[1] = 0x00,
1583 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1584 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1585 { .channel = 116, .freq = 5580, .data[0] = 0x00, .data[1] = 0x00,
1586 .data[2] = 0x00, .data[3] = 0x10, .data[4] = 0x3C, .data[5] = 0x77,
1587 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1588 { .channel = 120, .freq = 5600, .data[0] = 0x00, .data[1] = 0x00,
1589 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1590 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1591 { .channel = 124, .freq = 5620, .data[0] = 0x00, .data[1] = 0x00,
1592 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1593 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1594 { .channel = 128, .freq = 5640, .data[0] = 0x00, .data[1] = 0x00,
1595 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1596 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1597 { .channel = 132, .freq = 5660, .data[0] = 0x00, .data[1] = 0x00,
1598 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1599 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1600 { .channel = 136, .freq = 5680, .data[0] = 0x00, .data[1] = 0x00,
1601 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1602 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1603 { .channel = 140, .freq = 5700, .data[0] = 0x00, .data[1] = 0x00,
1604 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1605 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1606 { .channel = 149, .freq = 5745, .data[0] = 0x00, .data[1] = 0x00,
1607 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1608 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1609 { .channel = 153, .freq = 5765, .data[0] = 0x00, .data[1] = 0x00,
1610 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1611 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1612 { .channel = 157, .freq = 5785, .data[0] = 0x00, .data[1] = 0x00,
1613 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1614 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1615 { .channel = 161, .freq = 5805, .data[0] = 0x00, .data[1] = 0x00,
1616 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1617 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1618 { .channel = 165, .freq = 5825, .data[0] = 0x00, .data[1] = 0x00,
1619 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1620 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1621 { .channel = 184, .freq = 4920, .data[0] = 0x55, .data[1] = 0x77,
1622 .data[2] = 0x90, .data[3] = 0xF7, .data[4] = 0x3C, .data[5] = 0x77,
1623 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1624 { .channel = 188, .freq = 4940, .data[0] = 0x44, .data[1] = 0x77,
1625 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1626 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1627 { .channel = 192, .freq = 4960, .data[0] = 0x44, .data[1] = 0x66,
1628 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1629 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1630 { .channel = 196, .freq = 4980, .data[0] = 0x33, .data[1] = 0x66,
1631 .data[2] = 0x70, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1632 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1633 { .channel = 200, .freq = 5000, .data[0] = 0x22, .data[1] = 0x55,
1634 .data[2] = 0x60, .data[3] = 0xD7, .data[4] = 0x3C, .data[5] = 0x77,
1635 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1636 { .channel = 204, .freq = 5020, .data[0] = 0x22, .data[1] = 0x55,
1637 .data[2] = 0x60, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1638 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1639 { .channel = 208, .freq = 5040, .data[0] = 0x22, .data[1] = 0x44,
1640 .data[2] = 0x50, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1641 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1642 { .channel = 212, .freq = 5060, .data[0] = 0x11, .data[1] = 0x44,
1643 .data[2] = 0x50, .data[3] = 0xA5, .data[4] = 0x3C, .data[5] = 0x77,
1644 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1645 { .channel = 216, .freq = 5080, .data[0] = 0x00, .data[1] = 0x44,
1646 .data[2] = 0x40, .data[3] = 0xB6, .data[4] = 0x3C, .data[5] = 0x77,
1647 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1648};
1649
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]1650static const struct b206x_channel b2063_chantbl[] = {
1651 { .channel = 1, .freq = 2412, .data[0] = 0x6F, .data[1] = 0x3C,
1652 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1653 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1654 .data[10] = 0x80, .data[11] = 0x70, },
1655 { .channel = 2, .freq = 2417, .data[0] = 0x6F, .data[1] = 0x3C,
1656 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1657 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1658 .data[10] = 0x80, .data[11] = 0x70, },
1659 { .channel = 3, .freq = 2422, .data[0] = 0x6F, .data[1] = 0x3C,
1660 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1661 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1662 .data[10] = 0x80, .data[11] = 0x70, },
1663 { .channel = 4, .freq = 2427, .data[0] = 0x6F, .data[1] = 0x2C,
1664 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1665 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1666 .data[10] = 0x80, .data[11] = 0x70, },
1667 { .channel = 5, .freq = 2432, .data[0] = 0x6F, .data[1] = 0x2C,
1668 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1669 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1670 .data[10] = 0x80, .data[11] = 0x70, },
1671 { .channel = 6, .freq = 2437, .data[0] = 0x6F, .data[1] = 0x2C,
1672 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1673 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1674 .data[10] = 0x80, .data[11] = 0x70, },
1675 { .channel = 7, .freq = 2442, .data[0] = 0x6F, .data[1] = 0x2C,
1676 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1677 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1678 .data[10] = 0x80, .data[11] = 0x70, },
1679 { .channel = 8, .freq = 2447, .data[0] = 0x6F, .data[1] = 0x2C,
1680 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1681 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1682 .data[10] = 0x80, .data[11] = 0x70, },
1683 { .channel = 9, .freq = 2452, .data[0] = 0x6F, .data[1] = 0x1C,
1684 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1685 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1686 .data[10] = 0x80, .data[11] = 0x70, },
1687 { .channel = 10, .freq = 2457, .data[0] = 0x6F, .data[1] = 0x1C,
1688 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1689 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1690 .data[10] = 0x80, .data[11] = 0x70, },
1691 { .channel = 11, .freq = 2462, .data[0] = 0x6E, .data[1] = 0x1C,
1692 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1693 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1694 .data[10] = 0x80, .data[11] = 0x70, },
1695 { .channel = 12, .freq = 2467, .data[0] = 0x6E, .data[1] = 0x1C,
1696 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1697 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1698 .data[10] = 0x80, .data[11] = 0x70, },
1699 { .channel = 13, .freq = 2472, .data[0] = 0x6E, .data[1] = 0x1C,
1700 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1701 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1702 .data[10] = 0x80, .data[11] = 0x70, },
1703 { .channel = 14, .freq = 2484, .data[0] = 0x6E, .data[1] = 0x0C,
1704 .data[2] = 0x0C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1705 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1706 .data[10] = 0x80, .data[11] = 0x70, },
1707 { .channel = 34, .freq = 5170, .data[0] = 0x6A, .data[1] = 0x0C,
1708 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x02, .data[5] = 0x05,
1709 .data[6] = 0x0D, .data[7] = 0x0D, .data[8] = 0x77, .data[9] = 0x80,
1710 .data[10] = 0x20, .data[11] = 0x00, },
1711 { .channel = 36, .freq = 5180, .data[0] = 0x6A, .data[1] = 0x0C,
1712 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x05,
1713 .data[6] = 0x0D, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1714 .data[10] = 0x20, .data[11] = 0x00, },
1715 { .channel = 38, .freq = 5190, .data[0] = 0x6A, .data[1] = 0x0C,
1716 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1717 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1718 .data[10] = 0x20, .data[11] = 0x00, },
1719 { .channel = 40, .freq = 5200, .data[0] = 0x69, .data[1] = 0x0C,
1720 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1721 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1722 .data[10] = 0x20, .data[11] = 0x00, },
1723 { .channel = 42, .freq = 5210, .data[0] = 0x69, .data[1] = 0x0C,
1724 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1725 .data[6] = 0x0B, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1726 .data[10] = 0x20, .data[11] = 0x00, },
1727 { .channel = 44, .freq = 5220, .data[0] = 0x69, .data[1] = 0x0C,
1728 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x04,
1729 .data[6] = 0x0B, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1730 .data[10] = 0x20, .data[11] = 0x00, },
1731 { .channel = 46, .freq = 5230, .data[0] = 0x69, .data[1] = 0x0C,
1732 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1733 .data[6] = 0x0A, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1734 .data[10] = 0x20, .data[11] = 0x00, },
1735 { .channel = 48, .freq = 5240, .data[0] = 0x69, .data[1] = 0x0C,
1736 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1737 .data[6] = 0x0A, .data[7] = 0x0A, .data[8] = 0x77, .data[9] = 0x60,
1738 .data[10] = 0x20, .data[11] = 0x00, },
1739 { .channel = 52, .freq = 5260, .data[0] = 0x68, .data[1] = 0x0C,
1740 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x02,
1741 .data[6] = 0x09, .data[7] = 0x09, .data[8] = 0x77, .data[9] = 0x60,
1742 .data[10] = 0x20, .data[11] = 0x00, },
1743 { .channel = 56, .freq = 5280, .data[0] = 0x68, .data[1] = 0x0C,
1744 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1745 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1746 .data[10] = 0x10, .data[11] = 0x00, },
1747 { .channel = 60, .freq = 5300, .data[0] = 0x68, .data[1] = 0x0C,
1748 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1749 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1750 .data[10] = 0x10, .data[11] = 0x00, },
1751 { .channel = 64, .freq = 5320, .data[0] = 0x67, .data[1] = 0x0C,
1752 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1753 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1754 .data[10] = 0x10, .data[11] = 0x00, },
1755 { .channel = 100, .freq = 5500, .data[0] = 0x64, .data[1] = 0x0C,
1756 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1757 .data[6] = 0x02, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1758 .data[10] = 0x00, .data[11] = 0x00, },
1759 { .channel = 104, .freq = 5520, .data[0] = 0x64, .data[1] = 0x0C,
1760 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1761 .data[6] = 0x01, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1762 .data[10] = 0x00, .data[11] = 0x00, },
1763 { .channel = 108, .freq = 5540, .data[0] = 0x63, .data[1] = 0x0C,
1764 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1765 .data[6] = 0x01, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1766 .data[10] = 0x00, .data[11] = 0x00, },
1767 { .channel = 112, .freq = 5560, .data[0] = 0x63, .data[1] = 0x0C,
1768 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1769 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1770 .data[10] = 0x00, .data[11] = 0x00, },
1771 { .channel = 116, .freq = 5580, .data[0] = 0x62, .data[1] = 0x0C,
1772 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1773 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1774 .data[10] = 0x00, .data[11] = 0x00, },
1775 { .channel = 120, .freq = 5600, .data[0] = 0x62, .data[1] = 0x0C,
1776 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1777 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1778 .data[10] = 0x00, .data[11] = 0x00, },
1779 { .channel = 124, .freq = 5620, .data[0] = 0x62, .data[1] = 0x0C,
1780 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1781 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1782 .data[10] = 0x00, .data[11] = 0x00, },
1783 { .channel = 128, .freq = 5640, .data[0] = 0x61, .data[1] = 0x0C,
1784 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1785 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1786 .data[10] = 0x00, .data[11] = 0x00, },
1787 { .channel = 132, .freq = 5660, .data[0] = 0x61, .data[1] = 0x0C,
1788 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1789 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1790 .data[10] = 0x00, .data[11] = 0x00, },
1791 { .channel = 136, .freq = 5680, .data[0] = 0x61, .data[1] = 0x0C,
1792 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1793 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1794 .data[10] = 0x00, .data[11] = 0x00, },
1795 { .channel = 140, .freq = 5700, .data[0] = 0x60, .data[1] = 0x0C,
1796 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1797 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1798 .data[10] = 0x00, .data[11] = 0x00, },
1799 { .channel = 149, .freq = 5745, .data[0] = 0x60, .data[1] = 0x0C,
1800 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1801 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1802 .data[10] = 0x00, .data[11] = 0x00, },
1803 { .channel = 153, .freq = 5765, .data[0] = 0x60, .data[1] = 0x0C,
1804 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1805 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1806 .data[10] = 0x00, .data[11] = 0x00, },
1807 { .channel = 157, .freq = 5785, .data[0] = 0x60, .data[1] = 0x0C,
1808 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1809 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1810 .data[10] = 0x00, .data[11] = 0x00, },
1811 { .channel = 161, .freq = 5805, .data[0] = 0x60, .data[1] = 0x0C,
1812 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1813 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1814 .data[10] = 0x00, .data[11] = 0x00, },
1815 { .channel = 165, .freq = 5825, .data[0] = 0x60, .data[1] = 0x0C,
1816 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1817 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1818 .data[10] = 0x00, .data[11] = 0x00, },
1819 { .channel = 184, .freq = 4920, .data[0] = 0x6E, .data[1] = 0x0C,
1820 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0E,
1821 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xC0,
1822 .data[10] = 0x50, .data[11] = 0x00, },
1823 { .channel = 188, .freq = 4940, .data[0] = 0x6E, .data[1] = 0x0C,
1824 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0D,
1825 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1826 .data[10] = 0x50, .data[11] = 0x00, },
1827 { .channel = 192, .freq = 4960, .data[0] = 0x6E, .data[1] = 0x0C,
1828 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1829 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1830 .data[10] = 0x50, .data[11] = 0x00, },
1831 { .channel = 196, .freq = 4980, .data[0] = 0x6D, .data[1] = 0x0C,
1832 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1833 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1834 .data[10] = 0x40, .data[11] = 0x00, },
1835 { .channel = 200, .freq = 5000, .data[0] = 0x6D, .data[1] = 0x0C,
1836 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0B,
1837 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1838 .data[10] = 0x40, .data[11] = 0x00, },
1839 { .channel = 204, .freq = 5020, .data[0] = 0x6D, .data[1] = 0x0C,
1840 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0A,
1841 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1842 .data[10] = 0x40, .data[11] = 0x00, },
1843 { .channel = 208, .freq = 5040, .data[0] = 0x6C, .data[1] = 0x0C,
1844 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x07, .data[5] = 0x09,
1845 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1846 .data[10] = 0x40, .data[11] = 0x00, },
1847 { .channel = 212, .freq = 5060, .data[0] = 0x6C, .data[1] = 0x0C,
1848 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x06, .data[5] = 0x08,
1849 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1850 .data[10] = 0x40, .data[11] = 0x00, },
1851 { .channel = 216, .freq = 5080, .data[0] = 0x6C, .data[1] = 0x0C,
1852 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x05, .data[5] = 0x08,
1853 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1854 .data[10] = 0x40, .data[11] = 0x00, },
1855};
1856
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]1857static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev)
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]1858{
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]1859 struct ssb_bus *bus = dev->dev->bus;
1860
1861 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF);
1862 udelay(20);
1863 if (bus->chip_id == 0x5354) {
1864 b43_radio_write(dev, B2062_N_COMM1, 4);
1865 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4);
1866 } else {
1867 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0);
1868 }
1869 udelay(5);
1870}
1871
1872static void lpphy_b2062_vco_calib(struct b43_wldev *dev)
1873{
1874 b43_phy_write(dev, B2062_S_RFPLL_CTL21, 0x42);
1875 b43_phy_write(dev, B2062_S_RFPLL_CTL21, 0x62);
1876 udelay(200);
1877}
1878
1879static int lpphy_b2062_tune(struct b43_wldev *dev,
1880 unsigned int channel)
1881{
1882 struct b43_phy_lp *lpphy = dev->phy.lp;
1883 struct ssb_bus *bus = dev->dev->bus;
1884 static const struct b206x_channel *chandata = NULL;
1885 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1886 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9;
1887 int i, err = 0;
1888
1889 for (i = 0; i < ARRAY_SIZE(b2063_chantbl); i++) {
1890 if (b2063_chantbl[i].channel == channel) {
1891 chandata = &b2063_chantbl[i];
1892 break;
1893 }
1894 }
1895
1896 if (B43_WARN_ON(!chandata))
1897 return -EINVAL;
1898
1899 b43_radio_set(dev, B2062_S_RFPLL_CTL14, 0x04);
1900 b43_radio_write(dev, B2062_N_LGENA_TUNE0, chandata->data[0]);
1901 b43_radio_write(dev, B2062_N_LGENA_TUNE2, chandata->data[1]);
1902 b43_radio_write(dev, B2062_N_LGENA_TUNE3, chandata->data[2]);
1903 b43_radio_write(dev, B2062_N_TX_TUNE, chandata->data[3]);
1904 b43_radio_write(dev, B2062_S_LGENG_CTL1, chandata->data[4]);
1905 b43_radio_write(dev, B2062_N_LGENA_CTL5, chandata->data[5]);
1906 b43_radio_write(dev, B2062_N_LGENA_CTL6, chandata->data[6]);
1907 b43_radio_write(dev, B2062_N_TX_PGA, chandata->data[7]);
1908 b43_radio_write(dev, B2062_N_TX_PAD, chandata->data[8]);
1909
1910 tmp1 = crystal_freq / 1000;
1911 tmp2 = lpphy->pdiv * 1000;
1912 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xCC);
1913 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0x07);
1914 lpphy_b2062_reset_pll_bias(dev);
1915 tmp3 = tmp2 * channel2freq_lp(channel);
1916 if (channel2freq_lp(channel) < 4000)
1917 tmp3 *= 2;
1918 tmp4 = 48 * tmp1;
1919 tmp6 = tmp3 / tmp4;
1920 tmp7 = tmp3 % tmp4;
1921 b43_radio_write(dev, B2062_S_RFPLL_CTL26, tmp6);
1922 tmp5 = tmp7 * 0x100;
1923 tmp6 = tmp5 / tmp4;
1924 tmp7 = tmp5 % tmp4;
Gábor Stefanik055114a2009-08-16 15:32:40 +0200[diff] [blame^]1925 b43_radio_write(dev, B2062_S_RFPLL_CTL27, tmp6);
1926 tmp5 = tmp7 * 0x100;
1927 tmp6 = tmp5 / tmp4;
1928 tmp7 = tmp5 % tmp4;
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]1929 b43_radio_write(dev, B2062_S_RFPLL_CTL28, tmp6);
1930 tmp5 = tmp7 * 0x100;
1931 tmp6 = tmp5 / tmp4;
1932 tmp7 = tmp5 % tmp4;
1933 b43_radio_write(dev, B2062_S_RFPLL_CTL29, tmp6 + ((2 * tmp7) / tmp4));
1934 tmp8 = b43_phy_read(dev, B2062_S_RFPLL_CTL19);
1935 tmp9 = ((2 * tmp3 * (tmp8 + 1)) + (3 * tmp1)) / (6 * tmp1);
1936 b43_radio_write(dev, B2062_S_RFPLL_CTL23, tmp9 >> 8);
1937 b43_radio_write(dev, B2062_S_RFPLL_CTL24, tmp9 & 0xFF);
1938
1939 lpphy_b2062_vco_calib(dev);
1940 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10) {
1941 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xFC);
1942 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0);
1943 lpphy_b2062_reset_pll_bias(dev);
1944 lpphy_b2062_vco_calib(dev);
1945 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10)
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]1946 err = -EIO;
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]1947 }
1948
1949 b43_radio_mask(dev, B2062_S_RFPLL_CTL14, ~0x04);
1950 return err;
1951}
1952
1953static void lpphy_japan_filter(struct b43_wldev *dev, int channel)
1954{
1955 struct b43_phy_lp *lpphy = dev->phy.lp;
1956 u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
1957
1958 if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
1959 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
1960 if ((dev->phy.rev == 1) && (lpphy->rc_cap))
1961 lpphy_set_rc_cap(dev);
1962 } else {
1963 b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
1964 }
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]1965}
1966
1967static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
1968{
1969 u16 tmp;
1970
1971 b43_phy_mask(dev, B2063_PLL_SP1, ~0x40);
1972 tmp = b43_phy_read(dev, B2063_PLL_JTAG_CALNRST) & 0xF8;
1973 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp);
1974 udelay(1);
1975 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x4);
1976 udelay(1);
1977 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x6);
1978 udelay(1);
1979 b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x7);
1980 udelay(300);
1981 b43_phy_set(dev, B2063_PLL_SP1, 0x40);
1982}
1983
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]1984static int lpphy_b2063_tune(struct b43_wldev *dev,
1985 unsigned int channel)
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]1986{
1987 struct ssb_bus *bus = dev->dev->bus;
1988
1989 static const struct b206x_channel *chandata = NULL;
1990 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1991 u32 freqref, vco_freq, val1, val2, val3, timeout, timeoutref, count;
1992 u16 old_comm15, scale;
1993 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
1994 int i, div = (crystal_freq <= 26000000 ? 1 : 2);
1995
1996 for (i = 0; i < ARRAY_SIZE(b2063_chantbl); i++) {
1997 if (b2063_chantbl[i].channel == channel) {
1998 chandata = &b2063_chantbl[i];
1999 break;
2000 }
2001 }
2002
2003 if (B43_WARN_ON(!chandata))
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]2004 return -EINVAL;
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2005
2006 b43_radio_write(dev, B2063_LOGEN_VCOBUF1, chandata->data[0]);
2007 b43_radio_write(dev, B2063_LOGEN_MIXER2, chandata->data[1]);
2008 b43_radio_write(dev, B2063_LOGEN_BUF2, chandata->data[2]);
2009 b43_radio_write(dev, B2063_LOGEN_RCCR1, chandata->data[3]);
2010 b43_radio_write(dev, B2063_A_RX_1ST3, chandata->data[4]);
2011 b43_radio_write(dev, B2063_A_RX_2ND1, chandata->data[5]);
2012 b43_radio_write(dev, B2063_A_RX_2ND4, chandata->data[6]);
2013 b43_radio_write(dev, B2063_A_RX_2ND7, chandata->data[7]);
2014 b43_radio_write(dev, B2063_A_RX_PS6, chandata->data[8]);
2015 b43_radio_write(dev, B2063_TX_RF_CTL2, chandata->data[9]);
2016 b43_radio_write(dev, B2063_TX_RF_CTL5, chandata->data[10]);
2017 b43_radio_write(dev, B2063_PA_CTL11, chandata->data[11]);
2018
2019 old_comm15 = b43_radio_read(dev, B2063_COMM15);
2020 b43_radio_set(dev, B2063_COMM15, 0x1E);
2021
2022 if (chandata->freq > 4000) /* spec says 2484, but 4000 is safer */
2023 vco_freq = chandata->freq << 1;
2024 else
2025 vco_freq = chandata->freq << 2;
2026
2027 freqref = crystal_freq * 3;
2028 val1 = lpphy_qdiv_roundup(crystal_freq, 1000000, 16);
2029 val2 = lpphy_qdiv_roundup(crystal_freq, 1000000 * div, 16);
2030 val3 = lpphy_qdiv_roundup(vco_freq, 3, 16);
2031 timeout = ((((8 * crystal_freq) / (div * 5000000)) + 1) >> 1) - 1;
2032 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB3, 0x2);
2033 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB6,
2034 0xFFF8, timeout >> 2);
2035 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2036 0xFF9F,timeout << 5);
2037
2038 timeoutref = ((((8 * crystal_freq) / (div * (timeout + 1))) +
2039 999999) / 1000000) + 1;
2040 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB5, timeoutref);
2041
2042 count = lpphy_qdiv_roundup(val3, val2 + 16, 16);
2043 count *= (timeout + 1) * (timeoutref + 1);
2044 count--;
2045 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2046 0xF0, count >> 8);
2047 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB8, count & 0xFF);
2048
2049 tmp1 = ((val3 * 62500) / freqref) << 4;
2050 tmp2 = ((val3 * 62500) % freqref) << 4;
2051 while (tmp2 >= freqref) {
2052 tmp1++;
2053 tmp2 -= freqref;
2054 }
2055 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG1, 0xFFE0, tmp1 >> 4);
2056 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFE0F, tmp1 << 4);
2057 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFFF0, tmp1 >> 16);
2058 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG3, (tmp2 >> 8) & 0xFF);
2059 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG4, tmp2 & 0xFF);
2060
2061 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF1, 0xB9);
2062 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF2, 0x88);
2063 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF3, 0x28);
2064 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF4, 0x63);
2065
2066 tmp3 = ((41 * (val3 - 3000)) /1200) + 27;
2067 tmp4 = lpphy_qdiv_roundup(132000 * tmp1, 8451, 16);
2068
2069 if ((tmp4 + tmp3 - 1) / tmp3 > 60) {
2070 scale = 1;
2071 tmp5 = ((tmp4 + tmp3) / (tmp3 << 1)) - 8;
2072 } else {
2073 scale = 0;
2074 tmp5 = ((tmp4 + (tmp3 >> 1)) / tmp3) - 8;
2075 }
2076 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFC0, tmp5);
2077 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFBF, scale << 6);
2078
2079 tmp6 = lpphy_qdiv_roundup(100 * val1, val3, 16);
2080 tmp6 *= (tmp5 * 8) * (scale + 1);
2081 if (tmp6 > 150)
2082 tmp6 = 0;
2083
2084 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFE0, tmp6);
2085 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFDF, scale << 5);
2086
2087 b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFFFB, 0x4);
2088 if (crystal_freq > 26000000)
2089 b43_phy_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2);
2090 else
2091 b43_phy_mask(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFD);
2092
2093 if (val1 == 45)
2094 b43_phy_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2);
2095 else
2096 b43_phy_mask(dev, B2063_PLL_JTAG_PLL_VCO1, 0xFD);
2097
2098 b43_phy_set(dev, B2063_PLL_SP2, 0x3);
2099 udelay(1);
2100 b43_phy_mask(dev, B2063_PLL_SP2, 0xFFFC);
2101 lpphy_b2063_vco_calib(dev);
2102 b43_radio_write(dev, B2063_COMM15, old_comm15);
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]2103
2104 return 0;
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2105}
2106
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2107static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
2108 unsigned int new_channel)
2109{
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]2110 int err;
2111
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2112 b43_write16(dev, B43_MMIO_CHANNEL, new_channel);
2113
2114 if (dev->phy.radio_ver == 0x2063) {
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]2115 err = lpphy_b2063_tune(dev, new_channel);
2116 if (err)
2117 return err;
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2118 } else {
Gábor Stefanik1e711be2009-08-14 00:15:17 +0200[diff] [blame]2119 err = lpphy_b2062_tune(dev, new_channel);
2120 if (err)
2121 return err;
2122 lpphy_japan_filter(dev, new_channel);
Gábor Stefanik0c61bb92009-08-14 21:11:59 +0200[diff] [blame]2123 lpphy_adjust_gain_table(dev, channel2freq_lp(new_channel));
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2124 }
2125
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2126 return 0;
2127}
2128
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2129static int b43_lpphy_op_init(struct b43_wldev *dev)
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2130{
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]2131 int err;
2132
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2133 lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs?
2134 lpphy_baseband_init(dev);
2135 lpphy_radio_init(dev);
2136 lpphy_calibrate_rc(dev);
Gábor Stefanik96909e92009-08-16 01:15:49 +0200[diff] [blame]2137 err = b43_lpphy_op_switch_channel(dev,
2138 b43_lpphy_op_get_default_chan(dev));
2139 if (err) {
2140 b43dbg(dev->wl, "Switch to init channel failed, error = %d.\n",
2141 err);
2142 }
Gábor Stefanik588f8372009-08-13 22:46:30 +0200[diff] [blame]2143 lpphy_tx_pctl_init(dev);
2144 lpphy_calibration(dev);
2145 //TODO ACI init
2146
2147 return 0;
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2148}
2149
2150static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2151{
2152 //TODO
2153}
2154
2155static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
2156{
2157 //TODO
2158}
2159
2160static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
2161 bool ignore_tssi)
2162{
2163 //TODO
2164 return B43_TXPWR_RES_DONE;
2165}
2166
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2167const struct b43_phy_operations b43_phyops_lp = {
2168 .allocate = b43_lpphy_op_allocate,
Michael Bueschfb111372008-09-02 13:00:34 +0200[diff] [blame]2169 .free = b43_lpphy_op_free,
2170 .prepare_structs = b43_lpphy_op_prepare_structs,
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2171 .init = b43_lpphy_op_init,
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2172 .phy_read = b43_lpphy_op_read,
2173 .phy_write = b43_lpphy_op_write,
2174 .radio_read = b43_lpphy_op_radio_read,
2175 .radio_write = b43_lpphy_op_radio_write,
2176 .software_rfkill = b43_lpphy_op_software_rfkill,
Michael Bueschcb24f572008-09-03 12:12:20 +0200[diff] [blame]2177 .switch_analog = b43_phyop_switch_analog_generic,
Michael Buesche63e4362008-08-30 10:55:48 +0200[diff] [blame]2178 .switch_channel = b43_lpphy_op_switch_channel,
2179 .get_default_chan = b43_lpphy_op_get_default_chan,
2180 .set_rx_antenna = b43_lpphy_op_set_rx_antenna,
2181 .recalc_txpower = b43_lpphy_op_recalc_txpower,
2182 .adjust_txpower = b43_lpphy_op_adjust_txpower,
2183};